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Missing AArch64ISD::BICi handling
1 parent c664a51 commit 00fd477

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3 files changed

+156
-2
lines changed

3 files changed

+156
-2
lines changed

‎llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

+7-2
Original file line numberDiff line numberDiff line change
@@ -3390,10 +3390,15 @@ KnownBits SelectionDAG::computeKnownBits(SDValue Op, const APInt &DemandedElts,
33903390
Known = KnownBits::mulhs(Known, Known2);
33913391
break;
33923392
}
3393-
case ISD::AVGCEILU: {
3393+
case ISD::AVGFLOORU:
3394+
case ISD::AVGCEILU:
3395+
case ISD::AVGFLOORS:
3396+
case ISD::AVGCEILS: {
33943397
Known = computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1);
33953398
Known2 = computeKnownBits(Op.getOperand(1), DemandedElts, Depth + 1);
3396-
Known = Known.zext(BitWidth + 1);
3399+
Known = (Opcode == ISD::AVGFLOORU || Opcode == ISD::AVGCEILU)
3400+
? Known.zext(BitWidth + 1)
3401+
: Known.sext(BitWidth + 1);
33973402
Known2 = Known2.zext(BitWidth + 1);
33983403
KnownBits One = KnownBits::makeConstant(APInt(1, 1));
33993404
Known = KnownBits::computeForAddCarry(Known, Known2, One);

‎llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

+24
Original file line numberDiff line numberDiff line change
@@ -23672,6 +23672,18 @@ SDValue AArch64TargetLowering::PerformDAGCombine(SDNode *N,
2367223672
if (auto R = foldOverflowCheck(N, DAG, /* IsAdd */ false))
2367323673
return R;
2367423674
return performFlagSettingCombine(N, DCI, AArch64ISD::SBC);
23675+
case AArch64ISD::BICi: {
23676+
KnownBits Known;
23677+
APInt DemandedElts(32, N->getValueType(0).getVectorNumElements());
23678+
APInt EltSize(32, N->getValueType(0).getScalarSizeInBits());
23679+
TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
23680+
!DCI.isBeforeLegalizeOps());
23681+
if (SimplifyDemandedBitsForTargetNode(SDValue(N, 0), EltSize, DemandedElts,
23682+
Known, TLO, 0)) {
23683+
return TLO.New;
23684+
}
23685+
break;
23686+
}
2367523687
case ISD::XOR:
2367623688
return performXorCombine(N, DAG, DCI, Subtarget);
2367723689
case ISD::MUL:
@@ -26658,6 +26670,18 @@ bool AArch64TargetLowering::SimplifyDemandedBitsForTargetNode(
2665826670
// used - simplify to just Val.
2665926671
return TLO.CombineTo(Op, ShiftR->getOperand(0));
2666026672
}
26673+
case AArch64ISD::BICi: {
26674+
// Fold BICi if all destination bits already known to be zeroed
26675+
SDValue Op0 = Op.getOperand(0);
26676+
KnownBits KnownOp0 = TLO.DAG.computeKnownBits(Op0, 0);
26677+
APInt Shift = Op.getConstantOperandAPInt(2);
26678+
APInt Op1Val = Op.getConstantOperandAPInt(1);
26679+
APInt BitsToClear = Op1Val.shl(Shift).zextOrTrunc(KnownOp0.getBitWidth());
26680+
APInt AlreadyZeroedBitsToClear = BitsToClear & KnownOp0.Zero;
26681+
if (AlreadyZeroedBitsToClear == BitsToClear)
26682+
return TLO.CombineTo(Op, Op0);
26683+
return false;
26684+
}
2666126685
case ISD::INTRINSIC_WO_CHAIN: {
2666226686
if (auto ElementSize = IsSVECntIntrinsic(Op)) {
2666326687
unsigned MaxSVEVectorSizeInBits = Subtarget->getMaxSVEVectorSizeInBits();

‎llvm/test/CodeGen/AArch64/aarch64-neon-bici.ll

+125
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,125 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
2+
; RUN: llc -mtriple=aarch64-neon < %s | FileCheck %s
3+
4+
declare <8 x i16> @llvm.aarch64.neon.uhadd.v8i16(<8 x i16>, <8 x i16>)
5+
declare <8 x i16> @llvm.aarch64.neon.urhadd.v8i16(<8 x i16>, <8 x i16>)
6+
declare <8 x i16> @llvm.aarch64.neon.shadd.v8i16(<8 x i16>, <8 x i16>)
7+
declare <8 x i16> @llvm.aarch64.neon.srhadd.v8i16(<8 x i16>, <8 x i16>)
8+
9+
define <8 x i16> @haddu_zext(<8 x i8> %a0, <8 x i8> %a1) {
10+
; CHECK-LABEL: haddu_zext:
11+
; CHECK: // %bb.0:
12+
; CHECK-NEXT: ushll v0.8h, v0.8b, #0
13+
; CHECK-NEXT: ushll v1.8h, v1.8b, #0
14+
; CHECK-NEXT: uhadd v0.8h, v0.8h, v1.8h
15+
; CHECK-NEXT: ret
16+
%x0 = zext <8 x i8> %a0 to <8 x i16>
17+
%x1 = zext <8 x i8> %a1 to <8 x i16>
18+
%hadd = call <8 x i16> @llvm.aarch64.neon.uhadd.v8i16(<8 x i16> %x0, <8 x i16> %x1)
19+
%res = and <8 x i16> %hadd, <i16 511, i16 511, i16 511, i16 511,i16 511, i16 511, i16 511, i16 511>
20+
ret <8 x i16> %res
21+
}
22+
23+
define <8 x i16> @rhaddu_zext(<8 x i8> %a0, <8 x i8> %a1) {
24+
; CHECK-LABEL: rhaddu_zext:
25+
; CHECK: // %bb.0:
26+
; CHECK-NEXT: ushll v0.8h, v0.8b, #0
27+
; CHECK-NEXT: ushll v1.8h, v1.8b, #0
28+
; CHECK-NEXT: urhadd v0.8h, v0.8h, v1.8h
29+
; CHECK-NEXT: ret
30+
%x0 = zext <8 x i8> %a0 to <8 x i16>
31+
%x1 = zext <8 x i8> %a1 to <8 x i16>
32+
%hadd = call <8 x i16> @llvm.aarch64.neon.urhadd.v8i16(<8 x i16> %x0, <8 x i16> %x1)
33+
%res = and <8 x i16> %hadd, <i16 511, i16 511, i16 511, i16 511, i16 511, i16 511, i16 511, i16 511>
34+
ret <8 x i16> %res
35+
}
36+
37+
define <8 x i16> @hadds_zext(<8 x i8> %a0, <8 x i8> %a1) {
38+
; CHECK-LABEL: hadds_zext:
39+
; CHECK: // %bb.0:
40+
; CHECK-NEXT: ushll v0.8h, v0.8b, #0
41+
; CHECK-NEXT: ushll v1.8h, v1.8b, #0
42+
; CHECK-NEXT: shadd v0.8h, v0.8h, v1.8h
43+
; CHECK-NEXT: ret
44+
%x0 = zext <8 x i8> %a0 to <8 x i16>
45+
%x1 = zext <8 x i8> %a1 to <8 x i16>
46+
%hadd = call <8 x i16> @llvm.aarch64.neon.shadd.v8i16(<8 x i16> %x0, <8 x i16> %x1)
47+
%res = and <8 x i16> %hadd, <i16 511, i16 511, i16 511, i16 511, i16 511, i16 511, i16 511, i16 511>
48+
ret <8 x i16> %res
49+
}
50+
51+
define <8 x i16> @shaddu_zext(<8 x i8> %a0, <8 x i8> %a1) {
52+
; CHECK-LABEL: shaddu_zext:
53+
; CHECK: // %bb.0:
54+
; CHECK-NEXT: ushll v0.8h, v0.8b, #0
55+
; CHECK-NEXT: ushll v1.8h, v1.8b, #0
56+
; CHECK-NEXT: srhadd v0.8h, v0.8h, v1.8h
57+
; CHECK-NEXT: ret
58+
%x0 = zext <8 x i8> %a0 to <8 x i16>
59+
%x1 = zext <8 x i8> %a1 to <8 x i16>
60+
%hadd = call <8 x i16> @llvm.aarch64.neon.srhadd.v8i16(<8 x i16> %x0, <8 x i16> %x1)
61+
%res = and <8 x i16> %hadd, <i16 511, i16 511, i16 511, i16 511, i16 511, i16 511, i16 511, i16 511>
62+
ret <8 x i16> %res
63+
}
64+
65+
; ; negative tests
66+
67+
define <8 x i16> @haddu_sext(<8 x i8> %a0, <8 x i8> %a1) {
68+
; CHECK-LABEL: haddu_sext:
69+
; CHECK: // %bb.0:
70+
; CHECK-NEXT: sshll v0.8h, v0.8b, #0
71+
; CHECK-NEXT: sshll v1.8h, v1.8b, #0
72+
; CHECK-NEXT: uhadd v0.8h, v0.8h, v1.8h
73+
; CHECK-NEXT: bic v0.8h, #254, lsl #8
74+
; CHECK-NEXT: ret
75+
%x0 = sext <8 x i8> %a0 to <8 x i16>
76+
%x1 = sext <8 x i8> %a1 to <8 x i16>
77+
%hadd = call <8 x i16> @llvm.aarch64.neon.uhadd.v8i16(<8 x i16> %x0, <8 x i16> %x1)
78+
%res = and <8 x i16> %hadd, <i16 511, i16 511, i16 511, i16 511,i16 511, i16 511, i16 511, i16 511>
79+
ret <8 x i16> %res
80+
}
81+
82+
define <8 x i16> @urhadd_sext(<8 x i8> %a0, <8 x i8> %a1) {
83+
; CHECK-LABEL: urhadd_sext:
84+
; CHECK: // %bb.0:
85+
; CHECK-NEXT: sshll v0.8h, v0.8b, #0
86+
; CHECK-NEXT: sshll v1.8h, v1.8b, #0
87+
; CHECK-NEXT: urhadd v0.8h, v0.8h, v1.8h
88+
; CHECK-NEXT: bic v0.8h, #254, lsl #8
89+
; CHECK-NEXT: ret
90+
%x0 = sext <8 x i8> %a0 to <8 x i16>
91+
%x1 = sext <8 x i8> %a1 to <8 x i16>
92+
%hadd = call <8 x i16> @llvm.aarch64.neon.urhadd.v8i16(<8 x i16> %x0, <8 x i16> %x1)
93+
%res = and <8 x i16> %hadd, <i16 511, i16 511, i16 511, i16 511,i16 511, i16 511, i16 511, i16 511>
94+
ret <8 x i16> %res
95+
}
96+
97+
define <8 x i16> @hadds_sext(<8 x i8> %a0, <8 x i8> %a1) {
98+
; CHECK-LABEL: hadds_sext:
99+
; CHECK: // %bb.0:
100+
; CHECK-NEXT: sshll v0.8h, v0.8b, #0
101+
; CHECK-NEXT: sshll v1.8h, v1.8b, #0
102+
; CHECK-NEXT: shadd v0.8h, v0.8h, v1.8h
103+
; CHECK-NEXT: bic v0.8h, #254, lsl #8
104+
; CHECK-NEXT: ret
105+
%x0 = sext <8 x i8> %a0 to <8 x i16>
106+
%x1 = sext <8 x i8> %a1 to <8 x i16>
107+
%hadd = call <8 x i16> @llvm.aarch64.neon.shadd.v8i16(<8 x i16> %x0, <8 x i16> %x1)
108+
%res = and <8 x i16> %hadd, <i16 511, i16 511, i16 511, i16 511, i16 511, i16 511, i16 511, i16 511>
109+
ret <8 x i16> %res
110+
}
111+
112+
define <8 x i16> @shaddu_sext(<8 x i8> %a0, <8 x i8> %a1) {
113+
; CHECK-LABEL: shaddu_sext:
114+
; CHECK: // %bb.0:
115+
; CHECK-NEXT: sshll v0.8h, v0.8b, #0
116+
; CHECK-NEXT: sshll v1.8h, v1.8b, #0
117+
; CHECK-NEXT: srhadd v0.8h, v0.8h, v1.8h
118+
; CHECK-NEXT: bic v0.8h, #254, lsl #8
119+
; CHECK-NEXT: ret
120+
%x0 = sext <8 x i8> %a0 to <8 x i16>
121+
%x1 = sext <8 x i8> %a1 to <8 x i16>
122+
%hadd = call <8 x i16> @llvm.aarch64.neon.srhadd.v8i16(<8 x i16> %x0, <8 x i16> %x1)
123+
%res = and <8 x i16> %hadd, <i16 511, i16 511, i16 511, i16 511, i16 511, i16 511, i16 511, i16 511>
124+
ret <8 x i16> %res
125+
}

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