[AMDGPU] Convert flat scratch SS->SV in FI elimination

- Fix O0 crash on gfx950 by remapping SS to SV and materializing the
offset in a VGPR when FrameReg is unavailable and no SGPR can be
scavenged. Resolves issue #155902
- Reuse existing VGPR temp if available; otherwise scavenge one.
- Add regression: llvm/test/CodeGen/AMDGPU/flat-scratch-ss-to-sv-scavenge.ll.

Co-authored by Matt Arsenault

Author: gandhi56

llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp

@@ -3183,8 +3183,42 @@ bool SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI,
                   : RS->scavengeRegisterBackwards(AMDGPU::SReg_32_XM0RegClass,
                                                   MI, false, 0, !UseSGPR);
 
-      // TODO: for flat scratch another attempt can be made with a VGPR index
-      //       if no SGPRs can be scavenged.
+      // Fallback: If we need an SGPR but cannot scavenge one and there is no
+      // frame register, try to convert the flat-scratch instruction to use a
+      // VGPR index (SS -> SV) and materialize the offset in a VGPR.
+      if (!TmpSReg && !FrameReg && TII->isFLATScratch(*MI)) {
+        // Reuse an existing VGPR temp if available, otherwise scavenge one.
+        Register VTmp = (!UseSGPR && TmpReg)
+                            ? TmpReg
+                            : RS->scavengeRegisterBackwards(
+                                  AMDGPU::VGPR_32RegClass, MI, false, 0);
+        if (VTmp) {
+          // Put the large offset into a VGPR and zero the immediate offset.
+          BuildMI(*MBB, MI, DL, TII->get(AMDGPU::V_MOV_B32_e32), VTmp)
+              .addImm(Offset);
+
+          unsigned Opc = MI->getOpcode();
+          int NewOpc = AMDGPU::getFlatScratchInstSVfromSS(Opc);
+          if (NewOpc != -1) {
+            int OldSAddrIdx =
+                AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::saddr);
+            int NewVAddrIdx =
+                AMDGPU::getNamedOperandIdx(NewOpc, AMDGPU::OpName::vaddr);
+            if (OldSAddrIdx == NewVAddrIdx && OldSAddrIdx >= 0) {
+              MI->setDesc(TII->get(NewOpc));
+              // Replace former saddr (now vaddr) with the VGPR index.
+              MI->getOperand(NewVAddrIdx).ChangeToRegister(VTmp, false);
+              // Reset the immediate offset to 0 as it is now in vaddr.
+              MachineOperand *OffOp =
+                  TII->getNamedOperand(*MI, AMDGPU::OpName::offset);
+              assert(OffOp && "Flat scratch SV form must have offset operand");
+              OffOp->setImm(0);
+              return false;
+            }
+          }
+        }
+      }
+
       if ((!TmpSReg && !FrameReg) || (!TmpReg && !UseSGPR))
         report_fatal_error("Cannot scavenge register in FI elimination!");