@@ -433,3 +433,167 @@ multiclass VMVm<string opcStr, bits<8>opc, RegisterClass RC,
433433 defm iv : VMVmm<opcStr, opc, RC, RCM, (ins uimm7:$sy, RC:$vz)>;
434434}
435435defm VMV : VMVm<"vmv", 0x9c, V64, VM>;
436+
437+ //-----------------------------------------------------------------------------
438+ // Section 8.10 - Vector Fixed-Point Arithmetic Instructions
439+ //-----------------------------------------------------------------------------
440+
441+ // Multiclass for generic vector calculation
442+ let vx = ?, hasSideEffects = 0, Uses = [VL] in
443+ multiclass RVbm<string opcStr, string argStr, bits<8>opc, RegisterClass RC,
444+ dag dag_in, string disEnc = ""> {
445+ let DisableEncoding = disEnc in
446+ def "" : RV<opc, (outs RC:$vx), dag_in,
447+ !strconcat(opcStr, " $vx", argStr)>;
448+ let Constraints = "$vx = $base", DisableEncoding = disEnc#"$base",
449+ isCodeGenOnly = 1 in
450+ def _v : RV<opc, (outs RC:$vx), !con(dag_in, (ins RC:$base)),
451+ !strconcat(opcStr, " $vx", argStr)>;
452+ }
453+ multiclass RVlm<string opcStr, string argStr, bits<8>opc, RegisterClass RC,
454+ dag dag_in> {
455+ defm "" : RVbm<opcStr, argStr, opc, RC, dag_in>;
456+ let isCodeGenOnly = 1, VE_VLInUse = 1 in {
457+ defm l : RVbm<opcStr, argStr, opc, RC, !con(dag_in, (ins I32:$vl)),
458+ "$vl,">;
459+ defm L : RVbm<opcStr, argStr, opc, RC, !con(dag_in, (ins VLS:$vl)),
460+ "$vl,">;
461+ }
462+ }
463+ multiclass RVmm<string opcStr, string argStr, bits<8>opc, RegisterClass RC,
464+ RegisterClass RCM, dag dag_in> {
465+ defm "" : RVlm<opcStr, argStr, opc, RC, dag_in>;
466+ let m = ?, VE_VLWithMask = 1 in
467+ defm m : RVlm<opcStr, argStr#", $m", opc, RC, !con(dag_in, (ins RCM:$m))>;
468+ }
469+ // Generic RV multiclass with 2 arguments.
470+ // e.g. VADD, VSUB, VMPY, and etc.
471+ let VE_VLIndex = 3 in
472+ multiclass RVm<string opcStr, bits<8>opc, RegisterClass VRC, RegisterClass RC,
473+ RegisterClass RCM, Operand SIMM = simm7> {
474+ let cy = 0, sy = 0, vy = ?, vz = ? in
475+ defm vv : RVmm<opcStr, ", $vy, $vz", opc, VRC, RCM, (ins VRC:$vy, VRC:$vz)>;
476+ let cs = 1, vz = ? in
477+ defm rv : RVmm<opcStr, ", $sy, $vz", opc, VRC, RCM, (ins RC:$sy, VRC:$vz)>;
478+ let cs = 1, cy = 0, vz = ? in
479+ defm iv : RVmm<opcStr, ", $sy, $vz", opc, VRC, RCM, (ins SIMM:$sy, VRC:$vz)>;
480+ }
481+ // Special RV multiclass with 2 arguments using cs2.
482+ // e.g. VDIV, VDVS, and VDVX.
483+ let VE_VLIndex = 3 in
484+ multiclass RVDIVm<string opcStr, bits<8>opc, RegisterClass VRC,
485+ RegisterClass RC, RegisterClass RCM, Operand SIMM = simm7> {
486+ let cy = 0, sy = 0, vy = ?, vz = ? in
487+ defm vv : RVmm<opcStr, ", $vy, $vz", opc, VRC, RCM, (ins VRC:$vy, VRC:$vz)>;
488+ let cs2 = 1, vy = ? in
489+ defm vr : RVmm<opcStr, ", $vy, $sy", opc, VRC, RCM, (ins VRC:$vy, RC:$sy)>;
490+ let cs2 = 1, cy = 0, vy = ? in
491+ defm vi : RVmm<opcStr, ", $vy, $sy", opc, VRC, RCM, (ins VRC:$vy, SIMM:$sy)>;
492+ let cs = 1, vz = ? in
493+ defm rv : RVmm<opcStr, ", $sy, $vz", opc, VRC, RCM, (ins RC:$sy, VRC:$vz)>;
494+ let cs = 1, cy = 0, vz = ? in
495+ defm iv : RVmm<opcStr, ", $sy, $vz", opc, VRC, RCM, (ins SIMM:$sy, VRC:$vz)>;
496+ }
497+
498+ // Section 8.10.1 - VADD (Vector Add)
499+ let cx = 0, cx2 = 0 in
500+ defm VADDUL : RVm<"vaddu.l", 0xc8, V64, I64, VM>;
501+ let cx = 0, cx2 = 1 in {
502+ defm PVADDULO : RVm<"pvaddu.lo", 0xc8, V64, I32, VM>;
503+ let isCodeGenOnly = 1 in
504+ defm VADDUW : RVm<"vaddu.w", 0xc8, V64, I32, VM>;
505+ }
506+ let cx = 1, cx2 = 0 in
507+ defm PVADDUUP : RVm<"pvaddu.up", 0xc8, V64, I64, VM>;
508+ let cx = 1, cx2 = 1 in
509+ defm PVADDU : RVm<"pvaddu", 0xc8, V64, I64, VM512>;
510+ def : MnemonicAlias<"vaddu.w", "pvaddu.lo">;
511+
512+ // Section 8.10.2 - VADS (Vector Add Single)
513+ let cx = 0, cx2 = 0 in
514+ defm VADDSWSX : RVm<"vadds.w.sx", 0xca, V64, I32, VM>;
515+ let cx = 0, cx2 = 1 in {
516+ defm PVADDSLO : RVm<"pvadds.lo", 0xca, V64, I32, VM>;
517+ let isCodeGenOnly = 1 in
518+ defm VADDSWZX : RVm<"vadds.w.zx", 0xca, V64, I32, VM>;
519+ }
520+ let cx = 1, cx2 = 0 in
521+ defm PVADDSUP : RVm<"pvadds.up", 0xca, V64, I64, VM>;
522+ let cx = 1, cx2 = 1 in
523+ defm PVADDS : RVm<"pvadds", 0xca, V64, I64, VM512>;
524+ def : MnemonicAlias<"pvadds.lo.sx", "vadds.w.sx">;
525+ def : MnemonicAlias<"vadds.w.zx", "pvadds.lo">;
526+ def : MnemonicAlias<"vadds.w", "pvadds.lo">;
527+ def : MnemonicAlias<"pvadds.lo.zx", "pvadds.lo">;
528+
529+ // Section 8.10.3 - VADX (Vector Add)
530+ defm VADDSL : RVm<"vadds.l", 0x8b, V64, I64, VM>;
531+
532+ // Section 8.10.4 - VSUB (Vector Subtract)
533+ let cx = 0, cx2 = 0 in
534+ defm VSUBUL : RVm<"vsubu.l", 0xd8, V64, I64, VM>;
535+ let cx = 0, cx2 = 1 in {
536+ defm PVSUBULO : RVm<"pvsubu.lo", 0xd8, V64, I32, VM>;
537+ let isCodeGenOnly = 1 in
538+ defm VSUBUW : RVm<"vsubu.w", 0xd8, V64, I32, VM>;
539+ }
540+ let cx = 1, cx2 = 0 in
541+ defm PVSUBUUP : RVm<"pvsubu.up", 0xd8, V64, I64, VM>;
542+ let cx = 1, cx2 = 1 in
543+ defm PVSUBU : RVm<"pvsubu", 0xd8, V64, I64, VM512>;
544+ def : MnemonicAlias<"vsubu.w", "pvsubu.lo">;
545+
546+ // Section 8.10.5 - VSBS (Vector Subtract Single)
547+ let cx = 0, cx2 = 0 in
548+ defm VSUBSWSX : RVm<"vsubs.w.sx", 0xda, V64, I32, VM>;
549+ let cx = 0, cx2 = 1 in {
550+ defm PVSUBSLO : RVm<"pvsubs.lo", 0xda, V64, I32, VM>;
551+ let isCodeGenOnly = 1 in
552+ defm VSUBSWZX : RVm<"vsubs.w.zx", 0xda, V64, I32, VM>;
553+ }
554+ let cx = 1, cx2 = 0 in
555+ defm PVSUBSUP : RVm<"pvsubs.up", 0xda, V64, I64, VM>;
556+ let cx = 1, cx2 = 1 in
557+ defm PVSUBS : RVm<"pvsubs", 0xda, V64, I64, VM512>;
558+ def : MnemonicAlias<"pvsubs.lo.sx", "vsubs.w.sx">;
559+ def : MnemonicAlias<"vsubs.w.zx", "pvsubs.lo">;
560+ def : MnemonicAlias<"vsubs.w", "pvsubs.lo">;
561+ def : MnemonicAlias<"pvsubs.lo.zx", "pvsubs.lo">;
562+
563+ // Section 8.10.6 - VSBX (Vector Subtract)
564+ defm VSUBSL : RVm<"vsubs.l", 0x9b, V64, I64, VM>;
565+
566+ // Section 8.10.7 - VMPY (Vector Multiply)
567+ let cx2 = 0 in
568+ defm VMULUL : RVm<"vmulu.l", 0xc9, V64, I64, VM>;
569+ let cx2 = 1 in
570+ defm VMULUW : RVm<"vmulu.w", 0xc9, V64, I32, VM>;
571+
572+ // Section 8.10.8 - VMPS (Vector Multiply Single)
573+ let cx2 = 0 in
574+ defm VMULSWSX : RVm<"vmuls.w.sx", 0xcb, V64, I32, VM>;
575+ let cx2 = 1 in
576+ defm VMULSWZX : RVm<"vmuls.w.zx", 0xcb, V64, I32, VM>;
577+ def : MnemonicAlias<"vmuls.w", "vmuls.w.zx">;
578+
579+ // Section 8.10.9 - VMPX (Vector Multiply)
580+ defm VMULSL : RVm<"vmuls.l", 0xdb, V64, I64, VM>;
581+
582+ // Section 8.10.10 - VMPD (Vector Multiply)
583+ defm VMULSLW : RVm<"vmuls.l.w", 0xd9, V64, I32, VM>;
584+
585+ // Section 8.10.11 - VDIV (Vector Divide)
586+ let cx2 = 0 in
587+ defm VDIVUL : RVDIVm<"vdivu.l", 0xe9, V64, I64, VM>;
588+ let cx2 = 1 in
589+ defm VDIVUW : RVDIVm<"vdivu.w", 0xe9, V64, I32, VM>;
590+
591+ // Section 8.10.12 - VDVS (Vector Divide Single)
592+ let cx2 = 0 in
593+ defm VDIVSWSX : RVDIVm<"vdivs.w.sx", 0xeb, V64, I32, VM>;
594+ let cx2 = 1 in
595+ defm VDIVSWZX : RVDIVm<"vdivs.w.zx", 0xeb, V64, I32, VM>;
596+ def : MnemonicAlias<"vdivs.w", "vdivs.w.zx">;
597+
598+ // Section 8.10.13 - VDVX (Vector Divide)
599+ defm VDIVSL : RVDIVm<"vdivs.l", 0xfb, V64, I64, VM>;
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