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x86: NFC remove needless InstrCompiler cast
Summary: The casts from String to PatFrag weren't needed if we instead provided an SDNode. This fix was suggested by @pete in D11382. Subscribers: pete, llvm-commits Differential Revision: http://reviews.llvm.org/D11788 llvm-svn: 244167
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llvm/lib/Target/X86/X86InstrCompiler.td

+15-15
Original file line numberDiff line numberDiff line change
@@ -759,38 +759,38 @@ defm LXADD : ATOMIC_LOAD_BINOP<0xc0, 0xc1, "xadd", "atomic_load_add",
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* extremely late to prevent them from being accidentally reordered in the backend
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* (see below the RELEASE_MOV* / ACQUIRE_MOV* pseudo-instructions)
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*/
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multiclass RELEASE_BINOP_MI<string op> {
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multiclass RELEASE_BINOP_MI<SDNode op> {
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def NAME#8mi : I<0, Pseudo, (outs), (ins i8mem:$dst, i8imm:$src),
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"#BINOP "#NAME#"8mi PSEUDO!",
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[(atomic_store_8 addr:$dst, (!cast<PatFrag>(op)
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[(atomic_store_8 addr:$dst, (op
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(atomic_load_8 addr:$dst), (i8 imm:$src)))]>;
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def NAME#8mr : I<0, Pseudo, (outs), (ins i8mem:$dst, GR8:$src),
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"#BINOP "#NAME#"8mr PSEUDO!",
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[(atomic_store_8 addr:$dst, (!cast<PatFrag>(op)
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[(atomic_store_8 addr:$dst, (op
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(atomic_load_8 addr:$dst), GR8:$src))]>;
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// NAME#16 is not generated as 16-bit arithmetic instructions are considered
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// costly and avoided as far as possible by this backend anyway
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def NAME#32mi : I<0, Pseudo, (outs), (ins i32mem:$dst, i32imm:$src),
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"#BINOP "#NAME#"32mi PSEUDO!",
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[(atomic_store_32 addr:$dst, (!cast<PatFrag>(op)
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[(atomic_store_32 addr:$dst, (op
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(atomic_load_32 addr:$dst), (i32 imm:$src)))]>;
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def NAME#32mr : I<0, Pseudo, (outs), (ins i32mem:$dst, GR32:$src),
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"#BINOP "#NAME#"32mr PSEUDO!",
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[(atomic_store_32 addr:$dst, (!cast<PatFrag>(op)
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[(atomic_store_32 addr:$dst, (op
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(atomic_load_32 addr:$dst), GR32:$src))]>;
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def NAME#64mi32 : I<0, Pseudo, (outs), (ins i64mem:$dst, i64i32imm:$src),
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"#BINOP "#NAME#"64mi32 PSEUDO!",
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[(atomic_store_64 addr:$dst, (!cast<PatFrag>(op)
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[(atomic_store_64 addr:$dst, (op
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(atomic_load_64 addr:$dst), (i64immSExt32:$src)))]>;
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def NAME#64mr : I<0, Pseudo, (outs), (ins i64mem:$dst, GR64:$src),
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"#BINOP "#NAME#"64mr PSEUDO!",
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[(atomic_store_64 addr:$dst, (!cast<PatFrag>(op)
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[(atomic_store_64 addr:$dst, (op
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(atomic_load_64 addr:$dst), GR64:$src))]>;
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}
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defm RELEASE_ADD : RELEASE_BINOP_MI<"add">;
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defm RELEASE_AND : RELEASE_BINOP_MI<"and">;
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defm RELEASE_OR : RELEASE_BINOP_MI<"or">;
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defm RELEASE_XOR : RELEASE_BINOP_MI<"xor">;
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defm RELEASE_ADD : RELEASE_BINOP_MI<add>;
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defm RELEASE_AND : RELEASE_BINOP_MI<and>;
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defm RELEASE_OR : RELEASE_BINOP_MI<or>;
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defm RELEASE_XOR : RELEASE_BINOP_MI<xor>;
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// Note: we don't deal with sub, because substractions of constants are
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// optimized into additions before this code can run
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@@ -799,21 +799,21 @@ defm RELEASE_XOR : RELEASE_BINOP_MI<"xor">;
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// FIXME: Version that doesn't clobber $src, using AVX's VADDSS.
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// FIXME: This could also handle SIMD operations with *ps and *pd instructions.
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let usesCustomInserter = 1 in {
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multiclass RELEASE_FP_BINOP_MI<string op> {
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multiclass RELEASE_FP_BINOP_MI<SDNode op> {
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def NAME#32mr : I<0, Pseudo, (outs), (ins i32mem:$dst, FR32:$src),
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"#BINOP "#NAME#"32mr PSEUDO!",
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[(atomic_store_32 addr:$dst,
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(i32 (bitconvert (!cast<PatFrag>(op)
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(i32 (bitconvert (op
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(f32 (bitconvert (i32 (atomic_load_32 addr:$dst)))),
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FR32:$src))))]>, Requires<[HasSSE1]>;
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def NAME#64mr : I<0, Pseudo, (outs), (ins i64mem:$dst, FR64:$src),
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"#BINOP "#NAME#"64mr PSEUDO!",
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[(atomic_store_64 addr:$dst,
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(i64 (bitconvert (!cast<PatFrag>(op)
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(i64 (bitconvert (op
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(f64 (bitconvert (i64 (atomic_load_64 addr:$dst)))),
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FR64:$src))))]>, Requires<[HasSSE2]>;
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}
816-
defm RELEASE_FADD : RELEASE_FP_BINOP_MI<"fadd">;
816+
defm RELEASE_FADD : RELEASE_FP_BINOP_MI<fadd>;
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// FIXME: Add fsub, fmul, fdiv, ...
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}
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