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The RISCV-V-Spec[1] describes which RVV instructions are allowed to overlap between source operands and destination operands. Currently, most of these instructions are constrained with early-clobber.
This patch labels these instructions with TargetOverlapConstraintType in pseudo to indicate that these instructions can overlap.
The value of TargetOverlapConstraintType is:
1 -> default
2 -> narrow case
3 -> widen case
This information is useful for future optimization passes.
[1] https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#52-vector-operands
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D157588
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