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[llvm][CodeGen] Resolve issues when updating live intervals in window scheduler (#101945)
Corrupted live interval information can cause window scheduling to crash in some cases. By adding the missing MBB's live interval information in the ModuloScheduleExpander, the information can be correctly analyzed in the window scheduler. (cherry picked from commit 43ba109)
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‎llvm/lib/CodeGen/ModuloSchedule.cpp

+3
Original file line numberDiff line numberDiff line change
@@ -130,6 +130,7 @@ void ModuloScheduleExpander::generatePipelinedLoop() {
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// Generate the prolog instructions that set up the pipeline.
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generateProlog(MaxStageCount, KernelBB, VRMap, PrologBBs);
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MF.insert(BB->getIterator(), KernelBB);
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LIS.insertMBBInMaps(KernelBB);
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// Rearrange the instructions to generate the new, pipelined loop,
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// and update register names as needed.
@@ -210,6 +211,7 @@ void ModuloScheduleExpander::generateProlog(unsigned LastStage,
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NewBB->transferSuccessors(PredBB);
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PredBB->addSuccessor(NewBB);
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PredBB = NewBB;
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LIS.insertMBBInMaps(NewBB);
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// Generate instructions for each appropriate stage. Process instructions
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// in original program order.
@@ -283,6 +285,7 @@ void ModuloScheduleExpander::generateEpilog(
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PredBB->replaceSuccessor(LoopExitBB, NewBB);
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NewBB->addSuccessor(LoopExitBB);
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LIS.insertMBBInMaps(NewBB);
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if (EpilogStart == LoopExitBB)
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EpilogStart = NewBB;

‎llvm/test/CodeGen/Hexagon/swp-ws-live-intervals.mir

+217
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,217 @@
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# REQUIRES: asserts
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#
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# RUN: llc --march=hexagon %s -run-pass=pipeliner -debug-only=pipeliner \
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# RUN: -window-sched=force -filetype=null -window-search-num=100 \
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# RUN: -window-search-ratio=100 -window-diff-limit=0 -verify-machineinstrs \
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# RUN: 2>&1 | FileCheck %s
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# The bug was reported at https://github.com/llvm/llvm-project/pull/99454.
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# It is caused by the corruption of live intervals in certain scenarios.
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#
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# We check the newly generated MBBs after successful scheduling here.
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# CHECK: Best window offset is {{[0-9]+}} and Best II is {{[0-9]+}}.
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# CHECK: prolog:
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# CHECK: bb.5:
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# CHECK: New block
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# CHECK: bb.6:
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# CHECK: epilog:
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# CHECK: bb.7:
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# CHECK: Best window offset is {{[0-9]+}} and Best II is {{[0-9]+}}.
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# CHECK: prolog:
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# CHECK: bb.8:
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# CHECK: New block
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# CHECK: bb.9:
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# CHECK: epilog:
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# CHECK: bb.10:
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--- |
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target triple = "hexagon"
29+
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@_dp_ctrl_calc_tu_temp2_fp = global i64 0
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@_dp_ctrl_calc_tu_temp1_fp = global i32 0
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@dp_panel_update_tu_timings___trans_tmp_5 = global i64 0
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@_dp_ctrl_calc_tu___trans_tmp_8 = global i64 0
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declare void @llvm.lifetime.start.p0(i64 immarg, ptr nocapture)
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declare i8 @div64_u64_rem(i32, ptr)
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declare void @llvm.lifetime.end.p0(i64 immarg, ptr nocapture)
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define void @dp_ctrl_calc_tu_parameters() {
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if.end.i:
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%rem.i11.i = alloca i64, align 8
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%rem.i.i = alloca i64, align 8
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call void @llvm.lifetime.start.p0(i64 8, ptr nonnull %rem.i11.i)
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%call.i.i = call i8 @div64_u64_rem(i32 0, ptr nonnull %rem.i11.i)
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%conv1.i.i = zext i8 %call.i.i to i64
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%rem.promoted.i.i = load i64, ptr %rem.i11.i, align 8
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br label %do.body.i.i
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do.body.i.i:
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%lsr.iv1 = phi i32 [ %lsr.iv.next2, %do.body.i.i ], [ -32, %if.end.i ]
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%sub9.i.i = phi i64 [ %rem.promoted.i.i, %if.end.i ], [ %sub8.i.i.7, %do.body.i.i ]
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%res_abs.0.i.i = phi i64 [ %conv1.i.i, %if.end.i ], [ %res_abs.1.i.i.7, %do.body.i.i ]
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%cmp.not.i.i = icmp ne i64 %sub9.i.i, 0
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%sub.i.neg.i = sext i1 %cmp.not.i.i to i64
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%sub8.i.i = add i64 %sub9.i.i, %sub.i.neg.i
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%0 = shl i64 %res_abs.0.i.i, 2
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%1 = select i1 %cmp.not.i.i, i64 2, i64 0
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%shl.i.i.5 = or disjoint i64 %0, %1
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%cmp.not.i.i.5 = icmp ne i64 %sub8.i.i, 0
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%sub.i.neg.i.5 = sext i1 %cmp.not.i.i.5 to i64
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%sub8.i.i.5 = add i64 %sub8.i.i, %sub.i.neg.i.5
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%or.i.i.5 = zext i1 %cmp.not.i.i.5 to i64
63+
%res_abs.1.i.i.5 = or disjoint i64 %shl.i.i.5, %or.i.i.5
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%cmp.not.i.i.6 = icmp ne i64 %sub8.i.i.5, 0
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%sub.i.neg.i.6 = sext i1 %cmp.not.i.i.6 to i64
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%sub8.i.i.6 = add i64 %sub8.i.i.5, %sub.i.neg.i.6
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%2 = shl i64 %res_abs.1.i.i.5, 2
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%3 = select i1 %cmp.not.i.i.6, i64 2, i64 0
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%shl.i.i.7 = or disjoint i64 %2, %3
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%cmp.not.i.i.7 = icmp ne i64 %sub8.i.i.6, 0
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%sub.i.neg.i.7 = sext i1 %cmp.not.i.i.7 to i64
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%sub8.i.i.7 = add i64 %sub8.i.i.6, %sub.i.neg.i.7
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%or.i.i.7 = zext i1 %cmp.not.i.i.7 to i64
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%res_abs.1.i.i.7 = or disjoint i64 %shl.i.i.7, %or.i.i.7
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%lsr.iv.next2 = add nsw i32 %lsr.iv1, 8
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%tobool.not.i.i.7 = icmp eq i32 %lsr.iv.next2, 0
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br i1 %tobool.not.i.i.7, label %fec_check.i, label %do.body.i.i
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79+
fec_check.i:
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call void @llvm.lifetime.end.p0(i64 8, ptr nonnull %rem.i11.i)
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store i64 %res_abs.1.i.i.7, ptr @_dp_ctrl_calc_tu_temp2_fp, align 8
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call void @llvm.lifetime.start.p0(i64 8, ptr nonnull %rem.i11.i)
83+
%call.i12.i = call i8 @div64_u64_rem(i32 0, ptr nonnull %rem.i11.i)
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%conv1.i13.i = zext i8 %call.i12.i to i64
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%rem.promoted.i14.i = load i64, ptr %rem.i11.i, align 8
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br label %do.body.i15.i
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88+
do.body.i15.i:
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%lsr.iv = phi i32 [ %lsr.iv.next, %do.body.i15.i ], [ -32, %fec_check.i ]
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%sub9.i16.i = phi i64 [ %rem.promoted.i14.i, %fec_check.i ], [ %sub8.i22.i.7, %do.body.i15.i ]
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%res_abs.0.i17.i = phi i64 [ %conv1.i13.i, %fec_check.i ], [ %res_abs.1.i24.i.7, %do.body.i15.i ]
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%cmp.not.i20.i = icmp ugt i64 %sub9.i16.i, 999
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%sub.i21.neg.i = select i1 %cmp.not.i20.i, i64 -1000, i64 0
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%sub8.i22.i = add i64 %sub.i21.neg.i, %sub9.i16.i
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%4 = shl i64 %res_abs.0.i17.i, 2
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%5 = select i1 %cmp.not.i20.i, i64 2, i64 0
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%shl.i19.i.7 = or disjoint i64 %4, %5
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%cmp.not.i20.i.7 = icmp ugt i64 %sub8.i22.i, 999
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%sub.i21.neg.i.7 = select i1 %cmp.not.i20.i.7, i64 -1000, i64 0
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%sub8.i22.i.7 = add i64 %sub.i21.neg.i.7, %sub8.i22.i
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%or.i23.i.7 = zext i1 %cmp.not.i20.i.7 to i64
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%res_abs.1.i24.i.7 = or disjoint i64 %shl.i19.i.7, %or.i23.i.7
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%lsr.iv.next = add nsw i32 %lsr.iv, 8
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%tobool.not.i26.i.7 = icmp eq i32 %lsr.iv.next, 0
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br i1 %tobool.not.i26.i.7, label %_dp_ctrl_calc_tu.exit, label %do.body.i15.i
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_dp_ctrl_calc_tu.exit:
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call void @llvm.lifetime.end.p0(i64 8, ptr nonnull %rem.i11.i)
109+
%conv.i = trunc i64 %res_abs.1.i24.i.7 to i32
110+
store i32 %conv.i, ptr @_dp_ctrl_calc_tu_temp1_fp, align 4
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%conv5.i = and i64 %res_abs.1.i24.i.7, 4294967295
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store i64 %conv5.i, ptr @dp_panel_update_tu_timings___trans_tmp_5, align 8
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store i64 %res_abs.1.i.i.7, ptr @_dp_ctrl_calc_tu___trans_tmp_8, align 8
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ret void
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}
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...
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---
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name: dp_ctrl_calc_tu_parameters
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tracksRegLiveness: true
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stack:
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- { id: 0, name: rem.i11.i, type: default, offset: 0, size: 8, alignment: 8}
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body: |
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bb.0:
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successors: %bb.1(0x80000000)
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%0:intregs = A2_tfrsi 0
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%1:intregs = PS_fi %stack.0.rem.i11.i, 0
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%2:intregs = A2_tfrsi 0
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%3:doubleregs = A4_combineir 0, %2
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%4:doubleregs = L2_loadrd_io %stack.0.rem.i11.i, 0
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%5:doubleregs = A2_tfrpi 0
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J2_loop0i %bb.1, 4, implicit-def $lc0, implicit-def $sa0, implicit-def $usr
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bb.1 (machine-block-address-taken):
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successors: %bb.2(0x04000000), %bb.1(0x7c000000)
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138+
%6:doubleregs = PHI %4, %bb.0, %7, %bb.1
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%8:doubleregs = PHI %3, %bb.0, %9, %bb.1
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%10:predregs = C2_cmpeqp %6, %5
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%11:intregs = C2_muxii %10, 0, -1
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%12:doubleregs = A2_addsp %11, %6
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%13:doubleregs = S2_asl_i_p %8, 2
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%14:intregs = S2_setbit_i %13.isub_lo, 1
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%15:intregs = C2_mux %10, %13.isub_lo, %14
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%16:predregs = C2_cmpeqp %12, %5
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%17:intregs = C2_muxii %16, 0, -1
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%18:doubleregs = A2_addsp %17, %12
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%19:intregs = S2_setbit_i %15, 0
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%20:intregs = C2_mux %16, %15, %19
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%21:predregs = C2_cmpeqp %18, %5
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%22:intregs = C2_muxii %21, 0, -1
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%23:doubleregs = A2_addsp %22, %18
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%24:intregs = S2_asl_i_r %20, 2
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%25:intregs = S2_extractu %8.isub_lo, 2, 28
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%26:intregs = S2_asl_i_r_or %25, %13.isub_hi, 2
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%27:intregs = S2_setbit_i %24, 1
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%28:intregs = C2_mux %21, %24, %27
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%29:predregs = C2_cmpeqp %23, %5
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%30:intregs = C2_muxii %29, 0, -1
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%7:doubleregs = A2_addsp %30, %23
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%31:intregs = S2_setbit_i %28, 0
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%32:intregs = C2_mux %29, %28, %31
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%9:doubleregs = REG_SEQUENCE %26, %subreg.isub_hi, %32, %subreg.isub_lo
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ENDLOOP0 %bb.1, implicit-def $pc, implicit-def $lc0, implicit $sa0, implicit $lc0
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J2_jump %bb.2, implicit-def dead $pc
167+
168+
bb.2:
169+
successors: %bb.3(0x80000000)
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S2_storerdgp @_dp_ctrl_calc_tu_temp2_fp, %9, implicit $gp
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%33:intregs = A2_tfrsi 0
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%34:intregs = PS_fi %stack.0.rem.i11.i, 0
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%35:intregs = A2_tfrsi 0
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%36:doubleregs = L2_loadrd_io %stack.0.rem.i11.i, 0
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%37:doubleregs = A2_tfrpi 124
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%38:intregs = A2_tfrsi -1000
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%39:intregs = A2_tfrsi -1
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J2_loop0i %bb.3, 4, implicit-def $lc0, implicit-def $sa0, implicit-def $usr
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bb.3 (machine-block-address-taken):
182+
successors: %bb.4(0x04000000), %bb.3(0x7c000000)
183+
184+
%40:doubleregs = PHI %36, %bb.2, %41, %bb.3
185+
%42:intregs = PHI %35, %bb.2, %43, %bb.3
186+
%44:intregs = PHI %33, %bb.2, %45, %bb.3
187+
%46:doubleregs = S2_lsr_i_p %40, 3
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%47:predregs = C2_cmpgtup %46, %37
189+
%48:intregs = C2_mux %47, %38, %33
190+
%49:intregs = C2_mux %47, %39, %33
191+
%50:doubleregs = REG_SEQUENCE %49, %subreg.isub_hi, %48, %subreg.isub_lo
192+
%51:doubleregs = A2_addp %50, %40
193+
%52:intregs = S2_asl_i_r %42, 2
194+
%53:intregs = S2_extractu %42, 2, 30
195+
%45:intregs = S2_asl_i_r_or %53, %44, 2
196+
%54:intregs = S2_setbit_i %52, 1
197+
%55:intregs = C2_mux %47, %54, %52
198+
%56:doubleregs = S2_lsr_i_p %51, 3
199+
%57:predregs = C2_cmpgtup %56, %37
200+
%58:intregs = C2_mux %57, %38, %33
201+
%59:intregs = C2_mux %57, %39, %33
202+
%60:doubleregs = REG_SEQUENCE %59, %subreg.isub_hi, %58, %subreg.isub_lo
203+
%41:doubleregs = A2_addp %60, %51
204+
%61:intregs = S2_setbit_i %55, 0
205+
%43:intregs = C2_mux %57, %61, %55
206+
ENDLOOP0 %bb.3, implicit-def $pc, implicit-def $lc0, implicit $sa0, implicit $lc0
207+
J2_jump %bb.4, implicit-def dead $pc
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209+
bb.4:
210+
S2_storerigp @_dp_ctrl_calc_tu_temp1_fp, %43, implicit $gp
211+
%62:intregs = A2_tfrsi 0
212+
%63:doubleregs = REG_SEQUENCE %43, %subreg.isub_lo, %62, %subreg.isub_hi
213+
S2_storerdgp @dp_panel_update_tu_timings___trans_tmp_5, %63, implicit $gp
214+
S2_storerdgp @_dp_ctrl_calc_tu___trans_tmp_8, %9, implicit $gp
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PS_jmpret $r31, implicit-def dead $pc
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...

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