Skip to content

Commit 286a366

Browse files
lukel97lukel97
authored
[RISCV] Remove vmv.s.x and vmv.x.s lmul pseudo variants (#71501)
vmv.s.x and vmv.x.s ignore LMUL, so we can replace the PseudoVMV_S_X_MX and PseudoVMV_X_S_MX with just one pseudo each. These pseudos use the VR register class (just like the actual instruction), so we now only have TableGen patterns for vectors of LMUL <= 1. We now rely on the existing combines that shrink LMUL down to 1 for vmv_s_x_vl (and vfmv_s_f_vl). We could look into removing these combines later and just inserting the nodes with the correct type in a later patch. The test diff is due to the fact that a PseudoVMV_S_X/PsuedoVMV_X_S no longer carries any information about LMUL, so if it's the only vector pseudo instruction in a block then it now defaults to LMUL=1.
1 parent 44aa4d7 commit 286a366

34 files changed

+859
-886
lines changed

‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp‎

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -15732,6 +15732,17 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
1573215732

1573315733
break;
1573415734
}
15735+
case RISCVISD::VMV_X_S: {
15736+
SDValue Vec = N->getOperand(0);
15737+
MVT VecVT = N->getOperand(0).getSimpleValueType();
15738+
const MVT M1VT = getLMUL1VT(VecVT);
15739+
if (M1VT.bitsLT(VecVT)) {
15740+
Vec = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, M1VT, Vec,
15741+
DAG.getVectorIdxConstant(0, DL));
15742+
return DAG.getNode(RISCVISD::VMV_X_S, DL, N->getSimpleValueType(0), Vec);
15743+
}
15744+
break;
15745+
}
1573515746
case ISD::INTRINSIC_VOID:
1573615747
case ISD::INTRINSIC_W_CHAIN:
1573715748
case ISD::INTRINSIC_WO_CHAIN: {

‎llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td‎

Lines changed: 14 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -6764,24 +6764,18 @@ defm PseudoVID : VPseudoVID_V;
67646764

67656765
let Predicates = [HasVInstructions] in {
67666766
let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
6767-
foreach m = MxList in {
6768-
defvar mx = m.MX;
6769-
let VLMul = m.value in {
6770-
let HasSEWOp = 1, BaseInstr = VMV_X_S in
6771-
def PseudoVMV_X_S # "_" # mx:
6772-
Pseudo<(outs GPR:$rd), (ins m.vrclass:$rs2, ixlenimm:$sew), []>,
6773-
Sched<[WriteVIMovVX, ReadVIMovVX]>,
6774-
RISCVVPseudo;
6775-
let HasVLOp = 1, HasSEWOp = 1, BaseInstr = VMV_S_X,
6776-
Constraints = "$rd = $rs1" in
6777-
def PseudoVMV_S_X # "_" # mx: Pseudo<(outs m.vrclass:$rd),
6778-
(ins m.vrclass:$rs1, GPR:$rs2,
6779-
AVL:$vl, ixlenimm:$sew),
6780-
[]>,
6781-
Sched<[WriteVIMovXV, ReadVIMovXV, ReadVIMovXX]>,
6782-
RISCVVPseudo;
6783-
}
6784-
}
6767+
let HasSEWOp = 1, BaseInstr = VMV_X_S in
6768+
def PseudoVMV_X_S:
6769+
Pseudo<(outs GPR:$rd), (ins VR:$rs2, ixlenimm:$sew), []>,
6770+
Sched<[WriteVIMovVX, ReadVIMovVX]>,
6771+
RISCVVPseudo;
6772+
let HasVLOp = 1, HasSEWOp = 1, BaseInstr = VMV_S_X,
6773+
Constraints = "$rd = $rs1" in
6774+
def PseudoVMV_S_X: Pseudo<(outs VR:$rd),
6775+
(ins VR:$rs1, GPR:$rs2, AVL:$vl, ixlenimm:$sew),
6776+
[]>,
6777+
Sched<[WriteVIMovXV, ReadVIMovXV, ReadVIMovXX]>,
6778+
RISCVVPseudo;
67856779
}
67866780
} // Predicates = [HasVInstructions]
67876781

@@ -7408,10 +7402,10 @@ defm : VPatNullaryV<"int_riscv_vid", "PseudoVID">;
74087402
// 16.1. Integer Scalar Move Instructions
74097403
//===----------------------------------------------------------------------===//
74107404

7411-
foreach vti = AllIntegerVectors in {
7405+
foreach vti = NoGroupIntegerVectors in {
74127406
let Predicates = GetVTypePredicates<vti>.Predicates in
74137407
def : Pat<(XLenVT (riscv_vmv_x_s (vti.Vector vti.RegClass:$rs2))),
7414-
(!cast<Instruction>("PseudoVMV_X_S_" # vti.LMul.MX) $rs2, vti.Log2SEW)>;
7408+
(PseudoVMV_X_S $rs2, vti.Log2SEW)>;
74157409
// vmv.s.x is handled with a custom node in RISCVInstrInfoVVLPatterns.td
74167410
}
74177411

‎llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td‎

Lines changed: 16 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -2794,16 +2794,19 @@ foreach mti = AllMasks in {
27942794
// 16. Vector Permutation Instructions
27952795

27962796
// 16.1. Integer Scalar Move Instructions
2797-
// 16.4. Vector Register Gather Instruction
2798-
foreach vti = AllIntegerVectors in {
2797+
foreach vti = NoGroupIntegerVectors in {
27992798
let Predicates = GetVTypePredicates<vti>.Predicates in {
28002799
def : Pat<(vti.Vector (riscv_vmv_s_x_vl (vti.Vector vti.RegClass:$merge),
28012800
vti.ScalarRegClass:$rs1,
28022801
VLOpFrag)),
2803-
(!cast<Instruction>("PseudoVMV_S_X_"#vti.LMul.MX)
2804-
vti.RegClass:$merge,
2805-
(vti.Scalar vti.ScalarRegClass:$rs1), GPR:$vl, vti.Log2SEW)>;
2802+
(PseudoVMV_S_X $merge, vti.ScalarRegClass:$rs1, GPR:$vl,
2803+
vti.Log2SEW)>;
2804+
}
2805+
}
28062806

2807+
// 16.4. Vector Register Gather Instruction
2808+
foreach vti = AllIntegerVectors in {
2809+
let Predicates = GetVTypePredicates<vti>.Predicates in {
28072810
def : Pat<(vti.Vector (riscv_vrgather_vv_vl vti.RegClass:$rs2,
28082811
vti.RegClass:$rs1,
28092812
vti.RegClass:$merge,
@@ -2851,18 +2854,21 @@ foreach vti = AllIntegerVectors in {
28512854
}
28522855

28532856
// 16.2. Floating-Point Scalar Move Instructions
2854-
foreach vti = AllFloatVectors in {
2857+
foreach vti = NoGroupFloatVectors in {
28552858
let Predicates = GetVTypePredicates<vti>.Predicates in {
28562859
def : Pat<(vti.Vector (riscv_vfmv_s_f_vl (vti.Vector vti.RegClass:$merge),
28572860
(vti.Scalar (fpimm0)),
28582861
VLOpFrag)),
2859-
(!cast<Instruction>("PseudoVMV_S_X_"#vti.LMul.MX)
2860-
vti.RegClass:$merge, (XLenVT X0), GPR:$vl, vti.Log2SEW)>;
2862+
(PseudoVMV_S_X $merge, (XLenVT X0), GPR:$vl, vti.Log2SEW)>;
28612863
def : Pat<(vti.Vector (riscv_vfmv_s_f_vl (vti.Vector vti.RegClass:$merge),
28622864
(vti.Scalar (SelectFPImm (XLenVT GPR:$imm))),
28632865
VLOpFrag)),
2864-
(!cast<Instruction>("PseudoVMV_S_X_"#vti.LMul.MX)
2865-
vti.RegClass:$merge, GPR:$imm, GPR:$vl, vti.Log2SEW)>;
2866+
(PseudoVMV_S_X $merge, GPR:$imm, GPR:$vl, vti.Log2SEW)>;
2867+
}
2868+
}
2869+
2870+
foreach vti = AllFloatVectors in {
2871+
let Predicates = GetVTypePredicates<vti>.Predicates in {
28662872
def : Pat<(vti.Vector (riscv_vfmv_s_f_vl (vti.Vector vti.RegClass:$merge),
28672873
vti.ScalarRegClass:$rs1,
28682874
VLOpFrag)),

‎llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp‎

Lines changed: 1 addition & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -370,13 +370,7 @@ static bool isSignExtendingOpW(const MachineInstr &MI,
370370
return MI.getOperand(1).getReg() == RISCV::X0;
371371
case RISCV::PseudoAtomicLoadNand32:
372372
return true;
373-
case RISCV::PseudoVMV_X_S_MF8:
374-
case RISCV::PseudoVMV_X_S_MF4:
375-
case RISCV::PseudoVMV_X_S_MF2:
376-
case RISCV::PseudoVMV_X_S_M1:
377-
case RISCV::PseudoVMV_X_S_M2:
378-
case RISCV::PseudoVMV_X_S_M4:
379-
case RISCV::PseudoVMV_X_S_M8: {
373+
case RISCV::PseudoVMV_X_S: {
380374
// vmv.x.s has at least 33 sign bits if log2(sew) <= 5.
381375
int64_t Log2SEW = MI.getOperand(2).getImm();
382376
assert(Log2SEW >= 3 && Log2SEW <= 6 && "Unexpected Log2SEW");

‎llvm/test/CodeGen/RISCV/rvv/emergency-slot.mir‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -139,7 +139,7 @@ body: |
139139
; CHECK-NEXT: renamable $v0 = VL1RE8_V killed $x10 :: (load unknown-size from %stack.1, align 8)
140140
; CHECK-NEXT: $x10 = LD $x2, 8 :: (load (s64) from %stack.15)
141141
; CHECK-NEXT: renamable $v0 = PseudoVSLIDEDOWN_VX_M1 undef renamable $v0, killed renamable $v0, killed renamable $x13, $noreg, 3 /* e8 */, 1 /* ta, mu */, implicit $vl, implicit $vtype
142-
; CHECK-NEXT: renamable $x13 = PseudoVMV_X_S_M1 killed renamable $v0, 3 /* e8 */, implicit $vl, implicit $vtype
142+
; CHECK-NEXT: renamable $x13 = PseudoVMV_X_S killed renamable $v0, 3 /* e8 */, implicit $vl, implicit $vtype
143143
; CHECK-NEXT: BLT killed renamable $x16, renamable $x27, %bb.2
144144
; CHECK-NEXT: {{ $}}
145145
; CHECK-NEXT: bb.1:
@@ -206,7 +206,7 @@ body: |
206206
renamable $x13 = nsw ADDI renamable $x16, -2
207207
renamable $v0 = VL1RE8_V %stack.1 :: (load unknown-size from %stack.1, align 8)
208208
renamable $v0 = PseudoVSLIDEDOWN_VX_M1 undef renamable $v0, killed renamable $v0, killed renamable $x13, $noreg, 3, 1, implicit $vl, implicit $vtype
209-
renamable $x13 = PseudoVMV_X_S_M1 killed renamable $v0, 3, implicit $vl, implicit $vtype
209+
renamable $x13 = PseudoVMV_X_S killed renamable $v0, 3, implicit $vl, implicit $vtype
210210
BLT killed renamable $x16, renamable $x27, %bb.2
211211
212212
bb.1:

‎llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv32.ll‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -8,7 +8,7 @@
88
define signext i8 @extractelt_nxv1i8_0(<vscale x 1 x i8> %v) {
99
; CHECK-LABEL: extractelt_nxv1i8_0:
1010
; CHECK: # %bb.0:
11-
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
11+
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
1212
; CHECK-NEXT: vmv.x.s a0, v8
1313
; CHECK-NEXT: ret
1414
%r = extractelement <vscale x 1 x i8> %v, i32 0
@@ -40,7 +40,7 @@ define signext i8 @extractelt_nxv1i8_idx(<vscale x 1 x i8> %v, i32 %idx) {
4040
define signext i8 @extractelt_nxv2i8_0(<vscale x 2 x i8> %v) {
4141
; CHECK-LABEL: extractelt_nxv2i8_0:
4242
; CHECK: # %bb.0:
43-
; CHECK-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
43+
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
4444
; CHECK-NEXT: vmv.x.s a0, v8
4545
; CHECK-NEXT: ret
4646
%r = extractelement <vscale x 2 x i8> %v, i32 0
@@ -72,7 +72,7 @@ define signext i8 @extractelt_nxv2i8_idx(<vscale x 2 x i8> %v, i32 %idx) {
7272
define signext i8 @extractelt_nxv4i8_0(<vscale x 4 x i8> %v) {
7373
; CHECK-LABEL: extractelt_nxv4i8_0:
7474
; CHECK: # %bb.0:
75-
; CHECK-NEXT: vsetivli zero, 1, e8, mf2, ta, ma
75+
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
7676
; CHECK-NEXT: vmv.x.s a0, v8
7777
; CHECK-NEXT: ret
7878
%r = extractelement <vscale x 4 x i8> %v, i32 0
@@ -232,7 +232,7 @@ define signext i8 @extractelt_nxv64i8_idx(<vscale x 64 x i8> %v, i32 %idx) {
232232
define signext i16 @extractelt_nxv1i16_0(<vscale x 1 x i16> %v) {
233233
; CHECK-LABEL: extractelt_nxv1i16_0:
234234
; CHECK: # %bb.0:
235-
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
235+
; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma
236236
; CHECK-NEXT: vmv.x.s a0, v8
237237
; CHECK-NEXT: ret
238238
%r = extractelement <vscale x 1 x i16> %v, i32 0
@@ -264,7 +264,7 @@ define signext i16 @extractelt_nxv1i16_idx(<vscale x 1 x i16> %v, i32 %idx) {
264264
define signext i16 @extractelt_nxv2i16_0(<vscale x 2 x i16> %v) {
265265
; CHECK-LABEL: extractelt_nxv2i16_0:
266266
; CHECK: # %bb.0:
267-
; CHECK-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
267+
; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma
268268
; CHECK-NEXT: vmv.x.s a0, v8
269269
; CHECK-NEXT: ret
270270
%r = extractelement <vscale x 2 x i16> %v, i32 0
@@ -424,7 +424,7 @@ define signext i16 @extractelt_nxv32i16_idx(<vscale x 32 x i16> %v, i32 %idx) {
424424
define i32 @extractelt_nxv1i32_0(<vscale x 1 x i32> %v) {
425425
; CHECK-LABEL: extractelt_nxv1i32_0:
426426
; CHECK: # %bb.0:
427-
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
427+
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
428428
; CHECK-NEXT: vmv.x.s a0, v8
429429
; CHECK-NEXT: ret
430430
%r = extractelement <vscale x 1 x i32> %v, i32 0

‎llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv64.ll‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -7,7 +7,7 @@
77
define signext i8 @extractelt_nxv1i8_0(<vscale x 1 x i8> %v) {
88
; CHECK-LABEL: extractelt_nxv1i8_0:
99
; CHECK: # %bb.0:
10-
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
10+
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
1111
; CHECK-NEXT: vmv.x.s a0, v8
1212
; CHECK-NEXT: ret
1313
%r = extractelement <vscale x 1 x i8> %v, i32 0
@@ -39,7 +39,7 @@ define signext i8 @extractelt_nxv1i8_idx(<vscale x 1 x i8> %v, i32 zeroext %idx)
3939
define signext i8 @extractelt_nxv2i8_0(<vscale x 2 x i8> %v) {
4040
; CHECK-LABEL: extractelt_nxv2i8_0:
4141
; CHECK: # %bb.0:
42-
; CHECK-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
42+
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
4343
; CHECK-NEXT: vmv.x.s a0, v8
4444
; CHECK-NEXT: ret
4545
%r = extractelement <vscale x 2 x i8> %v, i32 0
@@ -71,7 +71,7 @@ define signext i8 @extractelt_nxv2i8_idx(<vscale x 2 x i8> %v, i32 zeroext %idx)
7171
define signext i8 @extractelt_nxv4i8_0(<vscale x 4 x i8> %v) {
7272
; CHECK-LABEL: extractelt_nxv4i8_0:
7373
; CHECK: # %bb.0:
74-
; CHECK-NEXT: vsetivli zero, 1, e8, mf2, ta, ma
74+
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
7575
; CHECK-NEXT: vmv.x.s a0, v8
7676
; CHECK-NEXT: ret
7777
%r = extractelement <vscale x 4 x i8> %v, i32 0
@@ -231,7 +231,7 @@ define signext i8 @extractelt_nxv64i8_idx(<vscale x 64 x i8> %v, i32 zeroext %id
231231
define signext i16 @extractelt_nxv1i16_0(<vscale x 1 x i16> %v) {
232232
; CHECK-LABEL: extractelt_nxv1i16_0:
233233
; CHECK: # %bb.0:
234-
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
234+
; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma
235235
; CHECK-NEXT: vmv.x.s a0, v8
236236
; CHECK-NEXT: ret
237237
%r = extractelement <vscale x 1 x i16> %v, i32 0
@@ -263,7 +263,7 @@ define signext i16 @extractelt_nxv1i16_idx(<vscale x 1 x i16> %v, i32 zeroext %i
263263
define signext i16 @extractelt_nxv2i16_0(<vscale x 2 x i16> %v) {
264264
; CHECK-LABEL: extractelt_nxv2i16_0:
265265
; CHECK: # %bb.0:
266-
; CHECK-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
266+
; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma
267267
; CHECK-NEXT: vmv.x.s a0, v8
268268
; CHECK-NEXT: ret
269269
%r = extractelement <vscale x 2 x i16> %v, i32 0
@@ -423,7 +423,7 @@ define signext i16 @extractelt_nxv32i16_idx(<vscale x 32 x i16> %v, i32 zeroext
423423
define signext i32 @extractelt_nxv1i32_0(<vscale x 1 x i32> %v) {
424424
; CHECK-LABEL: extractelt_nxv1i32_0:
425425
; CHECK: # %bb.0:
426-
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
426+
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
427427
; CHECK-NEXT: vmv.x.s a0, v8
428428
; CHECK-NEXT: ret
429429
%r = extractelement <vscale x 1 x i32> %v, i32 0

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll‎

Lines changed: 13 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -32,13 +32,13 @@ define <32 x i1> @bitcast_v4i8_v32i1(<4 x i8> %a, <32 x i1> %b) {
3232
define i8 @bitcast_v1i8_i8(<1 x i8> %a) {
3333
; CHECK-LABEL: bitcast_v1i8_i8:
3434
; CHECK: # %bb.0:
35-
; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
35+
; CHECK-NEXT: vsetivli zero, 1, e8, m1, ta, ma
3636
; CHECK-NEXT: vmv.x.s a0, v8
3737
; CHECK-NEXT: ret
3838
;
3939
; ELEN32-LABEL: bitcast_v1i8_i8:
4040
; ELEN32: # %bb.0:
41-
; ELEN32-NEXT: vsetivli zero, 1, e8, mf4, ta, ma
41+
; ELEN32-NEXT: vsetivli zero, 1, e8, m1, ta, ma
4242
; ELEN32-NEXT: vmv.x.s a0, v8
4343
; ELEN32-NEXT: ret
4444
%b = bitcast <1 x i8> %a to i8
@@ -48,13 +48,13 @@ define i8 @bitcast_v1i8_i8(<1 x i8> %a) {
4848
define i16 @bitcast_v2i8_i16(<2 x i8> %a) {
4949
; CHECK-LABEL: bitcast_v2i8_i16:
5050
; CHECK: # %bb.0:
51-
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
51+
; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma
5252
; CHECK-NEXT: vmv.x.s a0, v8
5353
; CHECK-NEXT: ret
5454
;
5555
; ELEN32-LABEL: bitcast_v2i8_i16:
5656
; ELEN32: # %bb.0:
57-
; ELEN32-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
57+
; ELEN32-NEXT: vsetivli zero, 1, e16, m1, ta, ma
5858
; ELEN32-NEXT: vmv.x.s a0, v8
5959
; ELEN32-NEXT: ret
6060
%b = bitcast <2 x i8> %a to i16
@@ -64,13 +64,13 @@ define i16 @bitcast_v2i8_i16(<2 x i8> %a) {
6464
define i16 @bitcast_v1i16_i16(<1 x i16> %a) {
6565
; CHECK-LABEL: bitcast_v1i16_i16:
6666
; CHECK: # %bb.0:
67-
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
67+
; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma
6868
; CHECK-NEXT: vmv.x.s a0, v8
6969
; CHECK-NEXT: ret
7070
;
7171
; ELEN32-LABEL: bitcast_v1i16_i16:
7272
; ELEN32: # %bb.0:
73-
; ELEN32-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
73+
; ELEN32-NEXT: vsetivli zero, 1, e16, m1, ta, ma
7474
; ELEN32-NEXT: vmv.x.s a0, v8
7575
; ELEN32-NEXT: ret
7676
%b = bitcast <1 x i16> %a to i16
@@ -80,7 +80,7 @@ define i16 @bitcast_v1i16_i16(<1 x i16> %a) {
8080
define i32 @bitcast_v4i8_i32(<4 x i8> %a) {
8181
; CHECK-LABEL: bitcast_v4i8_i32:
8282
; CHECK: # %bb.0:
83-
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
83+
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
8484
; CHECK-NEXT: vmv.x.s a0, v8
8585
; CHECK-NEXT: ret
8686
;
@@ -96,7 +96,7 @@ define i32 @bitcast_v4i8_i32(<4 x i8> %a) {
9696
define i32 @bitcast_v2i16_i32(<2 x i16> %a) {
9797
; CHECK-LABEL: bitcast_v2i16_i32:
9898
; CHECK: # %bb.0:
99-
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
99+
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
100100
; CHECK-NEXT: vmv.x.s a0, v8
101101
; CHECK-NEXT: ret
102102
;
@@ -112,7 +112,7 @@ define i32 @bitcast_v2i16_i32(<2 x i16> %a) {
112112
define i32 @bitcast_v1i32_i32(<1 x i32> %a) {
113113
; CHECK-LABEL: bitcast_v1i32_i32:
114114
; CHECK: # %bb.0:
115-
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
115+
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
116116
; CHECK-NEXT: vmv.x.s a0, v8
117117
; CHECK-NEXT: ret
118118
;
@@ -433,13 +433,13 @@ define double @bitcast_v1i64_f64(<1 x i64> %a) {
433433
define <1 x i16> @bitcast_i16_v1i16(i16 %a) {
434434
; CHECK-LABEL: bitcast_i16_v1i16:
435435
; CHECK: # %bb.0:
436-
; CHECK-NEXT: vsetivli zero, 1, e16, mf4, ta, ma
436+
; CHECK-NEXT: vsetivli zero, 1, e16, m1, ta, ma
437437
; CHECK-NEXT: vmv.s.x v8, a0
438438
; CHECK-NEXT: ret
439439
;
440440
; ELEN32-LABEL: bitcast_i16_v1i16:
441441
; ELEN32: # %bb.0:
442-
; ELEN32-NEXT: vsetivli zero, 1, e16, mf2, ta, ma
442+
; ELEN32-NEXT: vsetivli zero, 1, e16, m1, ta, ma
443443
; ELEN32-NEXT: vmv.s.x v8, a0
444444
; ELEN32-NEXT: ret
445445
%b = bitcast i16 %a to <1 x i16>
@@ -449,7 +449,7 @@ define <1 x i16> @bitcast_i16_v1i16(i16 %a) {
449449
define <2 x i16> @bitcast_i32_v2i16(i32 %a) {
450450
; CHECK-LABEL: bitcast_i32_v2i16:
451451
; CHECK: # %bb.0:
452-
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
452+
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
453453
; CHECK-NEXT: vmv.s.x v8, a0
454454
; CHECK-NEXT: ret
455455
;
@@ -465,7 +465,7 @@ define <2 x i16> @bitcast_i32_v2i16(i32 %a) {
465465
define <1 x i32> @bitcast_i32_v1i32(i32 %a) {
466466
; CHECK-LABEL: bitcast_i32_v1i32:
467467
; CHECK: # %bb.0:
468-
; CHECK-NEXT: vsetivli zero, 1, e32, mf2, ta, ma
468+
; CHECK-NEXT: vsetivli zero, 1, e32, m1, ta, ma
469469
; CHECK-NEXT: vmv.s.x v8, a0
470470
; CHECK-NEXT: ret
471471
;

0 commit comments

Comments
 (0)