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Update documentation on x86 constraint codes (#68830)
This updates the documentation on these inline asm constraint codes to match reality. Context: #68818 (comment) Note: dropping also the `'o'` from the docs because I can't find any mention of it in X86ISelLowering.cpp.
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llvm/docs/LangRef.rst

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@@ -5282,7 +5282,6 @@ X86:
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- ``O``: An immediate integer between 0 and 127.
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- ``e``: An immediate 32-bit signed integer.
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- ``Z``: An immediate 32-bit unsigned integer.
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- ``o``, ``v``: Treated the same as ``m``, at the moment.
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- ``q``: An 8, 16, 32, or 64-bit register which can be accessed as an 8-bit
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``l`` integer register. On X86-32, this is the ``a``, ``b``, ``c``, and ``d``
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registers, and on X86-64, it is all of the integer registers.
@@ -5293,10 +5292,13 @@ X86:
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existed since i386, and can be accessed without the REX prefix.
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- ``f``: A 32, 64, or 80-bit '387 FPU stack pseudo-register.
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- ``y``: A 64-bit MMX register, if MMX is enabled.
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- ``x``: If SSE is enabled: a 32 or 64-bit scalar operand, or 128-bit vector
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- ``v``: If SSE is enabled: a 32 or 64-bit scalar operand, or 128-bit vector
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operand in a SSE register. If AVX is also enabled, can also be a 256-bit
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vector operand in an AVX register. If AVX-512 is also enabled, can also be a
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512-bit vector operand in an AVX512 register, Otherwise, an error.
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512-bit vector operand in an AVX512 register. Otherwise, an error.
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- ``x``: The same as ``v``, except that when AVX-512 is enabled, the ``x`` code
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only allocates into the first 16 AVX-512 registers, while the ``v`` code
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allocates into any of the 32 AVX-512 registers.
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- ``Y``: The same as ``x``, if *SSE2* is enabled, otherwise an error.
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- ``A``: Special case: allocates EAX first, then EDX, for a single operand (in
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32-bit mode, a 64-bit integer operand will get split into two registers). It

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