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tgymnichtru
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[PowerPC] Respect endianness when bitcasting to fp128 (#95931)
Fixes #92246 Match the behaviour of `bitcast v2i64 (BUILD_PAIR %lo %hi)` when encountering `bitcast fp128 (BUILD_PAIR %lo $hi)`. by inserting a missing swap of the arguments based on endianness. ### Current behaviour: **fp128** bitcast fp128 (BUILD_PAIR %lo $hi) => BUILD_FP128 %lo %hi BUILD_FP128 %lo %hi => MTVSRDD %hi %lo **v2i64** bitcast v2i64 (BUILD_PAIR %lo %hi) => BUILD_VECTOR %hi %lo BUILD_VECTOR %hi %lo => MTVSRDD %lo %hi (cherry picked from commit 408d82d)
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-11
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llvm/lib/Target/PowerPC/PPCISelLowering.cpp

+9-5
Original file line numberDiff line numberDiff line change
@@ -9338,14 +9338,18 @@ SDValue PPCTargetLowering::LowerBITCAST(SDValue Op, SelectionDAG &DAG) const {
93389338
SDLoc dl(Op);
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SDValue Op0 = Op->getOperand(0);
93409340

9341+
SDValue Lo = Op0.getOperand(0);
9342+
SDValue Hi = Op0.getOperand(1);
9343+
93419344
if ((Op.getValueType() != MVT::f128) ||
9342-
(Op0.getOpcode() != ISD::BUILD_PAIR) ||
9343-
(Op0.getOperand(0).getValueType() != MVT::i64) ||
9344-
(Op0.getOperand(1).getValueType() != MVT::i64) || !Subtarget.isPPC64())
9345+
(Op0.getOpcode() != ISD::BUILD_PAIR) || (Lo.getValueType() != MVT::i64) ||
9346+
(Hi.getValueType() != MVT::i64) || !Subtarget.isPPC64())
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return SDValue();
93469348

9347-
return DAG.getNode(PPCISD::BUILD_FP128, dl, MVT::f128, Op0.getOperand(0),
9348-
Op0.getOperand(1));
9349+
if (!Subtarget.isLittleEndian())
9350+
std::swap(Lo, Hi);
9351+
9352+
return DAG.getNode(PPCISD::BUILD_FP128, dl, MVT::f128, Lo, Hi);
93499353
}
93509354

93519355
static const SDValue *getNormalLoadInput(const SDValue &Op, bool &IsPermuted) {

llvm/test/CodeGen/PowerPC/f128-aggregates.ll

+6-6
Original file line numberDiff line numberDiff line change
@@ -283,7 +283,7 @@ define fp128 @testMixedAggregate([3 x i128] %a.coerce) {
283283
;
284284
; CHECK-BE-LABEL: testMixedAggregate:
285285
; CHECK-BE: # %bb.0: # %entry
286-
; CHECK-BE-NEXT: mtvsrdd v2, r8, r7
286+
; CHECK-BE-NEXT: mtvsrdd v2, r7, r8
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; CHECK-BE-NEXT: blr
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;
289289
; CHECK-P8-LABEL: testMixedAggregate:
@@ -310,7 +310,7 @@ define fp128 @testMixedAggregate_02([4 x i128] %a.coerce) {
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;
311311
; CHECK-BE-LABEL: testMixedAggregate_02:
312312
; CHECK-BE: # %bb.0: # %entry
313-
; CHECK-BE-NEXT: mtvsrdd v2, r6, r5
313+
; CHECK-BE-NEXT: mtvsrdd v2, r5, r6
314314
; CHECK-BE-NEXT: blr
315315
;
316316
; CHECK-P8-LABEL: testMixedAggregate_02:
@@ -344,7 +344,7 @@ define fp128 @testMixedAggregate_03([4 x i128] %sa.coerce) {
344344
; CHECK-BE-LABEL: testMixedAggregate_03:
345345
; CHECK-BE: # %bb.0: # %entry
346346
; CHECK-BE-NEXT: mtvsrwa v2, r4
347-
; CHECK-BE-NEXT: mtvsrdd v3, r6, r5
347+
; CHECK-BE-NEXT: mtvsrdd v3, r5, r6
348348
; CHECK-BE-NEXT: xscvsdqp v2, v2
349349
; CHECK-BE-NEXT: xsaddqp v2, v3, v2
350350
; CHECK-BE-NEXT: mtvsrd v3, r9
@@ -467,7 +467,7 @@ define fp128 @testUnion_01([1 x i128] %a.coerce) {
467467
;
468468
; CHECK-BE-LABEL: testUnion_01:
469469
; CHECK-BE: # %bb.0: # %entry
470-
; CHECK-BE-NEXT: mtvsrdd v2, r4, r3
470+
; CHECK-BE-NEXT: mtvsrdd v2, r3, r4
471471
; CHECK-BE-NEXT: blr
472472
;
473473
; CHECK-P8-LABEL: testUnion_01:
@@ -494,7 +494,7 @@ define fp128 @testUnion_02([1 x i128] %a.coerce) {
494494
;
495495
; CHECK-BE-LABEL: testUnion_02:
496496
; CHECK-BE: # %bb.0: # %entry
497-
; CHECK-BE-NEXT: mtvsrdd v2, r4, r3
497+
; CHECK-BE-NEXT: mtvsrdd v2, r3, r4
498498
; CHECK-BE-NEXT: blr
499499
;
500500
; CHECK-P8-LABEL: testUnion_02:
@@ -521,7 +521,7 @@ define fp128 @testUnion_03([4 x i128] %a.coerce) {
521521
;
522522
; CHECK-BE-LABEL: testUnion_03:
523523
; CHECK-BE: # %bb.0: # %entry
524-
; CHECK-BE-NEXT: mtvsrdd v2, r8, r7
524+
; CHECK-BE-NEXT: mtvsrdd v2, r7, r8
525525
; CHECK-BE-NEXT: blr
526526
;
527527
; CHECK-P8-LABEL: testUnion_03:

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