[ADT] Make use of subsetOf and anyCommon methods of BitVector (NFC)

Replace the code along these lines

    BitVector Tmp = LHS;
    Tmp &= RHS;
    return Tmp.any();

and

    BitVector Tmp = LHS;
    Tmp.reset(RHS);
    return Tmp.none();

with `LHS.anyCommon(RHS)` and `LHS.subsetOf(RHS)`, correspondingly, which
do not require creating temporary BitVector and can return early.

Author: atrosinenko

bolt/include/bolt/Passes/LivenessAnalysis.h

@@ -37,10 +37,9 @@ class LivenessAnalysis : public DataflowAnalysis<LivenessAnalysis, BitVector,
   virtual ~LivenessAnalysis();
 
   bool isAlive(ProgramPoint PP, MCPhysReg Reg) const {
-    BitVector BV = (*this->getStateAt(PP));
+    const BitVector &BV = *this->getStateAt(PP);
     const BitVector &RegAliases = BC.MIB->getAliases(Reg);
-    BV &= RegAliases;
-    return BV.any();
+    return BV.anyCommon(RegAliases);
   }
 
   void run() { Parent::run(); }

bolt/include/bolt/Passes/ReachingDefOrUse.h

@@ -133,8 +133,7 @@ class ReachingDefOrUse
           RA.getInstClobberList(Point, Regs);
         else
           RA.getInstUsedRegsList(Point, Regs, false);
-        Regs &= this->BC.MIB->getAliases(*TrackingReg);
-        if (Regs.any())
+        if (Regs.anyCommon(this->BC.MIB->getAliases(*TrackingReg)))
           Next.set(this->ExprToIdx[&Point]);
       }
     }

bolt/lib/Passes/RegReAssign.cpp

@@ -316,18 +316,14 @@ void RegReAssign::aggressivePassOverFunction(BinaryFunction &Function) {
       break;
     }
 
-    BitVector AnyAliasAlive = AliveAtStart;
-    AnyAliasAlive &= BC.MIB->getAliases(ClassicReg);
-    if (AnyAliasAlive.any()) {
+    if (AliveAtStart.anyCommon(BC.MIB->getAliases(ClassicReg))) {
       LLVM_DEBUG(dbgs() << " Bailed on " << BC.MRI->getName(ClassicReg)
                         << " with " << BC.MRI->getName(ExtReg)
                         << " because classic reg is alive\n");
       --End;
       continue;
     }
-    AnyAliasAlive = AliveAtStart;
-    AnyAliasAlive &= BC.MIB->getAliases(ExtReg);
-    if (AnyAliasAlive.any()) {
+    if (AliveAtStart.anyCommon(BC.MIB->getAliases(ExtReg))) {
       LLVM_DEBUG(dbgs() << " Bailed on " << BC.MRI->getName(ClassicReg)
                         << " with " << BC.MRI->getName(ExtReg)
                         << " because extended reg is alive\n");

bolt/lib/Passes/ShrinkWrapping.cpp

@@ -1100,19 +1100,17 @@ SmallVector<ProgramPoint, 4> ShrinkWrapping::fixPopsPlacements(
     bool Found = false;
     if (SPT.getStateAt(ProgramPoint::getLastPointAt(*BB))->first ==
         SaveOffset) {
-      BitVector BV = *RI.getStateAt(ProgramPoint::getLastPointAt(*BB));
-      BV &= UsesByReg[CSR];
-      if (!BV.any()) {
+      const BitVector &BV = *RI.getStateAt(ProgramPoint::getLastPointAt(*BB));
+      if (!BV.anyCommon(UsesByReg[CSR])) {
         Found = true;
         PP = BB;
         continue;
       }
     }
     for (MCInst &Inst : llvm::reverse(*BB)) {
       if (SPT.getStateBefore(Inst)->first == SaveOffset) {
-        BitVector BV = *RI.getStateAt(Inst);
-        BV &= UsesByReg[CSR];
-        if (!BV.any()) {
+        const BitVector &BV = *RI.getStateAt(Inst);
+        if (!BV.anyCommon(UsesByReg[CSR])) {
           Found = true;
           PP = &Inst;
           break;

bolt/lib/Passes/StackAvailableExpressions.cpp

@@ -103,8 +103,7 @@ bool StackAvailableExpressions::doesXKillsY(const MCInst *X, const MCInst *Y) {
   else
     RA.getInstClobberList(*Y, YClobbers);
 
-  XClobbers &= YClobbers;
-  return XClobbers.any();
+  return XClobbers.anyCommon(YClobbers);
 }
 
 BitVector StackAvailableExpressions::computeNext(const MCInst &Point,

bolt/lib/Passes/TailDuplication.cpp

@@ -97,8 +97,8 @@ bool TailDuplication::regIsPossiblyOverwritten(const MCInst &Inst, unsigned Reg,
   getCallerSavedRegs(Inst, WrittenRegs, BC);
   if (BC.MIB->isRep(Inst))
     BC.MIB->getRepRegs(WrittenRegs);
-  WrittenRegs &= BC.MIB->getAliases(Reg, false);
-  return WrittenRegs.any();
+  const BitVector &AllAliases = BC.MIB->getAliases(Reg, false);
+  return WrittenRegs.anyCommon(AllAliases);
 }
 
 bool TailDuplication::regIsDefinitelyOverwritten(const MCInst &Inst,
@@ -117,8 +117,8 @@ bool TailDuplication::regIsUsed(const MCInst &Inst, unsigned Reg,
                                 BinaryContext &BC) const {
   BitVector SrcRegs = BitVector(BC.MRI->getNumRegs(), false);
   BC.MIB->getSrcRegs(Inst, SrcRegs);
-  SrcRegs &= BC.MIB->getAliases(Reg, true);
-  return SrcRegs.any();
+  const BitVector &SmallerAliases = BC.MIB->getAliases(Reg, true);
+  return SrcRegs.anyCommon(SmallerAliases);
 }
 
 bool TailDuplication::isOverwrittenBeforeUsed(BinaryBasicBlock &StartBB,

llvm/lib/CodeGen/RDFRegisters.cpp

@@ -287,10 +287,8 @@ bool RegisterAggr::hasAliasOf(RegisterRef RR) const {
 }
 
 bool RegisterAggr::hasCoverOf(RegisterRef RR) const {
-  if (RR.isMask()) {
-    BitVector T(PRI.getMaskUnits(RR));
-    return T.reset(Units).none();
-  }
+  if (RR.isMask())
+    return PRI.getMaskUnits(RR).subsetOf(Units);
 
   for (MCRegUnitMaskIterator U(RR.asMCReg(), &PRI.getTRI()); U.isValid(); ++U) {
     auto [Unit, LaneMask] = *U;

llvm/tools/llvm-exegesis/lib/SnippetGenerator.cpp

@@ -274,11 +274,9 @@ static Error randomizeMCOperand(const LLVMState &State,
     break;
   case MCOI::OperandType::OPERAND_REGISTER: {
     assert(Op.isReg());
-    auto AllowedRegs = Op.getRegisterAliasing().sourceBits();
+    const BitVector &AllowedRegs = Op.getRegisterAliasing().sourceBits();
     assert(AllowedRegs.size() == ForbiddenRegs.size());
-    for (auto I : ForbiddenRegs.set_bits())
-      AllowedRegs.reset(I);
-    if (!AllowedRegs.any())
+    if (AllowedRegs.subsetOf(ForbiddenRegs))
       return make_error<Failure>(
           Twine("no available registers:\ncandidates:\n")
               .concat(debugString(State.getRegInfo(),