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[SROA] Use !tbaa instead of !tbaa.struct if op matches field. (#81289)
If a split memory access introduced by SROA accesses precisely a single field of the original operation's !tbaa.struct, use the !tbaa tag for the accessed field directly instead of the full !tbaa.struct. InstCombine already had a similar logic. Motivation for this and follow-on patches is to improve codegen for libc++, where using memcpy limits optimizations, like vectorization for code iteration over std::vector<std::complex<float>>: https://godbolt.org/z/f3vqYos3c Depends on #81285.
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6 files changed

+115
-73
lines changed

6 files changed

+115
-73
lines changed

‎clang/test/CodeGen/aarch64-ABI-align-packed.c‎

Lines changed: 14 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -59,7 +59,7 @@ struct non_packed_struct gs_non_packed_struct;
5959
// CHECK-NEXT: entry:
6060
// CHECK-NEXT: [[S_NON_PACKED_STRUCT_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [1 x <8 x i16>] [[S_NON_PACKED_STRUCT_COERCE]], 0
6161
// CHECK-NEXT: store double [[D8]], ptr @gd, align 8, !tbaa [[TBAA2:![0-9]+]]
62-
// CHECK-NEXT: store <8 x i16> [[S_NON_PACKED_STRUCT_COERCE_FCA_0_EXTRACT]], ptr @gs_non_packed_struct, align 16, !tbaa.struct [[TBAA_STRUCT6:![0-9]+]]
62+
// CHECK-NEXT: store <8 x i16> [[S_NON_PACKED_STRUCT_COERCE_FCA_0_EXTRACT]], ptr @gs_non_packed_struct, align 16, !tbaa [[TBAA6:![0-9]+]]
6363
// CHECK-NEXT: ret void
6464
__attribute__((noinline)) void named_arg_non_packed_struct(double d0, double d1, double d2, double d3,
6565
double d4, double d5, double d6, double d7,
@@ -114,7 +114,7 @@ struct packed_struct gs_packed_struct;
114114
// CHECK-NEXT: entry:
115115
// CHECK-NEXT: [[S_PACKED_STRUCT_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [1 x <8 x i16>] [[S_PACKED_STRUCT_COERCE]], 0
116116
// CHECK-NEXT: store double [[D8]], ptr @gd, align 8, !tbaa [[TBAA2]]
117-
// CHECK-NEXT: store <8 x i16> [[S_PACKED_STRUCT_COERCE_FCA_0_EXTRACT]], ptr @gs_packed_struct, align 1, !tbaa.struct [[TBAA_STRUCT6]]
117+
// CHECK-NEXT: store <8 x i16> [[S_PACKED_STRUCT_COERCE_FCA_0_EXTRACT]], ptr @gs_packed_struct, align 1, !tbaa [[TBAA6]]
118118
// CHECK-NEXT: ret void
119119
__attribute__((noinline)) void named_arg_packed_struct(double d0, double d1, double d2, double d3,
120120
double d4, double d5, double d6, double d7,
@@ -169,7 +169,7 @@ struct packed_member gs_packed_member;
169169
// CHECK-NEXT: entry:
170170
// CHECK-NEXT: [[S_PACKED_MEMBER_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [1 x <8 x i16>] [[S_PACKED_MEMBER_COERCE]], 0
171171
// CHECK-NEXT: store double [[D8]], ptr @gd, align 8, !tbaa [[TBAA2]]
172-
// CHECK-NEXT: store <8 x i16> [[S_PACKED_MEMBER_COERCE_FCA_0_EXTRACT]], ptr @gs_packed_member, align 1, !tbaa.struct [[TBAA_STRUCT6]]
172+
// CHECK-NEXT: store <8 x i16> [[S_PACKED_MEMBER_COERCE_FCA_0_EXTRACT]], ptr @gs_packed_member, align 1, !tbaa [[TBAA6]]
173173
// CHECK-NEXT: ret void
174174
__attribute__((noinline)) void named_arg_packed_member(double d0, double d1, double d2, double d3,
175175
double d4, double d5, double d6, double d7,
@@ -224,7 +224,7 @@ struct aligned_struct_8 gs_aligned_struct_8;
224224
// CHECK-NEXT: entry:
225225
// CHECK-NEXT: [[S_ALIGNED_STRUCT_8_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [1 x <8 x i16>] [[S_ALIGNED_STRUCT_8_COERCE]], 0
226226
// CHECK-NEXT: store double [[D8]], ptr @gd, align 8, !tbaa [[TBAA2]]
227-
// CHECK-NEXT: store <8 x i16> [[S_ALIGNED_STRUCT_8_COERCE_FCA_0_EXTRACT]], ptr @gs_aligned_struct_8, align 16, !tbaa.struct [[TBAA_STRUCT6]]
227+
// CHECK-NEXT: store <8 x i16> [[S_ALIGNED_STRUCT_8_COERCE_FCA_0_EXTRACT]], ptr @gs_aligned_struct_8, align 16, !tbaa [[TBAA6]]
228228
// CHECK-NEXT: ret void
229229
__attribute__((noinline)) void named_arg_aligned_struct_8(double d0, double d1, double d2, double d3,
230230
double d4, double d5, double d6, double d7,
@@ -279,7 +279,7 @@ struct aligned_member_8 gs_aligned_member_8;
279279
// CHECK-NEXT: entry:
280280
// CHECK-NEXT: [[S_ALIGNED_MEMBER_8_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [1 x <8 x i16>] [[S_ALIGNED_MEMBER_8_COERCE]], 0
281281
// CHECK-NEXT: store double [[D8]], ptr @gd, align 8, !tbaa [[TBAA2]]
282-
// CHECK-NEXT: store <8 x i16> [[S_ALIGNED_MEMBER_8_COERCE_FCA_0_EXTRACT]], ptr @gs_aligned_member_8, align 16, !tbaa.struct [[TBAA_STRUCT6]]
282+
// CHECK-NEXT: store <8 x i16> [[S_ALIGNED_MEMBER_8_COERCE_FCA_0_EXTRACT]], ptr @gs_aligned_member_8, align 16, !tbaa [[TBAA6]]
283283
// CHECK-NEXT: ret void
284284
__attribute__((noinline)) void named_arg_aligned_member_8(double d0, double d1, double d2, double d3,
285285
double d4, double d5, double d6, double d7,
@@ -334,7 +334,7 @@ struct pragma_packed_struct_8 gs_pragma_packed_struct_8;
334334
// CHECK-NEXT: entry:
335335
// CHECK-NEXT: [[S_PRAGMA_PACKED_STRUCT_8_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [1 x <8 x i16>] [[S_PRAGMA_PACKED_STRUCT_8_COERCE]], 0
336336
// CHECK-NEXT: store double [[D8]], ptr @gd, align 8, !tbaa [[TBAA2]]
337-
// CHECK-NEXT: store <8 x i16> [[S_PRAGMA_PACKED_STRUCT_8_COERCE_FCA_0_EXTRACT]], ptr @gs_pragma_packed_struct_8, align 8, !tbaa.struct [[TBAA_STRUCT6]]
337+
// CHECK-NEXT: store <8 x i16> [[S_PRAGMA_PACKED_STRUCT_8_COERCE_FCA_0_EXTRACT]], ptr @gs_pragma_packed_struct_8, align 8, !tbaa [[TBAA6]]
338338
// CHECK-NEXT: ret void
339339
__attribute__((noinline)) void named_arg_pragma_packed_struct_8(double d0, double d1, double d2, double d3,
340340
double d4, double d5, double d6, double d7,
@@ -389,7 +389,7 @@ struct pragma_packed_struct_4 gs_pragma_packed_struct_4;
389389
// CHECK-NEXT: entry:
390390
// CHECK-NEXT: [[S_PRAGMA_PACKED_STRUCT_4_COERCE_FCA_0_EXTRACT:%.*]] = extractvalue [1 x <8 x i16>] [[S_PRAGMA_PACKED_STRUCT_4_COERCE]], 0
391391
// CHECK-NEXT: store double [[D8]], ptr @gd, align 8, !tbaa [[TBAA2]]
392-
// CHECK-NEXT: store <8 x i16> [[S_PRAGMA_PACKED_STRUCT_4_COERCE_FCA_0_EXTRACT]], ptr @gs_pragma_packed_struct_4, align 4, !tbaa.struct [[TBAA_STRUCT6]]
392+
// CHECK-NEXT: store <8 x i16> [[S_PRAGMA_PACKED_STRUCT_4_COERCE_FCA_0_EXTRACT]], ptr @gs_pragma_packed_struct_4, align 4, !tbaa [[TBAA6]]
393393
// CHECK-NEXT: ret void
394394
__attribute__((noinline)) void named_arg_pragma_packed_struct_4(double d0, double d1, double d2, double d3,
395395
double d4, double d5, double d6, double d7,
@@ -436,3 +436,10 @@ void test_pragma_packed_struct_4() {
436436
named_arg_pragma_packed_struct_4(1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 2.0, s_pragma_packed_struct_4);
437437
variadic_pragma_packed_struct_4(1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 1.0, 2.0, s_pragma_packed_struct_4);
438438
}
439+
//.
440+
// CHECK: [[TBAA2]] = !{[[META3:![0-9]+]], [[META3]], i64 0}
441+
// CHECK: [[META3]] = !{!"double", [[META4:![0-9]+]], i64 0}
442+
// CHECK: [[META4]] = !{!"omnipotent char", [[META5:![0-9]+]], i64 0}
443+
// CHECK: [[META5]] = !{!"Simple C/C++ TBAA"}
444+
// CHECK: [[TBAA6]] = !{[[META4]], [[META4]], i64 0}
445+
//.

‎llvm/include/llvm/IR/Metadata.h‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -849,6 +849,9 @@ struct AAMDNodes {
849849
/// If his AAMDNode has !tbaa.struct and \p AccessSize matches the size of the
850850
/// field at offset 0, get the TBAA tag describing the accessed field.
851851
AAMDNodes adjustForAccess(unsigned AccessSize);
852+
AAMDNodes adjustForAccess(size_t Offset, Type *AccessTy,
853+
const DataLayout &DL);
854+
AAMDNodes adjustForAccess(size_t Offset, unsigned AccessSize);
852855
};
853856

854857
// Specialize DenseMapInfo for AAMDNodes.

‎llvm/lib/Analysis/TypeBasedAliasAnalysis.cpp‎

Lines changed: 17 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -833,3 +833,20 @@ AAMDNodes AAMDNodes::adjustForAccess(unsigned AccessSize) {
833833
}
834834
return New;
835835
}
836+
837+
AAMDNodes AAMDNodes::adjustForAccess(size_t Offset, Type *AccessTy,
838+
const DataLayout &DL) {
839+
AAMDNodes New = shift(Offset);
840+
if (!DL.typeSizeEqualsStoreSize(AccessTy))
841+
return New;
842+
TypeSize Size = DL.getTypeStoreSize(AccessTy);
843+
if (Size.isScalable())
844+
return New;
845+
846+
return New.adjustForAccess(Size.getKnownMinValue());
847+
}
848+
849+
AAMDNodes AAMDNodes::adjustForAccess(size_t Offset, unsigned AccessSize) {
850+
AAMDNodes New = shift(Offset);
851+
return New.adjustForAccess(AccessSize);
852+
}

‎llvm/lib/Transforms/Scalar/SROA.cpp‎

Lines changed: 33 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -2914,7 +2914,8 @@ class AllocaSliceRewriter : public InstVisitor<AllocaSliceRewriter, bool> {
29142914

29152915
// Do this after copyMetadataForLoad() to preserve the TBAA shift.
29162916
if (AATags)
2917-
NewLI->setAAMetadata(AATags.shift(NewBeginOffset - BeginOffset));
2917+
NewLI->setAAMetadata(AATags.adjustForAccess(
2918+
NewBeginOffset - BeginOffset, NewLI->getType(), DL));
29182919

29192920
// Try to preserve nonnull metadata
29202921
V = NewLI;
@@ -2935,8 +2936,11 @@ class AllocaSliceRewriter : public InstVisitor<AllocaSliceRewriter, bool> {
29352936
LoadInst *NewLI =
29362937
IRB.CreateAlignedLoad(TargetTy, getNewAllocaSlicePtr(IRB, LTy),
29372938
getSliceAlign(), LI.isVolatile(), LI.getName());
2939+
29382940
if (AATags)
2939-
NewLI->setAAMetadata(AATags.shift(NewBeginOffset - BeginOffset));
2941+
NewLI->setAAMetadata(AATags.adjustForAccess(
2942+
NewBeginOffset - BeginOffset, NewLI->getType(), DL));
2943+
29402944
if (LI.isVolatile())
29412945
NewLI->setAtomic(LI.getOrdering(), LI.getSyncScopeID());
29422946
NewLI->copyMetadata(LI, {LLVMContext::MD_mem_parallel_loop_access,
@@ -3011,7 +3015,8 @@ class AllocaSliceRewriter : public InstVisitor<AllocaSliceRewriter, bool> {
30113015
Store->copyMetadata(SI, {LLVMContext::MD_mem_parallel_loop_access,
30123016
LLVMContext::MD_access_group});
30133017
if (AATags)
3014-
Store->setAAMetadata(AATags.shift(NewBeginOffset - BeginOffset));
3018+
Store->setAAMetadata(AATags.adjustForAccess(NewBeginOffset - BeginOffset,
3019+
V->getType(), DL));
30153020
Pass.DeadInsts.push_back(&SI);
30163021

30173022
// NOTE: Careful to use OrigV rather than V.
@@ -3038,7 +3043,8 @@ class AllocaSliceRewriter : public InstVisitor<AllocaSliceRewriter, bool> {
30383043
Store->copyMetadata(SI, {LLVMContext::MD_mem_parallel_loop_access,
30393044
LLVMContext::MD_access_group});
30403045
if (AATags)
3041-
Store->setAAMetadata(AATags.shift(NewBeginOffset - BeginOffset));
3046+
Store->setAAMetadata(AATags.adjustForAccess(NewBeginOffset - BeginOffset,
3047+
V->getType(), DL));
30423048

30433049
migrateDebugInfo(&OldAI, IsSplit, NewBeginOffset * 8, SliceSize * 8, &SI,
30443050
Store, Store->getPointerOperand(),
@@ -3098,7 +3104,8 @@ class AllocaSliceRewriter : public InstVisitor<AllocaSliceRewriter, bool> {
30983104
NewSI->copyMetadata(SI, {LLVMContext::MD_mem_parallel_loop_access,
30993105
LLVMContext::MD_access_group});
31003106
if (AATags)
3101-
NewSI->setAAMetadata(AATags.shift(NewBeginOffset - BeginOffset));
3107+
NewSI->setAAMetadata(AATags.adjustForAccess(NewBeginOffset - BeginOffset,
3108+
V->getType(), DL));
31023109
if (SI.isVolatile())
31033110
NewSI->setAtomic(SI.getOrdering(), SI.getSyncScopeID());
31043111
if (NewSI->isAtomic())
@@ -3200,12 +3207,14 @@ class AllocaSliceRewriter : public InstVisitor<AllocaSliceRewriter, bool> {
32003207
// a single value type, just emit a memset.
32013208
if (!CanContinue) {
32023209
Type *SizeTy = II.getLength()->getType();
3203-
Constant *Size = ConstantInt::get(SizeTy, NewEndOffset - NewBeginOffset);
3210+
unsigned Sz = NewEndOffset - NewBeginOffset;
3211+
Constant *Size = ConstantInt::get(SizeTy, Sz);
32043212
MemIntrinsic *New = cast<MemIntrinsic>(IRB.CreateMemSet(
32053213
getNewAllocaSlicePtr(IRB, OldPtr->getType()), II.getValue(), Size,
32063214
MaybeAlign(getSliceAlign()), II.isVolatile()));
32073215
if (AATags)
3208-
New->setAAMetadata(AATags.shift(NewBeginOffset - BeginOffset));
3216+
New->setAAMetadata(
3217+
AATags.adjustForAccess(NewBeginOffset - BeginOffset, Sz));
32093218

32103219
migrateDebugInfo(&OldAI, IsSplit, NewBeginOffset * 8, SliceSize * 8, &II,
32113220
New, New->getRawDest(), nullptr, DL);
@@ -3281,7 +3290,8 @@ class AllocaSliceRewriter : public InstVisitor<AllocaSliceRewriter, bool> {
32813290
New->copyMetadata(II, {LLVMContext::MD_mem_parallel_loop_access,
32823291
LLVMContext::MD_access_group});
32833292
if (AATags)
3284-
New->setAAMetadata(AATags.shift(NewBeginOffset - BeginOffset));
3293+
New->setAAMetadata(AATags.adjustForAccess(NewBeginOffset - BeginOffset,
3294+
V->getType(), DL));
32853295

32863296
migrateDebugInfo(&OldAI, IsSplit, NewBeginOffset * 8, SliceSize * 8, &II,
32873297
New, New->getPointerOperand(), V, DL);
@@ -3486,7 +3496,8 @@ class AllocaSliceRewriter : public InstVisitor<AllocaSliceRewriter, bool> {
34863496
Load->copyMetadata(II, {LLVMContext::MD_mem_parallel_loop_access,
34873497
LLVMContext::MD_access_group});
34883498
if (AATags)
3489-
Load->setAAMetadata(AATags.shift(NewBeginOffset - BeginOffset));
3499+
Load->setAAMetadata(AATags.adjustForAccess(NewBeginOffset - BeginOffset,
3500+
Load->getType(), DL));
34903501
Src = Load;
34913502
}
34923503

@@ -3508,7 +3519,8 @@ class AllocaSliceRewriter : public InstVisitor<AllocaSliceRewriter, bool> {
35083519
Store->copyMetadata(II, {LLVMContext::MD_mem_parallel_loop_access,
35093520
LLVMContext::MD_access_group});
35103521
if (AATags)
3511-
Store->setAAMetadata(AATags.shift(NewBeginOffset - BeginOffset));
3522+
Store->setAAMetadata(AATags.adjustForAccess(NewBeginOffset - BeginOffset,
3523+
Src->getType(), DL));
35123524

35133525
APInt Offset(DL.getIndexTypeSizeInBits(DstPtr->getType()), 0);
35143526
if (IsDest) {
@@ -3836,7 +3848,8 @@ class AggLoadStoreRewriter : public InstVisitor<AggLoadStoreRewriter, bool> {
38363848
DL.getIndexSizeInBits(Ptr->getType()->getPointerAddressSpace()), 0);
38373849
if (AATags &&
38383850
GEPOperator::accumulateConstantOffset(BaseTy, GEPIndices, DL, Offset))
3839-
Load->setAAMetadata(AATags.shift(Offset.getZExtValue()));
3851+
Load->setAAMetadata(
3852+
AATags.adjustForAccess(Offset.getZExtValue(), Load->getType(), DL));
38403853

38413854
Agg = IRB.CreateInsertValue(Agg, Load, Indices, Name + ".insert");
38423855
LLVM_DEBUG(dbgs() << " to: " << *Load << "\n");
@@ -3887,8 +3900,10 @@ class AggLoadStoreRewriter : public InstVisitor<AggLoadStoreRewriter, bool> {
38873900
APInt Offset(
38883901
DL.getIndexSizeInBits(Ptr->getType()->getPointerAddressSpace()), 0);
38893902
GEPOperator::accumulateConstantOffset(BaseTy, GEPIndices, DL, Offset);
3890-
if (AATags)
3891-
Store->setAAMetadata(AATags.shift(Offset.getZExtValue()));
3903+
if (AATags) {
3904+
Store->setAAMetadata(AATags.adjustForAccess(
3905+
Offset.getZExtValue(), ExtractValue->getType(), DL));
3906+
}
38923907

38933908
// migrateDebugInfo requires the base Alloca. Walk to it from this gep.
38943909
// If we cannot (because there's an intervening non-const or unbounded
@@ -4542,6 +4557,7 @@ bool SROA::presplitLoadsAndStores(AllocaInst &AI, AllocaSlices &AS) {
45424557

45434558
Value *StoreBasePtr = SI->getPointerOperand();
45444559
IRB.SetInsertPoint(SI);
4560+
AAMDNodes AATags = SI->getAAMetadata();
45454561

45464562
LLVM_DEBUG(dbgs() << " Splitting store of load: " << *SI << "\n");
45474563

@@ -4561,6 +4577,10 @@ bool SROA::presplitLoadsAndStores(AllocaInst &AI, AllocaSlices &AS) {
45614577
PStore->copyMetadata(*SI, {LLVMContext::MD_mem_parallel_loop_access,
45624578
LLVMContext::MD_access_group,
45634579
LLVMContext::MD_DIAssignID});
4580+
4581+
if (AATags)
4582+
PStore->setAAMetadata(
4583+
AATags.adjustForAccess(PartOffset, PLoad->getType(), DL));
45644584
LLVM_DEBUG(dbgs() << " +" << PartOffset << ":" << *PStore << "\n");
45654585
}
45664586

‎llvm/test/Transforms/SROA/tbaa-struct2.ll‎

Lines changed: 10 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -13,9 +13,9 @@ define double @bar(ptr %wishart) {
1313
; CHECK-NEXT: [[TMP_SROA_3:%.*]] = alloca [4 x i8], align 4
1414
; CHECK-NEXT: [[TMP_SROA_0_0_COPYLOAD:%.*]] = load double, ptr [[WISHART:%.*]], align 8, !tbaa.struct [[TBAA_STRUCT0:![0-9]+]]
1515
; CHECK-NEXT: [[TMP_SROA_2_0_WISHART_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[WISHART]], i64 8
16-
; CHECK-NEXT: [[TMP_SROA_2_0_COPYLOAD:%.*]] = load i32, ptr [[TMP_SROA_2_0_WISHART_SROA_IDX]], align 8, !tbaa.struct [[TBAA_STRUCT7:![0-9]+]]
16+
; CHECK-NEXT: [[TMP_SROA_2_0_COPYLOAD:%.*]] = load i32, ptr [[TMP_SROA_2_0_WISHART_SROA_IDX]], align 8, !tbaa [[TBAA5:![0-9]+]]
1717
; CHECK-NEXT: [[TMP_SROA_3_0_WISHART_SROA_IDX:%.*]] = getelementptr inbounds i8, ptr [[WISHART]], i64 12
18-
; CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP_SROA_3]], ptr align 4 [[TMP_SROA_3_0_WISHART_SROA_IDX]], i64 4, i1 false), !tbaa.struct [[TBAA_STRUCT8:![0-9]+]]
18+
; CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 4 [[TMP_SROA_3]], ptr align 4 [[TMP_SROA_3_0_WISHART_SROA_IDX]], i64 4, i1 false), !tbaa.struct [[TBAA_STRUCT7:![0-9]+]]
1919
; CHECK-NEXT: [[CALL:%.*]] = call double @subcall(double [[TMP_SROA_0_0_COPYLOAD]], i32 [[TMP_SROA_2_0_COPYLOAD]])
2020
; CHECK-NEXT: ret double [[CALL]]
2121
;
@@ -38,15 +38,14 @@ define double @bar(ptr %wishart) {
3838
;.
3939
; CHECK: attributes #[[ATTR0:[0-9]+]] = { nocallback nofree nounwind willreturn memory(argmem: readwrite) }
4040
;.
41-
; CHECK: [[TBAA_STRUCT0]] = !{i64 0, i64 8, !1, i64 8, i64 4, !5}
42-
; CHECK: [[META1:![0-9]+]] = !{!2, !2, i64 0}
43-
; CHECK: [[META2:![0-9]+]] = !{!"double", !3, i64 0}
44-
; CHECK: [[META3:![0-9]+]] = !{!"omnipotent char", !4, i64 0}
45-
; CHECK: [[META4:![0-9]+]] = !{!"Simple C++ TBAA"}
46-
; CHECK: [[META5:![0-9]+]] = !{!6, !6, i64 0}
47-
; CHECK: [[META6:![0-9]+]] = !{!"int", !3, i64 0}
48-
; CHECK: [[TBAA_STRUCT7]] = !{i64 0, i64 4, !5}
49-
; CHECK: [[TBAA_STRUCT8]] = !{}
41+
; CHECK: [[TBAA_STRUCT0]] = !{i64 0, i64 8, [[META1:![0-9]+]], i64 8, i64 4, [[TBAA5]]}
42+
; CHECK: [[META1]] = !{[[META2:![0-9]+]], [[META2]], i64 0}
43+
; CHECK: [[META2]] = !{!"double", [[META3:![0-9]+]], i64 0}
44+
; CHECK: [[META3]] = !{!"omnipotent char", [[META4:![0-9]+]], i64 0}
45+
; CHECK: [[META4]] = !{!"Simple C++ TBAA"}
46+
; CHECK: [[TBAA5]] = !{[[META6:![0-9]+]], [[META6]], i64 0}
47+
; CHECK: [[META6]] = !{!"int", [[META3]], i64 0}
48+
; CHECK: [[TBAA_STRUCT7]] = !{}
5049
;.
5150
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
5251
; CHECK-MODIFY-CFG: {{.*}}

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