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kaiyan96tru
authored andcommittedSep 1, 2024·
[llvm][CodeGen] Address the issue of multiple resource reservations In window scheduling (#101665)
Address the issue of multiple resource reservations in window scheduling.

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2 files changed

+100
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‎llvm/lib/CodeGen/WindowScheduler.cpp

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Original file line numberDiff line numberDiff line change
@@ -451,7 +451,6 @@ int WindowScheduler::calculateMaxCycle(ScheduleDAGInstrs &DAG,
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}
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RM.reserveResources(*SU, CurCycle);
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}
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RM.reserveResources(*SU, CurCycle);
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OriToCycle[getOriMI(&MI)] = CurCycle;
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LLVM_DEBUG(dbgs() << "\tCycle " << CurCycle << " [S."
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<< getOriStage(getOriMI(&MI), Offset) << "]: " << MI);
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@@ -0,0 +1,100 @@
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# REQUIRES: asserts
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# RUN: llc --march=hexagon %s -run-pass=pipeliner -debug-only=pipeliner \
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# RUN: -window-sched=force -filetype=null -verify-machineinstrs 2>&1 \
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# RUN: -window-search-ratio=100 -window-search-num=100 -window-diff-limit=1 \
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# RUN: | FileCheck %s
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# We want to verify that all three V6_vaddw instructions are emitted in the same cycle.
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# CHECK-LABEL: Current window Offset is 2
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# CHECK: Cycle [[CycleNum:[0-9]+]] [{{S.[0-9]+}}]: {{%[0-9]+}}:hvxvr = V6_vaddw {{%[0-9]+}}:hvxvr, {{%[0-9]+}}:hvxvr
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# CHECK: Cycle [[CycleNum]] [{{S.[0-9]+}}]: {{%[0-9]+}}:hvxvr = V6_vaddw {{%[0-9]+}}:hvxvr, {{%[0-9]+}}:hvxvr
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# CHECK: Cycle [[CycleNum]] [{{S.[0-9]+}}]: {{%[0-9]+}}:hvxvr = V6_vaddw {{%[0-9]+}}:hvxvr, {{%[0-9]+}}:hvxvr
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# CHECK-LABEL: Current window Offset is 3
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--- |
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define void @add_parallel(i32 %N, ptr noalias %x, ptr noalias %y) {
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entry:
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%isZeroLength = icmp eq i32 %N, 0
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br i1 %isZeroLength, label %loop.exit, label %loop.preheader
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loop.preheader: ; preds = %entry
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%half_splat = tail call <32 x i32> @llvm.hexagon.V6.lvsplatw.128B(i32 1056964608)
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%one_splat = tail call <32 x i32> @llvm.hexagon.V6.lvsplatw.128B(i32 1065353216)
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%two_splat = tail call <32 x i32> @llvm.hexagon.V6.lvsplatw.128B(i32 1073741824)
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br label %loop.body
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loop.exit: ; preds = %loop.body, %entry
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ret void
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loop.body: ; preds = %loop.body, %loop.preheader
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%lsr.iv1 = phi ptr [ %cgep2, %loop.body ], [ %x, %loop.preheader ]
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%lsr.iv = phi ptr [ %cgep1, %loop.body ], [ %y, %loop.preheader ]
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%index = phi i32 [ 0, %loop.preheader ], [ %index.next, %loop.body ]
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%vec_x1 = load <32 x i32>, ptr %lsr.iv1, align 128
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%vec_add_1 = tail call <32 x i32> @llvm.hexagon.V6.vaddw.128B(<32 x i32> %one_splat, <32 x i32> %vec_x1)
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%vec_add_2 = tail call <32 x i32> @llvm.hexagon.V6.vaddw.128B(<32 x i32> %half_splat, <32 x i32> %vec_x1)
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%vec_add_3 = tail call <32 x i32> @llvm.hexagon.V6.vaddw.128B(<32 x i32> %two_splat, <32 x i32> %vec_x1)
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%vec_add_4 = tail call <32 x i32> @llvm.hexagon.V6.vaddw.128B(<32 x i32> %vec_add_1, <32 x i32> %vec_add_2)
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%vec_add_5 = tail call <32 x i32> @llvm.hexagon.V6.vaddw.128B(<32 x i32> %vec_add_1, <32 x i32> %vec_add_3)
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%vec_add_6 = tail call <32 x i32> @llvm.hexagon.V6.vaddw.128B(<32 x i32> %vec_add_5, <32 x i32> %vec_add_4)
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store <32 x i32> %vec_add_6, ptr %lsr.iv, align 128
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%index.next = add nuw i32 %index, 32
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%continue = icmp ult i32 %index.next, %N
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%cgep1 = getelementptr i8, ptr %lsr.iv, i32 128
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%cgep2 = getelementptr i8, ptr %lsr.iv1, i32 128
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br i1 %continue, label %loop.body, label %loop.exit
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}
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declare <32 x i32> @llvm.hexagon.V6.lvsplatw.128B(i32)
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declare <32 x i32> @llvm.hexagon.V6.vaddw.128B(<32 x i32>, <32 x i32>)
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...
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---
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name: add_parallel
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tracksRegLiveness: true
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body: |
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bb.0.entry:
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successors: %bb.2(0x30000000), %bb.1(0x50000000)
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liveins: $r0, $r1, $r2
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%0:intregs = COPY $r2
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%1:intregs = COPY $r1
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%2:intregs = COPY $r0
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%3:predregs = C2_cmpeqi %2, 0
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J2_jumpt killed %3, %bb.2, implicit-def dead $pc
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J2_jump %bb.1, implicit-def dead $pc
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bb.1.loop.preheader:
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successors: %bb.3(0x80000000)
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%4:intregs = A2_tfrsi 1056964608
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%5:hvxvr = V6_lvsplatw killed %4
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%6:intregs = A2_tfrsi 1065353216
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%7:hvxvr = V6_lvsplatw killed %6
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%8:intregs = A2_tfrsi 1073741824
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%9:hvxvr = V6_lvsplatw killed %8
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%10:intregs = A2_addi %2, 31
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%11:intregs = S2_lsr_i_r %10, 5
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%12:intregs = COPY %11
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J2_loop0r %bb.3, %12, implicit-def $lc0, implicit-def $sa0, implicit-def $usr
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J2_jump %bb.3, implicit-def dead $pc
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bb.2.loop.exit:
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PS_jmpret $r31, implicit-def dead $pc
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bb.3.loop.body (machine-block-address-taken):
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successors: %bb.3(0x7c000000), %bb.2(0x04000000)
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%13:intregs = PHI %1, %bb.1, %14, %bb.3
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%15:intregs = PHI %0, %bb.1, %16, %bb.3
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%17:hvxvr, %14:intregs = V6_vL32b_pi %13, 128 :: (load (s1024) from %ir.lsr.iv1)
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%18:hvxvr = V6_vaddw %7, %17
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%19:hvxvr = V6_vaddw %5, %17
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%20:hvxvr = V6_vaddw %9, %17
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%21:hvxvr = V6_vaddw %18, killed %19
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%22:hvxvr = V6_vaddw %18, killed %20
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%23:hvxvr = V6_vaddw killed %22, killed %21
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%16:intregs = V6_vS32b_pi %15, 128, killed %23 :: (store (s1024) into %ir.lsr.iv)
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ENDLOOP0 %bb.3, implicit-def $pc, implicit-def $lc0, implicit $sa0, implicit $lc0
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J2_jump %bb.2, implicit-def dead $pc
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...

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