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[AArch64] Set predicates for FP/SIMD InstAliases (#79033)
These are aliases for instructions which are are only available when the fp-armv8 or neon features are enabled, so their predicates should be set appropriately.
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‎llvm/lib/Target/AArch64/AArch64InstrInfo.td

+23-1
Original file line numberDiff line numberDiff line change
@@ -3532,6 +3532,7 @@ def : InstAlias<"ldr $Rt, [$Rn, $offset]",
35323532
(LDURXi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb64:$offset), 0>;
35333533
def : InstAlias<"ldr $Rt, [$Rn, $offset]",
35343534
(LDURWi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>;
3535+
let Predicates = [HasFPARMv8] in {
35353536
def : InstAlias<"ldr $Rt, [$Rn, $offset]",
35363537
(LDURBi FPR8Op:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;
35373538
def : InstAlias<"ldr $Rt, [$Rn, $offset]",
@@ -3542,6 +3543,7 @@ def : InstAlias<"ldr $Rt, [$Rn, $offset]",
35423543
(LDURDi FPR64Op:$Rt, GPR64sp:$Rn, simm9_offset_fb64:$offset), 0>;
35433544
def : InstAlias<"ldr $Rt, [$Rn, $offset]",
35443545
(LDURQi FPR128Op:$Rt, GPR64sp:$Rn, simm9_offset_fb128:$offset), 0>;
3546+
}
35453547

35463548
// zextload -> i64
35473549
def : Pat<(i64 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))),
@@ -4175,6 +4177,7 @@ def : InstAlias<"str $Rt, [$Rn, $offset]",
41754177
(STURXi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb64:$offset), 0>;
41764178
def : InstAlias<"str $Rt, [$Rn, $offset]",
41774179
(STURWi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>;
4180+
let Predicates = [HasFPARMv8] in {
41784181
def : InstAlias<"str $Rt, [$Rn, $offset]",
41794182
(STURBi FPR8Op:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;
41804183
def : InstAlias<"str $Rt, [$Rn, $offset]",
@@ -4185,6 +4188,7 @@ def : InstAlias<"str $Rt, [$Rn, $offset]",
41854188
(STURDi FPR64Op:$Rt, GPR64sp:$Rn, simm9_offset_fb64:$offset), 0>;
41864189
def : InstAlias<"str $Rt, [$Rn, $offset]",
41874190
(STURQi FPR128Op:$Rt, GPR64sp:$Rn, simm9_offset_fb128:$offset), 0>;
4191+
}
41884192

41894193
def : InstAlias<"strb $Rt, [$Rn, $offset]",
41904194
(STURBBi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>;
@@ -4595,8 +4599,10 @@ def FMOVD0 : Pseudo<(outs FPR64:$Rd), (ins), [(set f64:$Rd, (fpimm0))]>,
45954599
// Similarly add aliases
45964600
def : InstAlias<"fmov $Rd, #0.0", (FMOVWHr FPR16:$Rd, WZR), 0>,
45974601
Requires<[HasFullFP16]>;
4602+
let Predicates = [HasFPARMv8] in {
45984603
def : InstAlias<"fmov $Rd, #0.0", (FMOVWSr FPR32:$Rd, WZR), 0>;
45994604
def : InstAlias<"fmov $Rd, #0.0", (FMOVXDr FPR64:$Rd, XZR), 0>;
4605+
}
46004606

46014607
def : Pat<(bf16 fpimm0),
46024608
(FMOVH0)>;
@@ -5040,10 +5046,12 @@ defm NEG : SIMDTwoVectorBHSD<1, 0b01011, "neg",
50405046
UnOpFrag<(sub immAllZerosV, node:$LHS)> >;
50415047
defm NOT : SIMDTwoVectorB<1, 0b00, 0b00101, "not", vnot>;
50425048
// Aliases for MVN -> NOT.
5049+
let Predicates = [HasNEON] in {
50435050
def : InstAlias<"mvn{ $Vd.8b, $Vn.8b|.8b $Vd, $Vn}",
50445051
(NOTv8i8 V64:$Vd, V64:$Vn)>;
50455052
def : InstAlias<"mvn{ $Vd.16b, $Vn.16b|.16b $Vd, $Vn}",
50465053
(NOTv16i8 V128:$Vd, V128:$Vn)>;
5054+
}
50475055

50485056
def : Pat<(vnot (v4i16 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
50495057
def : Pat<(vnot (v8i16 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
@@ -5318,6 +5326,7 @@ def : Pat<(AArch64bsp (v4i32 V128:$Rd), V128:$Rn, V128:$Rm),
53185326
def : Pat<(AArch64bsp (v2i64 V128:$Rd), V128:$Rn, V128:$Rm),
53195327
(BSPv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>;
53205328

5329+
let Predicates = [HasNEON] in {
53215330
def : InstAlias<"mov{\t$dst.16b, $src.16b|.16b\t$dst, $src}",
53225331
(ORRv16i8 V128:$dst, V128:$src, V128:$src), 1>;
53235332
def : InstAlias<"mov{\t$dst.8h, $src.8h|.8h\t$dst, $src}",
@@ -5495,6 +5504,7 @@ def : InstAlias<"{faclt\t$dst.4s, $src1.4s, $src2.4s" #
54955504
def : InstAlias<"{faclt\t$dst.2d, $src1.2d, $src2.2d" #
54965505
"|faclt.2d\t$dst, $src1, $src2}",
54975506
(FACGTv2f64 V128:$dst, V128:$src2, V128:$src1), 0>;
5507+
}
54985508

54995509
//===----------------------------------------------------------------------===//
55005510
// Advanced SIMD three scalar instructions.
@@ -5557,6 +5567,7 @@ defm : FMULScalarFromIndexedLane0Patterns<"FMULX", "16", "32", "64",
55575567
int_aarch64_neon_fmulx,
55585568
[HasNEONorSME]>;
55595569

5570+
let Predicates = [HasNEON] in {
55605571
def : InstAlias<"cmls $dst, $src1, $src2",
55615572
(CMHSv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
55625573
def : InstAlias<"cmle $dst, $src1, $src2",
@@ -5565,6 +5576,8 @@ def : InstAlias<"cmlo $dst, $src1, $src2",
55655576
(CMHIv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
55665577
def : InstAlias<"cmlt $dst, $src1, $src2",
55675578
(CMGTv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
5579+
}
5580+
let Predicates = [HasFPARMv8] in {
55685581
def : InstAlias<"fcmle $dst, $src1, $src2",
55695582
(FCMGE32 FPR32:$dst, FPR32:$src2, FPR32:$src1), 0>;
55705583
def : InstAlias<"fcmle $dst, $src1, $src2",
@@ -5581,6 +5594,7 @@ def : InstAlias<"faclt $dst, $src1, $src2",
55815594
(FACGT32 FPR32:$dst, FPR32:$src2, FPR32:$src1), 0>;
55825595
def : InstAlias<"faclt $dst, $src1, $src2",
55835596
(FACGT64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>;
5597+
}
55845598

55855599
//===----------------------------------------------------------------------===//
55865600
// Advanced SIMD three scalar instructions (mixed operands).
@@ -7027,6 +7041,7 @@ defm BIC : SIMDModifiedImmVectorShiftTied<1, 0b11, 0b01, "bic", AArch64bici>;
70277041
// AdvSIMD ORR
70287042
defm ORR : SIMDModifiedImmVectorShiftTied<0, 0b11, 0b01, "orr", AArch64orri>;
70297043

7044+
let Predicates = [HasNEON] in {
70307045
def : InstAlias<"bic $Vd.4h, $imm", (BICv4i16 V64:$Vd, imm0_255:$imm, 0)>;
70317046
def : InstAlias<"bic $Vd.8h, $imm", (BICv8i16 V128:$Vd, imm0_255:$imm, 0)>;
70327047
def : InstAlias<"bic $Vd.2s, $imm", (BICv2i32 V64:$Vd, imm0_255:$imm, 0)>;
@@ -7046,6 +7061,7 @@ def : InstAlias<"orr.4h $Vd, $imm", (ORRv4i16 V64:$Vd, imm0_255:$imm, 0)>;
70467061
def : InstAlias<"orr.8h $Vd, $imm", (ORRv8i16 V128:$Vd, imm0_255:$imm, 0)>;
70477062
def : InstAlias<"orr.2s $Vd, $imm", (ORRv2i32 V64:$Vd, imm0_255:$imm, 0)>;
70487063
def : InstAlias<"orr.4s $Vd, $imm", (ORRv4i32 V128:$Vd, imm0_255:$imm, 0)>;
7064+
}
70497065

70507066
// AdvSIMD FMOV
70517067
def FMOVv2f64_ns : SIMDModifiedImmVectorNoShift<1, 1, 0, 0b1111, V128, fpimm8,
@@ -7129,6 +7145,7 @@ let Predicates = [HasNEON] in {
71297145
ssub)>;
71307146
}
71317147

7148+
let Predicates = [HasNEON] in {
71327149
def : InstAlias<"movi $Vd.4h, $imm", (MOVIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
71337150
def : InstAlias<"movi $Vd.8h, $imm", (MOVIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
71347151
def : InstAlias<"movi $Vd.2s, $imm", (MOVIv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
@@ -7138,6 +7155,7 @@ def : InstAlias<"movi.4h $Vd, $imm", (MOVIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
71387155
def : InstAlias<"movi.8h $Vd, $imm", (MOVIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
71397156
def : InstAlias<"movi.2s $Vd, $imm", (MOVIv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
71407157
def : InstAlias<"movi.4s $Vd, $imm", (MOVIv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
7158+
}
71417159

71427160
def : Pat<(v2i32 (AArch64movi_shift imm0_255:$imm8, (i32 imm:$shift))),
71437161
(MOVIv2i32 imm0_255:$imm8, imm:$shift)>;
@@ -7173,6 +7191,7 @@ def MOVIv16b_ns : SIMDModifiedImmVectorNoShift<1, 0, 0, 0b1110, V128, imm0_255,
71737191
let isReMaterializable = 1, isAsCheapAsAMove = 1 in
71747192
defm MVNI : SIMDModifiedImmVectorShift<1, 0b10, 0b00, "mvni">;
71757193

7194+
let Predicates = [HasNEON] in {
71767195
def : InstAlias<"mvni $Vd.4h, $imm", (MVNIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
71777196
def : InstAlias<"mvni $Vd.8h, $imm", (MVNIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
71787197
def : InstAlias<"mvni $Vd.2s, $imm", (MVNIv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
@@ -7182,6 +7201,7 @@ def : InstAlias<"mvni.4h $Vd, $imm", (MVNIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
71827201
def : InstAlias<"mvni.8h $Vd, $imm", (MVNIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
71837202
def : InstAlias<"mvni.2s $Vd, $imm", (MVNIv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
71847203
def : InstAlias<"mvni.4s $Vd, $imm", (MVNIv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
7204+
}
71857205

71867206
def : Pat<(v2i32 (AArch64mvni_shift imm0_255:$imm8, (i32 imm:$shift))),
71877207
(MVNIv2i32 imm0_255:$imm8, imm:$shift)>;
@@ -7669,6 +7689,7 @@ def : Pat<(v2i64 (zext (v2i32 (extract_high_v4i32 (v4i32 V128:$Rn)) ))),
76697689
def : Pat<(v2i64 (sext (v2i32 (extract_high_v4i32 (v4i32 V128:$Rn)) ))),
76707690
(SSHLLv4i32_shift V128:$Rn, (i32 0))>;
76717691

7692+
let Predicates = [HasNEON] in {
76727693
// Vector shift sxtl aliases
76737694
def : InstAlias<"sxtl.8h $dst, $src1",
76747695
(SSHLLv8i8_shift V128:$dst, V64:$src1, 0)>;
@@ -7724,6 +7745,7 @@ def : InstAlias<"uxtl2.2d $dst, $src1",
77247745
(USHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
77257746
def : InstAlias<"uxtl2 $dst.2d, $src1.4s",
77267747
(USHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
7748+
}
77277749

77287750
// If an integer is about to be converted to a floating point value,
77297751
// just load it on the floating point unit.
@@ -8172,7 +8194,7 @@ def AESIMCrr : AESInst< 0b0111, "aesimc", int_aarch64_crypto_aesimc>;
81728194

81738195
// Pseudo instructions for AESMCrr/AESIMCrr with a register constraint required
81748196
// for AES fusion on some CPUs.
8175-
let hasSideEffects = 0, mayStore = 0, mayLoad = 0 in {
8197+
let hasSideEffects = 0, mayStore = 0, mayLoad = 0, Predicates = [HasAES] in {
81768198
def AESMCrrTied: Pseudo<(outs V128:$Rd), (ins V128:$Rn), [], "$Rn = $Rd">,
81778199
Sched<[WriteVq]>;
81788200
def AESIMCrrTied: Pseudo<(outs V128:$Rd), (ins V128:$Rn), [], "$Rn = $Rd">,

‎llvm/test/MC/AArch64/no-fp-errors.s

+170
Original file line numberDiff line numberDiff line change
@@ -191,3 +191,173 @@ label:
191191
// CHECK: [[@LINE-1]]:7: error: expected writable system register or pstate
192192
msr FPSR, x0
193193
// CHECK: [[@LINE-1]]:7: error: expected writable system register or pstate
194+
195+
ldr s0, [x0, #1]
196+
// CHECK: [[@LINE-1]]:3: error: instruction requires: fp-armv8
197+
str q0, [x0, #1]
198+
// CHECK: [[@LINE-1]]:3: error: instruction requires: fp-armv8
199+
200+
fmov s0, #0.0
201+
// CHECK: [[@LINE-1]]:3: error: instruction requires: fp-armv8
202+
fmov d0, #0.0
203+
// CHECK: [[@LINE-1]]:3: error: instruction requires: fp-armv8
204+
205+
mvn v0.8b, v1.8b
206+
// CHECK: [[@LINE-1]]:3: error: instruction requires: neon
207+
mvn v0.16b, v1.16b
208+
// CHECK: [[@LINE-1]]:3: error: instruction requires: neon
209+
210+
mov v0.16b, v1.16b
211+
// CHECK: [[@LINE-1]]:3: error: instruction requires: neon
212+
mov v0.8h, v1.8h
213+
// CHECK: [[@LINE-1]]:3: error: instruction requires: neon
214+
mov v0.4s, v1.4s
215+
// CHECK: [[@LINE-1]]:3: error: instruction requires: neon
216+
mov v0.2d, v1.2d
217+
// CHECK: [[@LINE-1]]:3: error: instruction requires: neon
218+
219+
mov v0.8b, v1.8b
220+
// CHECK: [[@LINE-1]]:3: error: instruction requires: neon
221+
mov v0.4h, v1.4h
222+
// CHECK: [[@LINE-1]]:3: error: instruction requires: neon
223+
mov v0.2s, v1.2s
224+
// CHECK: [[@LINE-1]]:3: error: instruction requires: neon
225+
mov v0.1d, v1.1d
226+
// CHECK: [[@LINE-1]]:3: error: instruction requires: neon
227+
228+
faclt v0.4h, v1.4h, v2.4h
229+
// CHECK: [[@LINE-1]]:3: error: instruction requires: fullfp16 neon
230+
faclt v0.8h, v1.8h, v2.8h
231+
// CHECK: [[@LINE-1]]:3: error: instruction requires: fullfp16 neon
232+
faclt v0.2s, v1.2s, v2.2s
233+
// CHECK: [[@LINE-1]]:3: error: instruction requires: neon
234+
faclt v0.4s, v1.4s, v2.4s
235+
// CHECK: [[@LINE-1]]:3: error: instruction requires: neon
236+
faclt v0.2d, v1.2d, v2.2d
237+
// CHECK: [[@LINE-1]]:3: error: instruction requires: neon
238+
239+
cmls d0, d1, d2
240+
// CHECK: [[@LINE-1]]:3: error: instruction requires: neon
241+
cmle d0, d1, d2
242+
// CHECK: [[@LINE-1]]:3: error: instruction requires: neon
243+
cmlo d0, d1, d2
244+
// CHECK: [[@LINE-1]]:3: error: instruction requires: neon
245+
cmlt d0, d1, d2
246+
// CHECK: [[@LINE-1]]:3: error: instruction requires: neon
247+
248+
fcmle s0, s1, s2
249+
// CHECK: [[@LINE-1]]:3: error: instruction requires: fp-armv8
250+
fcmle d0, d1, d2
251+
// CHECK: [[@LINE-1]]:3: error: instruction requires: fp-armv8
252+
fcmlt s0, s1, s2
253+
// CHECK: [[@LINE-1]]:3: error: instruction requires: fp-armv8
254+
fcmlt d0, d1, d2
255+
// CHECK: [[@LINE-1]]:3: error: instruction requires: fp-armv8
256+
facle s0, s1, s2
257+
// CHECK: [[@LINE-1]]:3: error: instruction requires: fp-armv8
258+
facle d0, d1, d2
259+
// CHECK: [[@LINE-1]]:3: error: instruction requires: fp-armv8
260+
faclt s0, s1, s2
261+
// CHECK: [[@LINE-1]]:3: error: instruction requires: fp-armv8
262+
faclt d0, d1, d2
263+
// CHECK: [[@LINE-1]]:3: error: instruction requires: fp-armv8
264+
265+
bic v0.4h, #42
266+
// CHECK: [[@LINE-1]]:3: error: instruction requires: neon
267+
bic v0.8h, #42
268+
// CHECK: [[@LINE-1]]:3: error: instruction requires: neon
269+
bic v0.2s, #42
270+
// CHECK: [[@LINE-1]]:3: error: instruction requires: neon
271+
bic v0.4s, #42
272+
// CHECK: [[@LINE-1]]:3: error: instruction requires: neon
273+
274+
bic.4h v0, #42
275+
// CHECK: [[@LINE-1]]:3: error: instruction requires: neon
276+
bic.8h v0, #42
277+
// CHECK: [[@LINE-1]]:3: error: instruction requires: neon
278+
bic.2s v0, #42
279+
// CHECK: [[@LINE-1]]:3: error: instruction requires: neon
280+
bic.4s v0, #42
281+
// CHECK: [[@LINE-1]]:3: error: instruction requires: neon
282+
283+
orr v0.4h, #42
284+
// CHECK: [[@LINE-1]]:3: error: instruction requires: neon
285+
orr v0.8h, #42
286+
// CHECK: [[@LINE-1]]:3: error: instruction requires: neon
287+
orr v0.2s, #42
288+
// CHECK: [[@LINE-1]]:3: error: instruction requires: neon
289+
orr v0.4s, #42
290+
// CHECK: [[@LINE-1]]:3: error: instruction requires: neon
291+
292+
orr.4h v0, #42
293+
// CHECK: [[@LINE-1]]:3: error: instruction requires: neon
294+
orr.8h v0, #42
295+
// CHECK: [[@LINE-1]]:3: error: instruction requires: neon
296+
orr.2s v0, #42
297+
// CHECK: [[@LINE-1]]:3: error: instruction requires: neon
298+
orr.4s v0, #42
299+
// CHECK: [[@LINE-1]]:3: error: instruction requires: neon
300+
301+
movi v0.4h, #42
302+
// CHECK: [[@LINE-1]]:3: error: instruction requires: neon
303+
movi v0.8h, #42
304+
// CHECK: [[@LINE-1]]:3: error: instruction requires: neon
305+
movi v0.2s, #42
306+
// CHECK: [[@LINE-1]]:3: error: instruction requires: neon
307+
movi v0.4s, #42
308+
// CHECK: [[@LINE-1]]:3: error: instruction requires: neon
309+
310+
movi.4h v0, #42
311+
// CHECK: [[@LINE-1]]:3: error: instruction requires: neon
312+
movi.8h v0, #42
313+
// CHECK: [[@LINE-1]]:3: error: instruction requires: neon
314+
movi.2s v0, #42
315+
// CHECK: [[@LINE-1]]:3: error: instruction requires: neon
316+
movi.4s v0, #42
317+
// CHECK: [[@LINE-1]]:3: error: instruction requires: neon
318+
319+
mvni v0.4h, #42
320+
// CHECK: [[@LINE-1]]:3: error: instruction requires: neon
321+
mvni v0.8h, #42
322+
// CHECK: [[@LINE-1]]:3: error: instruction requires: neon
323+
mvni v0.2s, #42
324+
// CHECK: [[@LINE-1]]:3: error: instruction requires: neon
325+
mvni v0.4s, #42
326+
// CHECK: [[@LINE-1]]:3: error: instruction requires: neon
327+
328+
mvni.4h v0, #42
329+
// CHECK: [[@LINE-1]]:3: error: instruction requires: neon
330+
mvni.8h v0, #42
331+
// CHECK: [[@LINE-1]]:3: error: instruction requires: neon
332+
mvni.2s v0, #42
333+
// CHECK: [[@LINE-1]]:3: error: instruction requires: neon
334+
mvni.4s v0, #42
335+
// CHECK: [[@LINE-1]]:3: error: instruction requires: neon
336+
337+
sxtl.8h v0, v1
338+
// CHECK: [[@LINE-1]]:3: error: instruction requires: neon
339+
sxtl.4s v0, v1
340+
// CHECK: [[@LINE-1]]:3: error: instruction requires: neon
341+
sxtl.2d v0, v1
342+
// CHECK: [[@LINE-1]]:3: error: instruction requires: neon
343+
344+
sxtl2.8h v0, v1
345+
// CHECK: [[@LINE-1]]:3: error: instruction requires: neon
346+
sxtl2.4s v0, v1
347+
// CHECK: [[@LINE-1]]:3: error: instruction requires: neon
348+
sxtl2.2d v0, v1
349+
// CHECK: [[@LINE-1]]:3: error: instruction requires: neon
350+
351+
uxtl.8h v0, v1
352+
// CHECK: [[@LINE-1]]:3: error: instruction requires: neon
353+
uxtl.4s v0, v1
354+
// CHECK: [[@LINE-1]]:3: error: instruction requires: neon
355+
uxtl.2d v0, v1
356+
// CHECK: [[@LINE-1]]:3: error: instruction requires: neon
357+
358+
uxtl2.8h v0, v1
359+
// CHECK: [[@LINE-1]]:3: error: instruction requires: neon
360+
uxtl2.4s v0, v1
361+
// CHECK: [[@LINE-1]]:3: error: instruction requires: neon
362+
uxtl2.2d v0, v1
363+
// CHECK: [[@LINE-1]]:3: error: instruction requires: neon

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