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[SelectionDAG] Use getVectorElementPointer in DAGCombiner::replaceStoreOfInsertLoad. (#74249)
This ensures we clip the index to be in bounds of the vector we are inserting into. If the index is out of bounds the results of the insert element is poison. If we don't clip the index we can write memory that was not part of the original store. Fixes #74248.
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‎llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp‎

Lines changed: 3 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -21006,20 +21006,18 @@ SDValue DAGCombiner::replaceStoreOfInsertLoad(StoreSDNode *ST) {
2100621006
&IsFast) ||
2100721007
!IsFast)
2100821008
return SDValue();
21009-
EVT PtrVT = Ptr.getValueType();
2101021009

21011-
SDValue Offset =
21012-
DAG.getNode(ISD::MUL, DL, PtrVT, DAG.getZExtOrTrunc(Idx, DL, PtrVT),
21013-
DAG.getConstant(EltVT.getSizeInBits() / 8, DL, PtrVT));
21014-
SDValue NewPtr = DAG.getNode(ISD::ADD, DL, PtrVT, Ptr, Offset);
2101521010
MachinePointerInfo PointerInfo(ST->getAddressSpace());
2101621011

2101721012
// If the offset is a known constant then try to recover the pointer
2101821013
// info
21014+
SDValue NewPtr;
2101921015
if (auto *CIdx = dyn_cast<ConstantSDNode>(Idx)) {
2102021016
unsigned COffset = CIdx->getSExtValue() * EltVT.getSizeInBits() / 8;
2102121017
NewPtr = DAG.getMemBasePlusOffset(Ptr, TypeSize::getFixed(COffset), DL);
2102221018
PointerInfo = ST->getPointerInfo().getWithOffset(COffset);
21019+
} else {
21020+
NewPtr = TLI.getVectorElementPointer(DAG, Ptr, Value.getValueType(), Idx);
2102321021
}
2102421022

2102521023
return DAG.getStore(Chain, DL, Elt, NewPtr, PointerInfo, ST->getAlign(),

‎llvm/test/CodeGen/Mips/msa/basic_operations.ll‎

Lines changed: 16 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1879,6 +1879,7 @@ define void @insert_v16i8_vidx(i32 signext %a) nounwind {
18791879
; O32-NEXT: addu $1, $2, $25
18801880
; O32-NEXT: lw $2, %got(i32)($1)
18811881
; O32-NEXT: lw $2, 0($2)
1882+
; O32-NEXT: andi $2, $2, 15
18821883
; O32-NEXT: lw $1, %got(v16i8)($1)
18831884
; O32-NEXT: addu $1, $1, $2
18841885
; O32-NEXT: jr $ra
@@ -1891,6 +1892,7 @@ define void @insert_v16i8_vidx(i32 signext %a) nounwind {
18911892
; N32-NEXT: addiu $1, $1, %lo(%neg(%gp_rel(insert_v16i8_vidx)))
18921893
; N32-NEXT: lw $2, %got_disp(i32)($1)
18931894
; N32-NEXT: lw $2, 0($2)
1895+
; N32-NEXT: andi $2, $2, 15
18941896
; N32-NEXT: lw $1, %got_disp(v16i8)($1)
18951897
; N32-NEXT: addu $1, $1, $2
18961898
; N32-NEXT: jr $ra
@@ -1902,7 +1904,8 @@ define void @insert_v16i8_vidx(i32 signext %a) nounwind {
19021904
; N64-NEXT: daddu $1, $1, $25
19031905
; N64-NEXT: daddiu $1, $1, %lo(%neg(%gp_rel(insert_v16i8_vidx)))
19041906
; N64-NEXT: ld $2, %got_disp(i32)($1)
1905-
; N64-NEXT: lwu $2, 0($2)
1907+
; N64-NEXT: lw $2, 0($2)
1908+
; N64-NEXT: andi $2, $2, 15
19061909
; N64-NEXT: ld $1, %got_disp(v16i8)($1)
19071910
; N64-NEXT: daddu $1, $1, $2
19081911
; N64-NEXT: jr $ra
@@ -1925,6 +1928,7 @@ define void @insert_v8i16_vidx(i32 signext %a) nounwind {
19251928
; O32-NEXT: addu $1, $2, $25
19261929
; O32-NEXT: lw $2, %got(i32)($1)
19271930
; O32-NEXT: lw $2, 0($2)
1931+
; O32-NEXT: andi $2, $2, 7
19281932
; O32-NEXT: lw $1, %got(v8i16)($1)
19291933
; O32-NEXT: lsa $1, $2, $1, 1
19301934
; O32-NEXT: jr $ra
@@ -1937,6 +1941,7 @@ define void @insert_v8i16_vidx(i32 signext %a) nounwind {
19371941
; N32-NEXT: addiu $1, $1, %lo(%neg(%gp_rel(insert_v8i16_vidx)))
19381942
; N32-NEXT: lw $2, %got_disp(i32)($1)
19391943
; N32-NEXT: lw $2, 0($2)
1944+
; N32-NEXT: andi $2, $2, 7
19401945
; N32-NEXT: lw $1, %got_disp(v8i16)($1)
19411946
; N32-NEXT: lsa $1, $2, $1, 1
19421947
; N32-NEXT: jr $ra
@@ -1948,7 +1953,8 @@ define void @insert_v8i16_vidx(i32 signext %a) nounwind {
19481953
; N64-NEXT: daddu $1, $1, $25
19491954
; N64-NEXT: daddiu $1, $1, %lo(%neg(%gp_rel(insert_v8i16_vidx)))
19501955
; N64-NEXT: ld $2, %got_disp(i32)($1)
1951-
; N64-NEXT: lwu $2, 0($2)
1956+
; N64-NEXT: lw $2, 0($2)
1957+
; N64-NEXT: andi $2, $2, 7
19521958
; N64-NEXT: ld $1, %got_disp(v8i16)($1)
19531959
; N64-NEXT: dlsa $1, $2, $1, 1
19541960
; N64-NEXT: jr $ra
@@ -1971,6 +1977,7 @@ define void @insert_v4i32_vidx(i32 signext %a) nounwind {
19711977
; O32-NEXT: addu $1, $2, $25
19721978
; O32-NEXT: lw $2, %got(i32)($1)
19731979
; O32-NEXT: lw $2, 0($2)
1980+
; O32-NEXT: andi $2, $2, 3
19741981
; O32-NEXT: lw $1, %got(v4i32)($1)
19751982
; O32-NEXT: lsa $1, $2, $1, 2
19761983
; O32-NEXT: jr $ra
@@ -1983,6 +1990,7 @@ define void @insert_v4i32_vidx(i32 signext %a) nounwind {
19831990
; N32-NEXT: addiu $1, $1, %lo(%neg(%gp_rel(insert_v4i32_vidx)))
19841991
; N32-NEXT: lw $2, %got_disp(i32)($1)
19851992
; N32-NEXT: lw $2, 0($2)
1993+
; N32-NEXT: andi $2, $2, 3
19861994
; N32-NEXT: lw $1, %got_disp(v4i32)($1)
19871995
; N32-NEXT: lsa $1, $2, $1, 2
19881996
; N32-NEXT: jr $ra
@@ -1994,7 +2002,8 @@ define void @insert_v4i32_vidx(i32 signext %a) nounwind {
19942002
; N64-NEXT: daddu $1, $1, $25
19952003
; N64-NEXT: daddiu $1, $1, %lo(%neg(%gp_rel(insert_v4i32_vidx)))
19962004
; N64-NEXT: ld $2, %got_disp(i32)($1)
1997-
; N64-NEXT: lwu $2, 0($2)
2005+
; N64-NEXT: lw $2, 0($2)
2006+
; N64-NEXT: andi $2, $2, 3
19982007
; N64-NEXT: ld $1, %got_disp(v4i32)($1)
19992008
; N64-NEXT: dlsa $1, $2, $1, 2
20002009
; N64-NEXT: jr $ra
@@ -2018,6 +2027,7 @@ define void @insert_v2i64_vidx(i64 signext %a) nounwind {
20182027
; O32-NEXT: addu $1, $2, $25
20192028
; O32-NEXT: lw $2, %got(i32)($1)
20202029
; O32-NEXT: lw $2, 0($2)
2030+
; O32-NEXT: andi $2, $2, 1
20212031
; O32-NEXT: lw $1, %got(v2i64)($1)
20222032
; O32-NEXT: lsa $1, $2, $1, 3
20232033
; O32-NEXT: sw $5, 4($1)
@@ -2031,6 +2041,7 @@ define void @insert_v2i64_vidx(i64 signext %a) nounwind {
20312041
; N32-NEXT: addiu $1, $1, %lo(%neg(%gp_rel(insert_v2i64_vidx)))
20322042
; N32-NEXT: lw $2, %got_disp(i32)($1)
20332043
; N32-NEXT: lw $2, 0($2)
2044+
; N32-NEXT: andi $2, $2, 1
20342045
; N32-NEXT: lw $1, %got_disp(v2i64)($1)
20352046
; N32-NEXT: lsa $1, $2, $1, 3
20362047
; N32-NEXT: jr $ra
@@ -2042,7 +2053,8 @@ define void @insert_v2i64_vidx(i64 signext %a) nounwind {
20422053
; N64-NEXT: daddu $1, $1, $25
20432054
; N64-NEXT: daddiu $1, $1, %lo(%neg(%gp_rel(insert_v2i64_vidx)))
20442055
; N64-NEXT: ld $2, %got_disp(i32)($1)
2045-
; N64-NEXT: lwu $2, 0($2)
2056+
; N64-NEXT: lw $2, 0($2)
2057+
; N64-NEXT: andi $2, $2, 1
20462058
; N64-NEXT: ld $1, %got_disp(v2i64)($1)
20472059
; N64-NEXT: dlsa $1, $2, $1, 3
20482060
; N64-NEXT: jr $ra

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert.ll‎

Lines changed: 20 additions & 32 deletions
Original file line numberDiff line numberDiff line change
@@ -321,20 +321,13 @@ define <32 x i16> @insertelt_v32i16(<32 x i16> %a, i16 %y, i32 %idx) {
321321
}
322322

323323
define void @insertelt_v32i16_store(ptr %x, i16 %y, i32 %idx) {
324-
; RV32-LABEL: insertelt_v32i16_store:
325-
; RV32: # %bb.0:
326-
; RV32-NEXT: slli a2, a2, 1
327-
; RV32-NEXT: add a0, a0, a2
328-
; RV32-NEXT: sh a1, 0(a0)
329-
; RV32-NEXT: ret
330-
;
331-
; RV64-LABEL: insertelt_v32i16_store:
332-
; RV64: # %bb.0:
333-
; RV64-NEXT: slli a2, a2, 32
334-
; RV64-NEXT: srli a2, a2, 31
335-
; RV64-NEXT: add a0, a0, a2
336-
; RV64-NEXT: sh a1, 0(a0)
337-
; RV64-NEXT: ret
324+
; CHECK-LABEL: insertelt_v32i16_store:
325+
; CHECK: # %bb.0:
326+
; CHECK-NEXT: andi a2, a2, 31
327+
; CHECK-NEXT: slli a2, a2, 1
328+
; CHECK-NEXT: add a0, a0, a2
329+
; CHECK-NEXT: sh a1, 0(a0)
330+
; CHECK-NEXT: ret
338331
%a = load <32 x i16>, ptr %x
339332
%b = insertelement <32 x i16> %a, i16 %y, i32 %idx
340333
store <32 x i16> %b, ptr %x
@@ -366,20 +359,13 @@ define <8 x float> @insertelt_v8f32(<8 x float> %a, float %y, i32 %idx) {
366359
}
367360

368361
define void @insertelt_v8f32_store(ptr %x, float %y, i32 %idx) {
369-
; RV32-LABEL: insertelt_v8f32_store:
370-
; RV32: # %bb.0:
371-
; RV32-NEXT: slli a1, a1, 2
372-
; RV32-NEXT: add a0, a0, a1
373-
; RV32-NEXT: fsw fa0, 0(a0)
374-
; RV32-NEXT: ret
375-
;
376-
; RV64-LABEL: insertelt_v8f32_store:
377-
; RV64: # %bb.0:
378-
; RV64-NEXT: slli a1, a1, 32
379-
; RV64-NEXT: srli a1, a1, 30
380-
; RV64-NEXT: add a0, a0, a1
381-
; RV64-NEXT: fsw fa0, 0(a0)
382-
; RV64-NEXT: ret
362+
; CHECK-LABEL: insertelt_v8f32_store:
363+
; CHECK: # %bb.0:
364+
; CHECK-NEXT: andi a1, a1, 7
365+
; CHECK-NEXT: slli a1, a1, 2
366+
; CHECK-NEXT: add a0, a0, a1
367+
; CHECK-NEXT: fsw fa0, 0(a0)
368+
; CHECK-NEXT: ret
383369
%a = load <8 x float>, ptr %x
384370
%b = insertelement <8 x float> %a, float %y, i32 %idx
385371
store <8 x float> %b, ptr %x
@@ -443,6 +429,7 @@ define <8 x i64> @insertelt_v8i64(<8 x i64> %a, i32 %idx) {
443429
define void @insertelt_v8i64_store(ptr %x, i32 %idx) {
444430
; RV32-LABEL: insertelt_v8i64_store:
445431
; RV32: # %bb.0:
432+
; RV32-NEXT: andi a1, a1, 7
446433
; RV32-NEXT: slli a1, a1, 3
447434
; RV32-NEXT: add a0, a0, a1
448435
; RV32-NEXT: li a1, -1
@@ -452,8 +439,8 @@ define void @insertelt_v8i64_store(ptr %x, i32 %idx) {
452439
;
453440
; RV64-LABEL: insertelt_v8i64_store:
454441
; RV64: # %bb.0:
455-
; RV64-NEXT: slli a1, a1, 32
456-
; RV64-NEXT: srli a1, a1, 29
442+
; RV64-NEXT: andi a1, a1, 7
443+
; RV64-NEXT: slli a1, a1, 3
457444
; RV64-NEXT: add a0, a0, a1
458445
; RV64-NEXT: li a1, -1
459446
; RV64-NEXT: sd a1, 0(a0)
@@ -521,6 +508,7 @@ define <8 x i64> @insertelt_c6_v8i64(<8 x i64> %a, i32 %idx) {
521508
define void @insertelt_c6_v8i64_store(ptr %x, i32 %idx) {
522509
; RV32-LABEL: insertelt_c6_v8i64_store:
523510
; RV32: # %bb.0:
511+
; RV32-NEXT: andi a1, a1, 7
524512
; RV32-NEXT: slli a1, a1, 3
525513
; RV32-NEXT: add a0, a0, a1
526514
; RV32-NEXT: sw zero, 4(a0)
@@ -530,8 +518,8 @@ define void @insertelt_c6_v8i64_store(ptr %x, i32 %idx) {
530518
;
531519
; RV64-LABEL: insertelt_c6_v8i64_store:
532520
; RV64: # %bb.0:
533-
; RV64-NEXT: slli a1, a1, 32
534-
; RV64-NEXT: srli a1, a1, 29
521+
; RV64-NEXT: andi a1, a1, 7
522+
; RV64-NEXT: slli a1, a1, 3
535523
; RV64-NEXT: add a0, a0, a1
536524
; RV64-NEXT: li a1, 6
537525
; RV64-NEXT: sd a1, 0(a0)

‎llvm/test/CodeGen/X86/pr59980.ll‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -9,6 +9,7 @@ define void @foo(ptr %0, ptr %1, ptr %2) #0 {
99
; CHECK: ## %bb.0:
1010
; CHECK-NEXT: movl (%rdx), %eax
1111
; CHECK-NEXT: vpinsrw $0, (%rdi), %xmm0, %xmm0
12+
; CHECK-NEXT: andl $15, %eax
1213
; CHECK-NEXT: vpextrw $0, %xmm0, (%rsi,%rax,2)
1314
; CHECK-NEXT: retq
1415
%4 = bitcast ptr %2 to ptr

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