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[RISCV][MC] Introduce MC support for XSfvfexp* and XSfvfbfexpa*
Co-Authored-By: Craig Topper <craig.topper@sifive.com>
1 parent c3d905e commit 5c89164

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10 files changed

+119
-3
lines changed

10 files changed

+119
-3
lines changed

‎llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -2406,7 +2406,8 @@ ParseStatus RISCVAsmParser::parseVTypeI(OperandVector &Operands) {
24062406
}
24072407

24082408
bool RISCVAsmParser::generateVTypeError(SMLoc ErrorLoc) {
2409-
if (STI->hasFeature(RISCV::FeatureStdExtZvfbfa))
2409+
if (STI->hasFeature(RISCV::FeatureStdExtZvfbfa) ||
2410+
STI->hasFeature(RISCV::FeatureVendorXSfvfbfexp16e))
24102411
return Error(
24112412
ErrorLoc,
24122413
"operand must be "

‎llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp‎

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -654,7 +654,10 @@ static constexpr FeatureBitset XqciFeatureGroup = {
654654
static constexpr FeatureBitset XSfVectorGroup = {
655655
RISCV::FeatureVendorXSfvcp, RISCV::FeatureVendorXSfvqmaccdod,
656656
RISCV::FeatureVendorXSfvqmaccqoq, RISCV::FeatureVendorXSfvfwmaccqqq,
657-
RISCV::FeatureVendorXSfvfnrclipxfqf, RISCV::FeatureVendorXSfmmbase};
657+
RISCV::FeatureVendorXSfvfnrclipxfqf, RISCV::FeatureVendorXSfmmbase,
658+
RISCV::FeatureVendorXSfvfexpa, RISCV::FeatureVendorXSfvfexpa64e,
659+
RISCV::FeatureVendorXSfvfbfexp16e, RISCV::FeatureVendorXSfvfexp16e,
660+
RISCV::FeatureVendorXSfvfexp32e};
658661
static constexpr FeatureBitset XSfSystemGroup = {
659662
RISCV::FeatureVendorXSiFivecdiscarddlone,
660663
RISCV::FeatureVendorXSiFivecflushdlone,

‎llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -220,7 +220,8 @@ void RISCVInstPrinter::printVTypeI(const MCInst *MI, unsigned OpNo,
220220
if (RISCVVType::getVLMUL(Imm) == RISCVVType::VLMUL::LMUL_RESERVED ||
221221
RISCVVType::getSEW(Imm) > 64 ||
222222
(RISCVVType::isAltFmt(Imm) &&
223-
!STI.hasFeature(RISCV::FeatureStdExtZvfbfa)) ||
223+
!(STI.hasFeature(RISCV::FeatureStdExtZvfbfa) ||
224+
STI.hasFeature(RISCV::FeatureVendorXSfvfbfexp16e))) ||
224225
(Imm >> 9) != 0) {
225226
O << formatImm(Imm);
226227
return;

‎llvm/lib/Target/RISCV/RISCVFeatures.td‎

Lines changed: 38 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1334,6 +1334,44 @@ def HasVendorXSfvfnrclipxfqf
13341334
AssemblerPredicate<(all_of FeatureVendorXSfvfnrclipxfqf),
13351335
"'XSfvfnrclipxfqf' (SiFive FP32-to-int8 Ranged Clip Instructions)">;
13361336

1337+
// Note: XSfvfbfexp16e depends on either Zvfbfmin _or_ Zvfbfa, which cannot be expressed here in
1338+
// TableGen. Instead, we check that in RISCVISAInfo.
1339+
def FeatureVendorXSfvfbfexp16e
1340+
: RISCVExtension<0, 5,
1341+
"SiFive Vector Floating-Point Exponential Function Instruction, BFloat16">;
1342+
def HasVendorXSfvfbfexp16e : Predicate<"Subtarget->hasVendorXSfvfbfexp16e()">;
1343+
1344+
def FeatureVendorXSfvfexp16e
1345+
: RISCVExtension<0, 5,
1346+
"SiFive Vector Floating-Point Exponential Function Instruction, Half Precision",
1347+
[FeatureStdExtZvfh]>;
1348+
def HasVendorXSfvfexp16e : Predicate<"Subtarget->hasVendorXSfvfexp16e()">;
1349+
1350+
def FeatureVendorXSfvfexp32e
1351+
: RISCVExtension<0, 5,
1352+
"SiFive Vector Floating-Point Exponential Function Instruction, Single Precision",
1353+
[FeatureStdExtZve32f]>;
1354+
def HasVendorXSfvfexp32e : Predicate<"Subtarget->hasVendorXSfvfexp32e()">;
1355+
1356+
def HasVendorXSfvfexpAnyFloat : Predicate<"Subtarget->hasVendorXSfvfexp16e() || Subtarget->hasVendorXSfvfexp32e()">;
1357+
def HasVendorXSfvfexpAny : Predicate<"Subtarget->hasVendorXSfvfbfexp16e() || Subtarget->hasVendorXSfvfexp16e() || Subtarget->hasVendorXSfvfexp32e()">,
1358+
AssemblerPredicate<(any_of FeatureVendorXSfvfbfexp16e, FeatureVendorXSfvfexp16e, FeatureVendorXSfvfexp32e),
1359+
"'Xsfvfbfexp16e/Xsfvfexp16e/Xsfvfexp32e' (SiFive Vector Floating-Point Exponential Function Instruction)">;
1360+
1361+
def FeatureVendorXSfvfexpa
1362+
: RISCVExtension<0, 2,
1363+
"SiFive Vector Floating-Point Exponential Approximation Instruction",
1364+
[FeatureStdExtZve32f]>;
1365+
def HasVendorXSfvfexpa : Predicate<"Subtarget->hasVendorXSfvfexpa()">,
1366+
AssemblerPredicate<(all_of FeatureVendorXSfvfexpa),
1367+
"'Xsfvfexpa' (SiFive Vector Floating-Point Exponential Approximation Instruction)">;
1368+
1369+
def FeatureVendorXSfvfexpa64e
1370+
: RISCVExtension<0, 2,
1371+
"SiFive Vector Floating-Point Exponential Approximation Instruction with Double-Precision",
1372+
[FeatureVendorXSfvfexpa, FeatureStdExtZve64d]>;
1373+
def HasVendorXSfvfexpa64e : Predicate<"Subtarget->hasVendorXSfvfexpa64e()">;
1374+
13371375
def FeatureVendorXSiFivecdiscarddlone
13381376
: RISCVExtension<1, 0,
13391377
"SiFive sf.cdiscard.d.l1 Instruction", []>;

‎llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td‎

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -217,6 +217,14 @@ let Predicates = [HasVendorXSfvcp], mayLoad = 0, mayStore = 0,
217217
defm FVW : CustomSiFiveVCIX<"fvw", VCIX_XVW, VR, VR, FPR32>, Sched<[]>;
218218
}
219219

220+
let Predicates = [HasVendorXSfvfexpAny], DecoderNamespace = "XSfvector" in {
221+
def SF_VFEXP_V : VALUVs2<0b010011, 0b00111, OPFVV, "sf.vfexp.v">;
222+
}
223+
224+
let Predicates = [HasVendorXSfvfexpa], DecoderNamespace = "XSfvector" in {
225+
def SF_VFEXPA_V : VALUVs2<0b010011, 0b00110, OPFVV, "sf.vfexpa.v">;
226+
}
227+
220228
let Predicates = [HasVendorXSfvqmaccdod], DecoderNamespace = "XSfvector",
221229
DestEEW = EEWSEWx4, RVVConstraint=VS2Constraint in {
222230
def SF_VQMACCU_2x8x2 : CustomSiFiveVMACC<0b101100, OPMVV, "sf.vqmaccu.2x8x2">;

‎llvm/lib/TargetParser/RISCVISAInfo.cpp‎

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -765,6 +765,12 @@ Error RISCVISAInfo::checkDependency() {
765765
if (HasZvl && !HasVector)
766766
return getExtensionRequiresError("zvl*b", "v' or 'zve*");
767767

768+
if (Exts.count("xsfvfbfexp16e") &&
769+
!(Exts.count("zvfbfmin") || Exts.count("zvfbfa")))
770+
return createStringError(errc::invalid_argument,
771+
"'xsfvfbfexp16e' requires 'zvfbfmin' or "
772+
"'zvfbfa' extension to also be specified");
773+
768774
if (HasD && (HasC || Exts.count("zcd")))
769775
for (auto Ext : ZcdOverlaps)
770776
if (Exts.count(Ext.str()))

‎llvm/test/CodeGen/RISCV/features-info.ll‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -217,6 +217,11 @@
217217
; CHECK-NEXT: xsfmm64t - 'XSfmm64t' (TE=64 configuration).
218218
; CHECK-NEXT: xsfmmbase - 'XSfmmbase' (All non arithmetic instructions for all TEWs and sf.vtzero).
219219
; CHECK-NEXT: xsfvcp - 'XSfvcp' (SiFive Custom Vector Coprocessor Interface Instructions).
220+
; CHECK-NEXT: xsfvfbfexp16e - 'XSfvfbfexp16e' (SiFive Vector Floating-Point Exponential Function Instruction, BFloat16).
221+
; CHECK-NEXT: xsfvfexp16e - 'XSfvfexp16e' (SiFive Vector Floating-Point Exponential Function Instruction, Half Precision).
222+
; CHECK-NEXT: xsfvfexp32e - 'XSfvfexp32e' (SiFive Vector Floating-Point Exponential Function Instruction, Single Precision).
223+
; CHECK-NEXT: xsfvfexpa - 'XSfvfexpa' (SiFive Vector Floating-Point Exponential Approximation Instruction).
224+
; CHECK-NEXT: xsfvfexpa64e - 'XSfvfexpa64e' (SiFive Vector Floating-Point Exponential Approximation Instruction with Double-Precision).
220225
; CHECK-NEXT: xsfvfnrclipxfqf - 'XSfvfnrclipxfqf' (SiFive FP32-to-int8 Ranged Clip Instructions).
221226
; CHECK-NEXT: xsfvfwmaccqqq - 'XSfvfwmaccqqq' (SiFive Matrix Multiply Accumulate Instruction (4-by-4)).
222227
; CHECK-NEXT: xsfvqmaccdod - 'XSfvqmaccdod' (SiFive Int8 Matrix Multiplication Instructions (2-by-8 and 8-by-2)).

‎llvm/test/MC/RISCV/xsfvfexp.s‎

Lines changed: 29 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,29 @@
1+
# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+xsfvfexp32e %s \
2+
# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
3+
# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
4+
# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
5+
# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xsfvfexp32e %s \
6+
# RUN: | llvm-objdump -d --mattr=+xsfvfexp32e - \
7+
# RUN: | FileCheck %s --check-prefix=CHECK-INST
8+
# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xsfvfexp32e %s \
9+
# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
10+
# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+xsfvfexp16e %s \
11+
# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
12+
# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xsfvfexp16e %s \
13+
# RUN: | llvm-objdump -d --mattr=+xsfvfexp16e - \
14+
# RUN: | FileCheck %s --check-prefix=CHECK-INST
15+
# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xsfvfexp16e %s \
16+
# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
17+
# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+zvfbfmin,+xsfvfbfexp16e %s \
18+
# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
19+
# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+zvfbfmin,+xsfvfbfexp16e %s \
20+
# RUN: | llvm-objdump -d --mattr=+xsfvfbfexp16e - \
21+
# RUN: | FileCheck %s --check-prefix=CHECK-INST
22+
# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+zvfbfmin,+xsfvfbfexp16e %s \
23+
# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
24+
25+
sf.vfexp.v v2, v5, v0.t
26+
# CHECK-INST: sf.vfexp.v v2, v5, v0.t
27+
# CHECK-ENCODING: [0x57,0x91,0x53,0x4c]
28+
# CHECK-ERROR: instruction requires the following: 'Xsfvfbfexp16e/Xsfvfexp16e/Xsfvfexp32e' (SiFive Vector Floating-Point Exponential Function Instruction){{$}}
29+
# CHECK-UNKNOWN: 4c539157 <unknown>

‎llvm/test/MC/RISCV/xsfvfexpa.s‎

Lines changed: 15 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,15 @@
1+
# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+xsfvfexpa %s \
2+
# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
3+
# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
4+
# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
5+
# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xsfvfexpa %s \
6+
# RUN: | llvm-objdump -d --mattr=+xsfvfexpa - \
7+
# RUN: | FileCheck %s --check-prefix=CHECK-INST
8+
# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+xsfvfexpa %s \
9+
# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
10+
11+
sf.vfexpa.v v2, v5, v0.t
12+
# CHECK-INST: sf.vfexpa.v v2, v5, v0.t
13+
# CHECK-ENCODING: [0x57,0x11,0x53,0x4c]
14+
# CHECK-ERROR: instruction requires the following: 'Xsfvfexpa' (SiFive Vector Floating-Point Exponential Approximation Instruction){{$}}
15+
# CHECK-UNKNOWN: 4c531157 <unknown>

‎llvm/unittests/TargetParser/RISCVISAInfoTest.cpp‎

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -730,6 +730,11 @@ TEST(ParseArchString, MissingDepency) {
730730
EXPECT_EQ(toString(RISCVISAInfo::parseArchString(Input, true).takeError()),
731731
"");
732732
}
733+
734+
EXPECT_EQ(toString(RISCVISAInfo::parseArchString("rv64i_xsfvfbfexp16e", true)
735+
.takeError()),
736+
"'xsfvfbfexp16e' requires 'zvfbfmin' or 'zvfbfa' extension to also "
737+
"be specified");
733738
}
734739

735740
TEST(ParseArchString, RejectsUnrecognizedProfileNames) {
@@ -1162,6 +1167,11 @@ R"(All available -march extensions for RISC-V
11621167
xsfmm64t 0.6
11631168
xsfmmbase 0.6
11641169
xsfvcp 1.0
1170+
xsfvfbfexp16e 0.5
1171+
xsfvfexp16e 0.5
1172+
xsfvfexp32e 0.5
1173+
xsfvfexpa 0.2
1174+
xsfvfexpa64e 0.2
11651175
xsfvfnrclipxfqf 1.0
11661176
xsfvfwmaccqqq 1.0
11671177
xsfvqmaccdod 1.0

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