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[AArch64][GlobalISel] Expand converage of FMA.
This moves the legalization of G_FMA to the action builder that can handle more types. The existing arm64-vfloatintrinsics.ll has been removed as they are covered in other test files.
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-1008
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5 files changed

+250
-1008
lines changed

‎llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -229,10 +229,10 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
229229
.clampScalar(1, s32, s64)
230230
.widenScalarToNextPow2(0);
231231

232-
getActionDefinitionsBuilder({G_FADD, G_FSUB, G_FMUL, G_FDIV, G_FNEG, G_FABS,
233-
G_FSQRT, G_FMAXNUM, G_FMINNUM, G_FMAXIMUM,
234-
G_FMINIMUM, G_FCEIL, G_FFLOOR, G_FRINT,
235-
G_FNEARBYINT, G_INTRINSIC_TRUNC,
232+
getActionDefinitionsBuilder({G_FADD, G_FSUB, G_FMUL, G_FDIV, G_FMA, G_FNEG,
233+
G_FABS, G_FSQRT, G_FMAXNUM, G_FMINNUM,
234+
G_FMAXIMUM, G_FMINIMUM, G_FCEIL, G_FFLOOR,
235+
G_FRINT, G_FNEARBYINT, G_INTRINSIC_TRUNC,
236236
G_INTRINSIC_ROUND, G_INTRINSIC_ROUNDEVEN})
237237
.legalFor({MinFPScalar, s32, s64, v2s32, v4s32, v2s64})
238238
.legalIf([=](const LegalityQuery &Query) {
@@ -251,7 +251,7 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
251251
.minScalar(0, s32)
252252
.scalarize(0);
253253

254-
getActionDefinitionsBuilder({G_FMA, G_INTRINSIC_LRINT})
254+
getActionDefinitionsBuilder(G_INTRINSIC_LRINT)
255255
// If we don't have full FP16 support, then scalarize the elements of
256256
// vectors containing fp16 types.
257257
.fewerElementsIf(

‎llvm/test/CodeGen/AArch64/GlobalISel/legalize-fma.mir‎

Lines changed: 92 additions & 126 deletions
Original file line numberDiff line numberDiff line change
@@ -13,43 +13,27 @@ body: |
1313
1414
; NO-FP16-LABEL: name: test_v4f16.fma
1515
; NO-FP16: liveins: $d0, $d1, $d2
16-
; NO-FP16: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
17-
; NO-FP16: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $d1
18-
; NO-FP16: [[COPY2:%[0-9]+]]:_(<4 x s16>) = COPY $d2
19-
; NO-FP16: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16), [[UV3:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY]](<4 x s16>)
20-
; NO-FP16: [[UV4:%[0-9]+]]:_(s16), [[UV5:%[0-9]+]]:_(s16), [[UV6:%[0-9]+]]:_(s16), [[UV7:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY1]](<4 x s16>)
21-
; NO-FP16: [[UV8:%[0-9]+]]:_(s16), [[UV9:%[0-9]+]]:_(s16), [[UV10:%[0-9]+]]:_(s16), [[UV11:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY2]](<4 x s16>)
22-
; NO-FP16: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[UV]](s16)
23-
; NO-FP16: [[FPEXT1:%[0-9]+]]:_(s32) = G_FPEXT [[UV4]](s16)
24-
; NO-FP16: [[FPEXT2:%[0-9]+]]:_(s32) = G_FPEXT [[UV8]](s16)
25-
; NO-FP16: [[FMA:%[0-9]+]]:_(s32) = G_FMA [[FPEXT]], [[FPEXT1]], [[FPEXT2]]
26-
; NO-FP16: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[FMA]](s32)
27-
; NO-FP16: [[FPEXT3:%[0-9]+]]:_(s32) = G_FPEXT [[UV1]](s16)
28-
; NO-FP16: [[FPEXT4:%[0-9]+]]:_(s32) = G_FPEXT [[UV5]](s16)
29-
; NO-FP16: [[FPEXT5:%[0-9]+]]:_(s32) = G_FPEXT [[UV9]](s16)
30-
; NO-FP16: [[FMA1:%[0-9]+]]:_(s32) = G_FMA [[FPEXT3]], [[FPEXT4]], [[FPEXT5]]
31-
; NO-FP16: [[FPTRUNC1:%[0-9]+]]:_(s16) = G_FPTRUNC [[FMA1]](s32)
32-
; NO-FP16: [[FPEXT6:%[0-9]+]]:_(s32) = G_FPEXT [[UV2]](s16)
33-
; NO-FP16: [[FPEXT7:%[0-9]+]]:_(s32) = G_FPEXT [[UV6]](s16)
34-
; NO-FP16: [[FPEXT8:%[0-9]+]]:_(s32) = G_FPEXT [[UV10]](s16)
35-
; NO-FP16: [[FMA2:%[0-9]+]]:_(s32) = G_FMA [[FPEXT6]], [[FPEXT7]], [[FPEXT8]]
36-
; NO-FP16: [[FPTRUNC2:%[0-9]+]]:_(s16) = G_FPTRUNC [[FMA2]](s32)
37-
; NO-FP16: [[FPEXT9:%[0-9]+]]:_(s32) = G_FPEXT [[UV3]](s16)
38-
; NO-FP16: [[FPEXT10:%[0-9]+]]:_(s32) = G_FPEXT [[UV7]](s16)
39-
; NO-FP16: [[FPEXT11:%[0-9]+]]:_(s32) = G_FPEXT [[UV11]](s16)
40-
; NO-FP16: [[FMA3:%[0-9]+]]:_(s32) = G_FMA [[FPEXT9]], [[FPEXT10]], [[FPEXT11]]
41-
; NO-FP16: [[FPTRUNC3:%[0-9]+]]:_(s16) = G_FPTRUNC [[FMA3]](s32)
42-
; NO-FP16: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s16>) = G_BUILD_VECTOR [[FPTRUNC]](s16), [[FPTRUNC1]](s16), [[FPTRUNC2]](s16), [[FPTRUNC3]](s16)
43-
; NO-FP16: $d0 = COPY [[BUILD_VECTOR]](<4 x s16>)
44-
; NO-FP16: RET_ReallyLR implicit $d0
16+
; NO-FP16-NEXT: {{ $}}
17+
; NO-FP16-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
18+
; NO-FP16-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $d1
19+
; NO-FP16-NEXT: [[COPY2:%[0-9]+]]:_(<4 x s16>) = COPY $d2
20+
; NO-FP16-NEXT: [[FPEXT:%[0-9]+]]:_(<4 x s32>) = G_FPEXT [[COPY]](<4 x s16>)
21+
; NO-FP16-NEXT: [[FPEXT1:%[0-9]+]]:_(<4 x s32>) = G_FPEXT [[COPY1]](<4 x s16>)
22+
; NO-FP16-NEXT: [[FPEXT2:%[0-9]+]]:_(<4 x s32>) = G_FPEXT [[COPY2]](<4 x s16>)
23+
; NO-FP16-NEXT: [[FMA:%[0-9]+]]:_(<4 x s32>) = G_FMA [[FPEXT]], [[FPEXT1]], [[FPEXT2]]
24+
; NO-FP16-NEXT: [[FPTRUNC:%[0-9]+]]:_(<4 x s16>) = G_FPTRUNC [[FMA]](<4 x s32>)
25+
; NO-FP16-NEXT: $d0 = COPY [[FPTRUNC]](<4 x s16>)
26+
; NO-FP16-NEXT: RET_ReallyLR implicit $d0
27+
;
4528
; FP16-LABEL: name: test_v4f16.fma
4629
; FP16: liveins: $d0, $d1, $d2
47-
; FP16: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
48-
; FP16: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $d1
49-
; FP16: [[COPY2:%[0-9]+]]:_(<4 x s16>) = COPY $d2
50-
; FP16: [[FMA:%[0-9]+]]:_(<4 x s16>) = G_FMA [[COPY]], [[COPY1]], [[COPY2]]
51-
; FP16: $d0 = COPY [[FMA]](<4 x s16>)
52-
; FP16: RET_ReallyLR implicit $d0
30+
; FP16-NEXT: {{ $}}
31+
; FP16-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
32+
; FP16-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $d1
33+
; FP16-NEXT: [[COPY2:%[0-9]+]]:_(<4 x s16>) = COPY $d2
34+
; FP16-NEXT: [[FMA:%[0-9]+]]:_(<4 x s16>) = G_FMA [[COPY]], [[COPY1]], [[COPY2]]
35+
; FP16-NEXT: $d0 = COPY [[FMA]](<4 x s16>)
36+
; FP16-NEXT: RET_ReallyLR implicit $d0
5337
%0:_(<4 x s16>) = COPY $d0
5438
%1:_(<4 x s16>) = COPY $d1
5539
%2:_(<4 x s16>) = COPY $d2
@@ -69,63 +53,36 @@ body: |
6953
7054
; NO-FP16-LABEL: name: test_v8f16.fma
7155
; NO-FP16: liveins: $q0, $q1, $q2
72-
; NO-FP16: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0
73-
; NO-FP16: [[COPY1:%[0-9]+]]:_(<8 x s16>) = COPY $q1
74-
; NO-FP16: [[COPY2:%[0-9]+]]:_(<8 x s16>) = COPY $q2
75-
; NO-FP16: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16), [[UV3:%[0-9]+]]:_(s16), [[UV4:%[0-9]+]]:_(s16), [[UV5:%[0-9]+]]:_(s16), [[UV6:%[0-9]+]]:_(s16), [[UV7:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY]](<8 x s16>)
76-
; NO-FP16: [[UV8:%[0-9]+]]:_(s16), [[UV9:%[0-9]+]]:_(s16), [[UV10:%[0-9]+]]:_(s16), [[UV11:%[0-9]+]]:_(s16), [[UV12:%[0-9]+]]:_(s16), [[UV13:%[0-9]+]]:_(s16), [[UV14:%[0-9]+]]:_(s16), [[UV15:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY1]](<8 x s16>)
77-
; NO-FP16: [[UV16:%[0-9]+]]:_(s16), [[UV17:%[0-9]+]]:_(s16), [[UV18:%[0-9]+]]:_(s16), [[UV19:%[0-9]+]]:_(s16), [[UV20:%[0-9]+]]:_(s16), [[UV21:%[0-9]+]]:_(s16), [[UV22:%[0-9]+]]:_(s16), [[UV23:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY2]](<8 x s16>)
78-
; NO-FP16: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[UV]](s16)
79-
; NO-FP16: [[FPEXT1:%[0-9]+]]:_(s32) = G_FPEXT [[UV8]](s16)
80-
; NO-FP16: [[FPEXT2:%[0-9]+]]:_(s32) = G_FPEXT [[UV16]](s16)
81-
; NO-FP16: [[FMA:%[0-9]+]]:_(s32) = G_FMA [[FPEXT]], [[FPEXT1]], [[FPEXT2]]
82-
; NO-FP16: [[FPTRUNC:%[0-9]+]]:_(s16) = G_FPTRUNC [[FMA]](s32)
83-
; NO-FP16: [[FPEXT3:%[0-9]+]]:_(s32) = G_FPEXT [[UV1]](s16)
84-
; NO-FP16: [[FPEXT4:%[0-9]+]]:_(s32) = G_FPEXT [[UV9]](s16)
85-
; NO-FP16: [[FPEXT5:%[0-9]+]]:_(s32) = G_FPEXT [[UV17]](s16)
86-
; NO-FP16: [[FMA1:%[0-9]+]]:_(s32) = G_FMA [[FPEXT3]], [[FPEXT4]], [[FPEXT5]]
87-
; NO-FP16: [[FPTRUNC1:%[0-9]+]]:_(s16) = G_FPTRUNC [[FMA1]](s32)
88-
; NO-FP16: [[FPEXT6:%[0-9]+]]:_(s32) = G_FPEXT [[UV2]](s16)
89-
; NO-FP16: [[FPEXT7:%[0-9]+]]:_(s32) = G_FPEXT [[UV10]](s16)
90-
; NO-FP16: [[FPEXT8:%[0-9]+]]:_(s32) = G_FPEXT [[UV18]](s16)
91-
; NO-FP16: [[FMA2:%[0-9]+]]:_(s32) = G_FMA [[FPEXT6]], [[FPEXT7]], [[FPEXT8]]
92-
; NO-FP16: [[FPTRUNC2:%[0-9]+]]:_(s16) = G_FPTRUNC [[FMA2]](s32)
93-
; NO-FP16: [[FPEXT9:%[0-9]+]]:_(s32) = G_FPEXT [[UV3]](s16)
94-
; NO-FP16: [[FPEXT10:%[0-9]+]]:_(s32) = G_FPEXT [[UV11]](s16)
95-
; NO-FP16: [[FPEXT11:%[0-9]+]]:_(s32) = G_FPEXT [[UV19]](s16)
96-
; NO-FP16: [[FMA3:%[0-9]+]]:_(s32) = G_FMA [[FPEXT9]], [[FPEXT10]], [[FPEXT11]]
97-
; NO-FP16: [[FPTRUNC3:%[0-9]+]]:_(s16) = G_FPTRUNC [[FMA3]](s32)
98-
; NO-FP16: [[FPEXT12:%[0-9]+]]:_(s32) = G_FPEXT [[UV4]](s16)
99-
; NO-FP16: [[FPEXT13:%[0-9]+]]:_(s32) = G_FPEXT [[UV12]](s16)
100-
; NO-FP16: [[FPEXT14:%[0-9]+]]:_(s32) = G_FPEXT [[UV20]](s16)
101-
; NO-FP16: [[FMA4:%[0-9]+]]:_(s32) = G_FMA [[FPEXT12]], [[FPEXT13]], [[FPEXT14]]
102-
; NO-FP16: [[FPTRUNC4:%[0-9]+]]:_(s16) = G_FPTRUNC [[FMA4]](s32)
103-
; NO-FP16: [[FPEXT15:%[0-9]+]]:_(s32) = G_FPEXT [[UV5]](s16)
104-
; NO-FP16: [[FPEXT16:%[0-9]+]]:_(s32) = G_FPEXT [[UV13]](s16)
105-
; NO-FP16: [[FPEXT17:%[0-9]+]]:_(s32) = G_FPEXT [[UV21]](s16)
106-
; NO-FP16: [[FMA5:%[0-9]+]]:_(s32) = G_FMA [[FPEXT15]], [[FPEXT16]], [[FPEXT17]]
107-
; NO-FP16: [[FPTRUNC5:%[0-9]+]]:_(s16) = G_FPTRUNC [[FMA5]](s32)
108-
; NO-FP16: [[FPEXT18:%[0-9]+]]:_(s32) = G_FPEXT [[UV6]](s16)
109-
; NO-FP16: [[FPEXT19:%[0-9]+]]:_(s32) = G_FPEXT [[UV14]](s16)
110-
; NO-FP16: [[FPEXT20:%[0-9]+]]:_(s32) = G_FPEXT [[UV22]](s16)
111-
; NO-FP16: [[FMA6:%[0-9]+]]:_(s32) = G_FMA [[FPEXT18]], [[FPEXT19]], [[FPEXT20]]
112-
; NO-FP16: [[FPTRUNC6:%[0-9]+]]:_(s16) = G_FPTRUNC [[FMA6]](s32)
113-
; NO-FP16: [[FPEXT21:%[0-9]+]]:_(s32) = G_FPEXT [[UV7]](s16)
114-
; NO-FP16: [[FPEXT22:%[0-9]+]]:_(s32) = G_FPEXT [[UV15]](s16)
115-
; NO-FP16: [[FPEXT23:%[0-9]+]]:_(s32) = G_FPEXT [[UV23]](s16)
116-
; NO-FP16: [[FMA7:%[0-9]+]]:_(s32) = G_FMA [[FPEXT21]], [[FPEXT22]], [[FPEXT23]]
117-
; NO-FP16: [[FPTRUNC7:%[0-9]+]]:_(s16) = G_FPTRUNC [[FMA7]](s32)
118-
; NO-FP16: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s16>) = G_BUILD_VECTOR [[FPTRUNC]](s16), [[FPTRUNC1]](s16), [[FPTRUNC2]](s16), [[FPTRUNC3]](s16), [[FPTRUNC4]](s16), [[FPTRUNC5]](s16), [[FPTRUNC6]](s16), [[FPTRUNC7]](s16)
119-
; NO-FP16: $q0 = COPY [[BUILD_VECTOR]](<8 x s16>)
120-
; NO-FP16: RET_ReallyLR implicit $q0
56+
; NO-FP16-NEXT: {{ $}}
57+
; NO-FP16-NEXT: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0
58+
; NO-FP16-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s16>) = COPY $q1
59+
; NO-FP16-NEXT: [[COPY2:%[0-9]+]]:_(<8 x s16>) = COPY $q2
60+
; NO-FP16-NEXT: [[UV:%[0-9]+]]:_(<4 x s16>), [[UV1:%[0-9]+]]:_(<4 x s16>) = G_UNMERGE_VALUES [[COPY]](<8 x s16>)
61+
; NO-FP16-NEXT: [[FPEXT:%[0-9]+]]:_(<4 x s32>) = G_FPEXT [[UV]](<4 x s16>)
62+
; NO-FP16-NEXT: [[FPEXT1:%[0-9]+]]:_(<4 x s32>) = G_FPEXT [[UV1]](<4 x s16>)
63+
; NO-FP16-NEXT: [[UV2:%[0-9]+]]:_(<4 x s16>), [[UV3:%[0-9]+]]:_(<4 x s16>) = G_UNMERGE_VALUES [[COPY1]](<8 x s16>)
64+
; NO-FP16-NEXT: [[FPEXT2:%[0-9]+]]:_(<4 x s32>) = G_FPEXT [[UV2]](<4 x s16>)
65+
; NO-FP16-NEXT: [[FPEXT3:%[0-9]+]]:_(<4 x s32>) = G_FPEXT [[UV3]](<4 x s16>)
66+
; NO-FP16-NEXT: [[UV4:%[0-9]+]]:_(<4 x s16>), [[UV5:%[0-9]+]]:_(<4 x s16>) = G_UNMERGE_VALUES [[COPY2]](<8 x s16>)
67+
; NO-FP16-NEXT: [[FPEXT4:%[0-9]+]]:_(<4 x s32>) = G_FPEXT [[UV4]](<4 x s16>)
68+
; NO-FP16-NEXT: [[FPEXT5:%[0-9]+]]:_(<4 x s32>) = G_FPEXT [[UV5]](<4 x s16>)
69+
; NO-FP16-NEXT: [[FMA:%[0-9]+]]:_(<4 x s32>) = G_FMA [[FPEXT]], [[FPEXT2]], [[FPEXT4]]
70+
; NO-FP16-NEXT: [[FMA1:%[0-9]+]]:_(<4 x s32>) = G_FMA [[FPEXT1]], [[FPEXT3]], [[FPEXT5]]
71+
; NO-FP16-NEXT: [[FPTRUNC:%[0-9]+]]:_(<4 x s16>) = G_FPTRUNC [[FMA]](<4 x s32>)
72+
; NO-FP16-NEXT: [[FPTRUNC1:%[0-9]+]]:_(<4 x s16>) = G_FPTRUNC [[FMA1]](<4 x s32>)
73+
; NO-FP16-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s16>) = G_CONCAT_VECTORS [[FPTRUNC]](<4 x s16>), [[FPTRUNC1]](<4 x s16>)
74+
; NO-FP16-NEXT: $q0 = COPY [[CONCAT_VECTORS]](<8 x s16>)
75+
; NO-FP16-NEXT: RET_ReallyLR implicit $q0
76+
;
12177
; FP16-LABEL: name: test_v8f16.fma
12278
; FP16: liveins: $q0, $q1, $q2
123-
; FP16: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0
124-
; FP16: [[COPY1:%[0-9]+]]:_(<8 x s16>) = COPY $q1
125-
; FP16: [[COPY2:%[0-9]+]]:_(<8 x s16>) = COPY $q2
126-
; FP16: [[FMA:%[0-9]+]]:_(<8 x s16>) = G_FMA [[COPY]], [[COPY1]], [[COPY2]]
127-
; FP16: $q0 = COPY [[FMA]](<8 x s16>)
128-
; FP16: RET_ReallyLR implicit $q0
79+
; FP16-NEXT: {{ $}}
80+
; FP16-NEXT: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0
81+
; FP16-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s16>) = COPY $q1
82+
; FP16-NEXT: [[COPY2:%[0-9]+]]:_(<8 x s16>) = COPY $q2
83+
; FP16-NEXT: [[FMA:%[0-9]+]]:_(<8 x s16>) = G_FMA [[COPY]], [[COPY1]], [[COPY2]]
84+
; FP16-NEXT: $q0 = COPY [[FMA]](<8 x s16>)
85+
; FP16-NEXT: RET_ReallyLR implicit $q0
12986
%0:_(<8 x s16>) = COPY $q0
13087
%1:_(<8 x s16>) = COPY $q1
13188
%2:_(<8 x s16>) = COPY $q2
@@ -145,20 +102,23 @@ body: |
145102
146103
; NO-FP16-LABEL: name: test_v2f32.fma
147104
; NO-FP16: liveins: $d0, $d1, $d2
148-
; NO-FP16: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
149-
; NO-FP16: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1
150-
; NO-FP16: [[COPY2:%[0-9]+]]:_(<2 x s32>) = COPY $d2
151-
; NO-FP16: [[FMA:%[0-9]+]]:_(<2 x s32>) = G_FMA [[COPY]], [[COPY1]], [[COPY2]]
152-
; NO-FP16: $d0 = COPY [[FMA]](<2 x s32>)
153-
; NO-FP16: RET_ReallyLR implicit $d0
105+
; NO-FP16-NEXT: {{ $}}
106+
; NO-FP16-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
107+
; NO-FP16-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1
108+
; NO-FP16-NEXT: [[COPY2:%[0-9]+]]:_(<2 x s32>) = COPY $d2
109+
; NO-FP16-NEXT: [[FMA:%[0-9]+]]:_(<2 x s32>) = G_FMA [[COPY]], [[COPY1]], [[COPY2]]
110+
; NO-FP16-NEXT: $d0 = COPY [[FMA]](<2 x s32>)
111+
; NO-FP16-NEXT: RET_ReallyLR implicit $d0
112+
;
154113
; FP16-LABEL: name: test_v2f32.fma
155114
; FP16: liveins: $d0, $d1, $d2
156-
; FP16: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
157-
; FP16: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1
158-
; FP16: [[COPY2:%[0-9]+]]:_(<2 x s32>) = COPY $d2
159-
; FP16: [[FMA:%[0-9]+]]:_(<2 x s32>) = G_FMA [[COPY]], [[COPY1]], [[COPY2]]
160-
; FP16: $d0 = COPY [[FMA]](<2 x s32>)
161-
; FP16: RET_ReallyLR implicit $d0
115+
; FP16-NEXT: {{ $}}
116+
; FP16-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
117+
; FP16-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1
118+
; FP16-NEXT: [[COPY2:%[0-9]+]]:_(<2 x s32>) = COPY $d2
119+
; FP16-NEXT: [[FMA:%[0-9]+]]:_(<2 x s32>) = G_FMA [[COPY]], [[COPY1]], [[COPY2]]
120+
; FP16-NEXT: $d0 = COPY [[FMA]](<2 x s32>)
121+
; FP16-NEXT: RET_ReallyLR implicit $d0
162122
%0:_(<2 x s32>) = COPY $d0
163123
%1:_(<2 x s32>) = COPY $d1
164124
%2:_(<2 x s32>) = COPY $d2
@@ -178,20 +138,23 @@ body: |
178138
179139
; NO-FP16-LABEL: name: test_v4f32.fma
180140
; NO-FP16: liveins: $q0, $q1, $q2
181-
; NO-FP16: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
182-
; NO-FP16: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1
183-
; NO-FP16: [[COPY2:%[0-9]+]]:_(<4 x s32>) = COPY $q2
184-
; NO-FP16: [[FMA:%[0-9]+]]:_(<4 x s32>) = G_FMA [[COPY]], [[COPY1]], [[COPY2]]
185-
; NO-FP16: $q0 = COPY [[FMA]](<4 x s32>)
186-
; NO-FP16: RET_ReallyLR implicit $q0
141+
; NO-FP16-NEXT: {{ $}}
142+
; NO-FP16-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
143+
; NO-FP16-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1
144+
; NO-FP16-NEXT: [[COPY2:%[0-9]+]]:_(<4 x s32>) = COPY $q2
145+
; NO-FP16-NEXT: [[FMA:%[0-9]+]]:_(<4 x s32>) = G_FMA [[COPY]], [[COPY1]], [[COPY2]]
146+
; NO-FP16-NEXT: $q0 = COPY [[FMA]](<4 x s32>)
147+
; NO-FP16-NEXT: RET_ReallyLR implicit $q0
148+
;
187149
; FP16-LABEL: name: test_v4f32.fma
188150
; FP16: liveins: $q0, $q1, $q2
189-
; FP16: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
190-
; FP16: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1
191-
; FP16: [[COPY2:%[0-9]+]]:_(<4 x s32>) = COPY $q2
192-
; FP16: [[FMA:%[0-9]+]]:_(<4 x s32>) = G_FMA [[COPY]], [[COPY1]], [[COPY2]]
193-
; FP16: $q0 = COPY [[FMA]](<4 x s32>)
194-
; FP16: RET_ReallyLR implicit $q0
151+
; FP16-NEXT: {{ $}}
152+
; FP16-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
153+
; FP16-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1
154+
; FP16-NEXT: [[COPY2:%[0-9]+]]:_(<4 x s32>) = COPY $q2
155+
; FP16-NEXT: [[FMA:%[0-9]+]]:_(<4 x s32>) = G_FMA [[COPY]], [[COPY1]], [[COPY2]]
156+
; FP16-NEXT: $q0 = COPY [[FMA]](<4 x s32>)
157+
; FP16-NEXT: RET_ReallyLR implicit $q0
195158
%0:_(<4 x s32>) = COPY $q0
196159
%1:_(<4 x s32>) = COPY $q1
197160
%2:_(<4 x s32>) = COPY $q2
@@ -211,20 +174,23 @@ body: |
211174
212175
; NO-FP16-LABEL: name: test_v2f64.fma
213176
; NO-FP16: liveins: $q0, $q1, $q2
214-
; NO-FP16: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
215-
; NO-FP16: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1
216-
; NO-FP16: [[COPY2:%[0-9]+]]:_(<2 x s64>) = COPY $q2
217-
; NO-FP16: [[FMA:%[0-9]+]]:_(<2 x s64>) = G_FMA [[COPY]], [[COPY1]], [[COPY2]]
218-
; NO-FP16: $q0 = COPY [[FMA]](<2 x s64>)
219-
; NO-FP16: RET_ReallyLR implicit $q0
177+
; NO-FP16-NEXT: {{ $}}
178+
; NO-FP16-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
179+
; NO-FP16-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1
180+
; NO-FP16-NEXT: [[COPY2:%[0-9]+]]:_(<2 x s64>) = COPY $q2
181+
; NO-FP16-NEXT: [[FMA:%[0-9]+]]:_(<2 x s64>) = G_FMA [[COPY]], [[COPY1]], [[COPY2]]
182+
; NO-FP16-NEXT: $q0 = COPY [[FMA]](<2 x s64>)
183+
; NO-FP16-NEXT: RET_ReallyLR implicit $q0
184+
;
220185
; FP16-LABEL: name: test_v2f64.fma
221186
; FP16: liveins: $q0, $q1, $q2
222-
; FP16: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
223-
; FP16: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1
224-
; FP16: [[COPY2:%[0-9]+]]:_(<2 x s64>) = COPY $q2
225-
; FP16: [[FMA:%[0-9]+]]:_(<2 x s64>) = G_FMA [[COPY]], [[COPY1]], [[COPY2]]
226-
; FP16: $q0 = COPY [[FMA]](<2 x s64>)
227-
; FP16: RET_ReallyLR implicit $q0
187+
; FP16-NEXT: {{ $}}
188+
; FP16-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
189+
; FP16-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1
190+
; FP16-NEXT: [[COPY2:%[0-9]+]]:_(<2 x s64>) = COPY $q2
191+
; FP16-NEXT: [[FMA:%[0-9]+]]:_(<2 x s64>) = G_FMA [[COPY]], [[COPY1]], [[COPY2]]
192+
; FP16-NEXT: $q0 = COPY [[FMA]](<2 x s64>)
193+
; FP16-NEXT: RET_ReallyLR implicit $q0
228194
%0:_(<2 x s64>) = COPY $q0
229195
%1:_(<2 x s64>) = COPY $q1
230196
%2:_(<2 x s64>) = COPY $q2

‎llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -154,7 +154,6 @@
154154
# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
155155
# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
156156
# DEBUG-NEXT: G_INTRINSIC_LRINT (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
157-
# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}}
158157
# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
159158
# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
160159
# DEBUG-NEXT: G_INTRINSIC_ROUNDEVEN (opcode {{[0-9]+}}): 1 type index, 0 imm indices
@@ -442,6 +441,7 @@
442441
# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
443442
# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
444443
# DEBUG-NEXT: G_FMA (opcode {{[0-9]+}}): 1 type index, 0 imm indices
444+
# DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}}
445445
# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
446446
# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
447447
# DEBUG-NEXT: G_FMAD (opcode {{[0-9]+}}): 1 type index, 0 imm indices

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