Fixed failing test.

Author: mgudim

clang/test/Misc/target-invalid-cpu-note.c

@@ -85,12 +85,12 @@
 
 // RUN: not %clang_cc1 -triple riscv64 -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix RISCV64
 // RISCV64: error: unknown target CPU 'not-a-cpu'
-// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280{{$}}
+// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, veyron-v1{{$}}
 
 // RUN: not %clang_cc1 -triple riscv32 -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE-RISCV32
 // TUNE-RISCV32: error: unknown target CPU 'not-a-cpu'
 // TUNE-RISCV32-NEXT: note: valid target CPU values are: generic-rv32, rocket-rv32, sifive-e20, sifive-e21, sifive-e24, sifive-e31, sifive-e34, sifive-e76, syntacore-scr1-base, syntacore-scr1-max, generic, rocket, sifive-7-series{{$}}
 
 // RUN: not %clang_cc1 -triple riscv64 -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE-RISCV64
 // TUNE-RISCV64: error: unknown target CPU 'not-a-cpu'
-// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, generic, rocket, sifive-7-series, veyron-v1{{$}}
+// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, veyron-v1, generic, rocket, sifive-7-series{{$}}

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

@@ -11633,39 +11633,15 @@ static SDValue performXORCombine(SDNode *N, SelectionDAG &DAG,
   return combineSelectAndUseCommutative(N, DAG, /*AllOnes*/ false, Subtarget);
 }
 
-/// According to the property that indexed load/store instructions zero-extend
-/// their indices, try to narrow the type of index operand.
+// According to the property that indexed load/store instructions
+// zero-extended their indices, \p narrowIndex tries to narrow the type of index
+// operand if it is matched to pattern (shl (zext x to ty), C) and bits(x) + C <
+// bits(ty).
 static bool narrowIndex(SDValue &N, ISD::MemIndexType IndexType, SelectionDAG &DAG) {
   if (isIndexTypeSigned(IndexType))
     return false;
 
-  if (!N->hasOneUse())
-    return false;
-
-  EVT VT = N.getValueType();
-  SDLoc DL(N);
-
-  // In general, what we're doing here is seeing if we can sink a truncate to
-  // a smaller element type into the expression tree building our index.
-  // TODO: We can generalize this and handle a bunch more cases if useful.
-
-  // Narrow a buildvector to the narrowest element type.  This requires less
-  // work and less register pressure at high LMUL, and creates smaller constants
-  // which may be cheaper to materialize.
-  if (ISD::isBuildVectorOfConstantSDNodes(N.getNode())) {
-    KnownBits Known = DAG.computeKnownBits(N);
-    unsigned ActiveBits = std::max(8u, Known.countMaxActiveBits());
-    LLVMContext &C = *DAG.getContext();
-    EVT ResultVT = EVT::getIntegerVT(C, ActiveBits).getRoundIntegerType(C);
-    if (ResultVT.bitsLT(VT.getVectorElementType())) {
-      N = DAG.getNode(ISD::TRUNCATE, DL,
-                      VT.changeVectorElementType(ResultVT), N);
-      return true;
-    }
-  }
-
-  // Handle the pattern (shl (zext x to ty), C) and bits(x) + C < bits(ty).
-  if (N.getOpcode() != ISD::SHL)
+  if (N.getOpcode() != ISD::SHL || !N->hasOneUse())
     return false;
 
   SDValue N0 = N.getOperand(0);

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll

@@ -13027,17 +13027,17 @@ define <8 x i16> @mgather_strided_2xSEW(ptr %base) {
 ; RV32-NEXT:    lui a1, %hi(.LCPI107_0)
 ; RV32-NEXT:    addi a1, a1, %lo(.LCPI107_0)
 ; RV32-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; RV32-NEXT:    vle8.v v9, (a1)
-; RV32-NEXT:    vluxei8.v v8, (a0), v9
+; RV32-NEXT:    vle32.v v10, (a1)
+; RV32-NEXT:    vluxei32.v v8, (a0), v10
 ; RV32-NEXT:    ret
 ;
 ; RV64V-LABEL: mgather_strided_2xSEW:
 ; RV64V:       # %bb.0:
 ; RV64V-NEXT:    lui a1, %hi(.LCPI107_0)
 ; RV64V-NEXT:    addi a1, a1, %lo(.LCPI107_0)
 ; RV64V-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; RV64V-NEXT:    vle8.v v9, (a1)
-; RV64V-NEXT:    vluxei8.v v8, (a0), v9
+; RV64V-NEXT:    vle64.v v12, (a1)
+; RV64V-NEXT:    vluxei64.v v8, (a0), v12
 ; RV64V-NEXT:    ret
 ;
 ; RV64ZVE32F-LABEL: mgather_strided_2xSEW:
@@ -13144,17 +13144,17 @@ define <8 x i16> @mgather_gather_2xSEW(ptr %base) {
 ; RV32-NEXT:    lui a1, %hi(.LCPI108_0)
 ; RV32-NEXT:    addi a1, a1, %lo(.LCPI108_0)
 ; RV32-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; RV32-NEXT:    vle8.v v9, (a1)
-; RV32-NEXT:    vluxei8.v v8, (a0), v9
+; RV32-NEXT:    vle32.v v10, (a1)
+; RV32-NEXT:    vluxei32.v v8, (a0), v10
 ; RV32-NEXT:    ret
 ;
 ; RV64V-LABEL: mgather_gather_2xSEW:
 ; RV64V:       # %bb.0:
 ; RV64V-NEXT:    lui a1, %hi(.LCPI108_0)
 ; RV64V-NEXT:    addi a1, a1, %lo(.LCPI108_0)
 ; RV64V-NEXT:    vsetivli zero, 8, e16, m1, ta, ma
-; RV64V-NEXT:    vle8.v v9, (a1)
-; RV64V-NEXT:    vluxei8.v v8, (a0), v9
+; RV64V-NEXT:    vle64.v v12, (a1)
+; RV64V-NEXT:    vluxei64.v v8, (a0), v12
 ; RV64V-NEXT:    ret
 ;
 ; RV64ZVE32F-LABEL: mgather_gather_2xSEW: