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Precommit tests for new targets
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‎llvm/test/CodeGen/ARM/scmp.ll‎

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -mtriple=armv7-unknown-eabi %s -o - | FileCheck %s
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define i8 @scmp_8_8(i8 signext %x, i8 signext %y) nounwind {
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; CHECK-LABEL: scmp_8_8:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: mov r2, #0
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; CHECK-NEXT: cmp r0, r1
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; CHECK-NEXT: movwgt r2, #1
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; CHECK-NEXT: cmp r2, #0
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; CHECK-NEXT: movwne r2, #1
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; CHECK-NEXT: cmp r0, r1
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; CHECK-NEXT: mvnlt r2, #0
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; CHECK-NEXT: mov r0, r2
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; CHECK-NEXT: bx lr
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%1 = call i8 @llvm.scmp(i8 %x, i8 %y)
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ret i8 %1
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}
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define i8 @scmp_8_16(i16 signext %x, i16 signext %y) nounwind {
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; CHECK-LABEL: scmp_8_16:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: mov r2, #0
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; CHECK-NEXT: cmp r0, r1
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; CHECK-NEXT: movwgt r2, #1
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; CHECK-NEXT: cmp r2, #0
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; CHECK-NEXT: movwne r2, #1
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; CHECK-NEXT: cmp r0, r1
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; CHECK-NEXT: mvnlt r2, #0
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; CHECK-NEXT: mov r0, r2
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; CHECK-NEXT: bx lr
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%1 = call i8 @llvm.scmp(i16 %x, i16 %y)
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ret i8 %1
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}
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define i8 @scmp_8_32(i32 %x, i32 %y) nounwind {
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; CHECK-LABEL: scmp_8_32:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: mov r2, #0
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; CHECK-NEXT: cmp r0, r1
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; CHECK-NEXT: movwgt r2, #1
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; CHECK-NEXT: cmp r2, #0
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; CHECK-NEXT: movwne r2, #1
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; CHECK-NEXT: cmp r0, r1
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; CHECK-NEXT: mvnlt r2, #0
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; CHECK-NEXT: mov r0, r2
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; CHECK-NEXT: bx lr
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%1 = call i8 @llvm.scmp(i32 %x, i32 %y)
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ret i8 %1
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}
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define i8 @scmp_8_64(i64 %x, i64 %y) nounwind {
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; CHECK-LABEL: scmp_8_64:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: .save {r11, lr}
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; CHECK-NEXT: push {r11, lr}
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; CHECK-NEXT: subs lr, r2, r0
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; CHECK-NEXT: mov r12, #0
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; CHECK-NEXT: sbcs lr, r3, r1
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; CHECK-NEXT: movwlt r12, #1
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; CHECK-NEXT: cmp r12, #0
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; CHECK-NEXT: movwne r12, #1
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; CHECK-NEXT: subs r0, r0, r2
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; CHECK-NEXT: sbcs r0, r1, r3
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; CHECK-NEXT: mvnlt r12, #0
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; CHECK-NEXT: mov r0, r12
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; CHECK-NEXT: pop {r11, pc}
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%1 = call i8 @llvm.scmp(i64 %x, i64 %y)
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ret i8 %1
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}
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define i8 @scmp_8_128(i128 %x, i128 %y) nounwind {
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; CHECK-LABEL: scmp_8_128:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: .save {r4, r5, r6, r7, r11, lr}
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; CHECK-NEXT: push {r4, r5, r6, r7, r11, lr}
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; CHECK-NEXT: ldr r5, [sp, #24]
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; CHECK-NEXT: mov r12, #0
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; CHECK-NEXT: ldr r6, [sp, #28]
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; CHECK-NEXT: subs r7, r5, r0
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; CHECK-NEXT: ldr lr, [sp, #32]
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; CHECK-NEXT: sbcs r7, r6, r1
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; CHECK-NEXT: ldr r4, [sp, #36]
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; CHECK-NEXT: sbcs r7, lr, r2
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; CHECK-NEXT: sbcs r7, r4, r3
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; CHECK-NEXT: movwlt r12, #1
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; CHECK-NEXT: cmp r12, #0
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; CHECK-NEXT: movwne r12, #1
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; CHECK-NEXT: subs r0, r0, r5
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; CHECK-NEXT: sbcs r0, r1, r6
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; CHECK-NEXT: sbcs r0, r2, lr
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; CHECK-NEXT: sbcs r0, r3, r4
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; CHECK-NEXT: mvnlt r12, #0
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; CHECK-NEXT: mov r0, r12
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; CHECK-NEXT: pop {r4, r5, r6, r7, r11, pc}
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%1 = call i8 @llvm.scmp(i128 %x, i128 %y)
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ret i8 %1
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}
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define i32 @scmp_32_32(i32 %x, i32 %y) nounwind {
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; CHECK-LABEL: scmp_32_32:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: mov r2, #0
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; CHECK-NEXT: cmp r0, r1
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; CHECK-NEXT: movwgt r2, #1
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; CHECK-NEXT: cmp r2, #0
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; CHECK-NEXT: movwne r2, #1
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; CHECK-NEXT: cmp r0, r1
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; CHECK-NEXT: mvnlt r2, #0
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; CHECK-NEXT: mov r0, r2
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; CHECK-NEXT: bx lr
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%1 = call i32 @llvm.scmp(i32 %x, i32 %y)
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ret i32 %1
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}
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define i32 @scmp_32_64(i64 %x, i64 %y) nounwind {
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; CHECK-LABEL: scmp_32_64:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: .save {r11, lr}
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; CHECK-NEXT: push {r11, lr}
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; CHECK-NEXT: subs lr, r2, r0
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; CHECK-NEXT: mov r12, #0
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; CHECK-NEXT: sbcs lr, r3, r1
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; CHECK-NEXT: movwlt r12, #1
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; CHECK-NEXT: cmp r12, #0
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; CHECK-NEXT: movwne r12, #1
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; CHECK-NEXT: subs r0, r0, r2
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; CHECK-NEXT: sbcs r0, r1, r3
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; CHECK-NEXT: mvnlt r12, #0
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; CHECK-NEXT: mov r0, r12
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; CHECK-NEXT: pop {r11, pc}
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%1 = call i32 @llvm.scmp(i64 %x, i64 %y)
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ret i32 %1
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}
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define i64 @scmp_64_64(i64 %x, i64 %y) nounwind {
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; CHECK-LABEL: scmp_64_64:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: .save {r11, lr}
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; CHECK-NEXT: push {r11, lr}
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; CHECK-NEXT: subs lr, r0, r2
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; CHECK-NEXT: mov r12, #0
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; CHECK-NEXT: sbcs lr, r1, r3
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; CHECK-NEXT: mov lr, #0
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; CHECK-NEXT: movwlt lr, #1
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; CHECK-NEXT: subs r0, r2, r0
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; CHECK-NEXT: sbcs r0, r3, r1
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; CHECK-NEXT: movwlt r12, #1
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; CHECK-NEXT: cmp r12, #0
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; CHECK-NEXT: movwne r12, #1
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; CHECK-NEXT: cmp lr, #0
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; CHECK-NEXT: mvnne r12, #0
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; CHECK-NEXT: mvnne lr, #0
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; CHECK-NEXT: mov r0, r12
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; CHECK-NEXT: mov r1, lr
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; CHECK-NEXT: pop {r11, pc}
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%1 = call i64 @llvm.scmp(i64 %x, i64 %y)
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ret i64 %1
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}

‎llvm/test/CodeGen/ARM/ucmp.ll‎

Lines changed: 159 additions & 0 deletions
Original file line numberDiff line numberDiff line change
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -mtriple=armv7-unknown-eabi %s -o - | FileCheck %s
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define i8 @ucmp_8_8(i8 zeroext %x, i8 zeroext %y) nounwind {
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; CHECK-LABEL: ucmp_8_8:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: mov r2, #0
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; CHECK-NEXT: cmp r0, r1
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; CHECK-NEXT: movwhi r2, #1
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; CHECK-NEXT: cmp r2, #0
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; CHECK-NEXT: movwne r2, #1
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; CHECK-NEXT: cmp r0, r1
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; CHECK-NEXT: mvnlo r2, #0
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; CHECK-NEXT: mov r0, r2
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; CHECK-NEXT: bx lr
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%1 = call i8 @llvm.ucmp(i8 %x, i8 %y)
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ret i8 %1
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}
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define i8 @ucmp_8_16(i16 zeroext %x, i16 zeroext %y) nounwind {
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; CHECK-LABEL: ucmp_8_16:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: mov r2, #0
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; CHECK-NEXT: cmp r0, r1
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; CHECK-NEXT: movwhi r2, #1
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; CHECK-NEXT: cmp r2, #0
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; CHECK-NEXT: movwne r2, #1
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; CHECK-NEXT: cmp r0, r1
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; CHECK-NEXT: mvnlo r2, #0
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; CHECK-NEXT: mov r0, r2
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; CHECK-NEXT: bx lr
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%1 = call i8 @llvm.ucmp(i16 %x, i16 %y)
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ret i8 %1
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}
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define i8 @ucmp_8_32(i32 %x, i32 %y) nounwind {
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; CHECK-LABEL: ucmp_8_32:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: mov r2, #0
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; CHECK-NEXT: cmp r0, r1
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; CHECK-NEXT: movwhi r2, #1
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; CHECK-NEXT: cmp r2, #0
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; CHECK-NEXT: movwne r2, #1
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; CHECK-NEXT: cmp r0, r1
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; CHECK-NEXT: mvnlo r2, #0
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; CHECK-NEXT: mov r0, r2
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; CHECK-NEXT: bx lr
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%1 = call i8 @llvm.ucmp(i32 %x, i32 %y)
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ret i8 %1
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}
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define i8 @ucmp_8_64(i64 %x, i64 %y) nounwind {
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; CHECK-LABEL: ucmp_8_64:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: .save {r11, lr}
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; CHECK-NEXT: push {r11, lr}
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; CHECK-NEXT: subs lr, r2, r0
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; CHECK-NEXT: mov r12, #0
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; CHECK-NEXT: sbcs lr, r3, r1
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; CHECK-NEXT: movwlo r12, #1
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; CHECK-NEXT: cmp r12, #0
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; CHECK-NEXT: movwne r12, #1
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; CHECK-NEXT: subs r0, r0, r2
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; CHECK-NEXT: sbcs r0, r1, r3
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; CHECK-NEXT: mvnlo r12, #0
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; CHECK-NEXT: mov r0, r12
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; CHECK-NEXT: pop {r11, pc}
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%1 = call i8 @llvm.ucmp(i64 %x, i64 %y)
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ret i8 %1
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}
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define i8 @ucmp_8_128(i128 %x, i128 %y) nounwind {
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; CHECK-LABEL: ucmp_8_128:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: .save {r4, r5, r6, r7, r11, lr}
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; CHECK-NEXT: push {r4, r5, r6, r7, r11, lr}
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; CHECK-NEXT: ldr r5, [sp, #24]
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; CHECK-NEXT: mov r12, #0
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; CHECK-NEXT: ldr r6, [sp, #28]
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; CHECK-NEXT: subs r7, r5, r0
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; CHECK-NEXT: ldr lr, [sp, #32]
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; CHECK-NEXT: sbcs r7, r6, r1
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; CHECK-NEXT: ldr r4, [sp, #36]
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; CHECK-NEXT: sbcs r7, lr, r2
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; CHECK-NEXT: sbcs r7, r4, r3
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; CHECK-NEXT: movwlo r12, #1
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; CHECK-NEXT: cmp r12, #0
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; CHECK-NEXT: movwne r12, #1
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; CHECK-NEXT: subs r0, r0, r5
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; CHECK-NEXT: sbcs r0, r1, r6
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; CHECK-NEXT: sbcs r0, r2, lr
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; CHECK-NEXT: sbcs r0, r3, r4
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; CHECK-NEXT: mvnlo r12, #0
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; CHECK-NEXT: mov r0, r12
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; CHECK-NEXT: pop {r4, r5, r6, r7, r11, pc}
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%1 = call i8 @llvm.ucmp(i128 %x, i128 %y)
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ret i8 %1
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}
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define i32 @ucmp_32_32(i32 %x, i32 %y) nounwind {
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; CHECK-LABEL: ucmp_32_32:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: mov r2, #0
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; CHECK-NEXT: cmp r0, r1
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; CHECK-NEXT: movwhi r2, #1
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; CHECK-NEXT: cmp r2, #0
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; CHECK-NEXT: movwne r2, #1
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; CHECK-NEXT: cmp r0, r1
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; CHECK-NEXT: mvnlo r2, #0
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; CHECK-NEXT: mov r0, r2
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; CHECK-NEXT: bx lr
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%1 = call i32 @llvm.ucmp(i32 %x, i32 %y)
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ret i32 %1
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}
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define i32 @ucmp_32_64(i64 %x, i64 %y) nounwind {
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; CHECK-LABEL: ucmp_32_64:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: .save {r11, lr}
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; CHECK-NEXT: push {r11, lr}
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; CHECK-NEXT: subs lr, r2, r0
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; CHECK-NEXT: mov r12, #0
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; CHECK-NEXT: sbcs lr, r3, r1
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; CHECK-NEXT: movwlo r12, #1
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; CHECK-NEXT: cmp r12, #0
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; CHECK-NEXT: movwne r12, #1
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; CHECK-NEXT: subs r0, r0, r2
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; CHECK-NEXT: sbcs r0, r1, r3
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; CHECK-NEXT: mvnlo r12, #0
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; CHECK-NEXT: mov r0, r12
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; CHECK-NEXT: pop {r11, pc}
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%1 = call i32 @llvm.ucmp(i64 %x, i64 %y)
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ret i32 %1
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}
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define i64 @ucmp_64_64(i64 %x, i64 %y) nounwind {
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; CHECK-LABEL: ucmp_64_64:
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; CHECK: @ %bb.0:
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; CHECK-NEXT: .save {r11, lr}
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; CHECK-NEXT: push {r11, lr}
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; CHECK-NEXT: subs lr, r0, r2
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; CHECK-NEXT: mov r12, #0
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; CHECK-NEXT: sbcs lr, r1, r3
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; CHECK-NEXT: mov lr, #0
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; CHECK-NEXT: movwlo lr, #1
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; CHECK-NEXT: subs r0, r2, r0
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; CHECK-NEXT: sbcs r0, r3, r1
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; CHECK-NEXT: movwlo r12, #1
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; CHECK-NEXT: cmp r12, #0
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; CHECK-NEXT: movwne r12, #1
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; CHECK-NEXT: cmp lr, #0
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; CHECK-NEXT: mvnne r12, #0
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; CHECK-NEXT: mvnne lr, #0
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; CHECK-NEXT: mov r0, r12
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; CHECK-NEXT: mov r1, lr
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; CHECK-NEXT: pop {r11, pc}
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%1 = call i64 @llvm.ucmp(i64 %x, i64 %y)
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ret i64 %1
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}

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