addressed comments

Author: fhossein-quic

llvm/lib/Target/Hexagon/HexagonQFPOptimizer.cpp

@@ -86,7 +86,8 @@ cl::opt<bool>
     DisableQFOptimizer("disable-qfp-opt", cl::init(false),
                        cl::desc("Disable optimization of Qfloat operations."));
 
-std::vector<unsigned short> QFPInst = {
+namespace{
+const std::vector<unsigned short> QFPInst = {
     Hexagon::V6_vadd_hf,          Hexagon::V6_vadd_qf16,
     Hexagon::V6_vadd_qf16_mix,    Hexagon::V6_vadd_qf32,
     Hexagon::V6_vadd_qf32_mix,    Hexagon::V6_vadd_sf,
@@ -100,7 +101,7 @@ std::vector<unsigned short> QFPInst = {
     Hexagon::V6_vsub_qf32,        Hexagon::V6_vsub_qf32_mix,
     Hexagon::V6_vsub_sf};
 
-std::map<unsigned short, unsigned short> QFPInstMap{
+const std::map<unsigned short, unsigned short> QFPInstMap{
     {Hexagon::V6_vadd_hf, Hexagon::V6_vadd_qf16_mix},
     {Hexagon::V6_vadd_qf16_mix, Hexagon::V6_vadd_qf16},
     {Hexagon::V6_vadd_sf, Hexagon::V6_vadd_qf32_mix},
@@ -114,6 +115,7 @@ std::map<unsigned short, unsigned short> QFPInstMap{
     {Hexagon::V6_vmpy_qf32_hf, Hexagon::V6_vmpy_qf32_mix_hf},
     {Hexagon::V6_vmpy_qf32_mix_hf, Hexagon::V6_vmpy_qf32_qf16},
     {Hexagon::V6_vmpy_qf32_sf, Hexagon::V6_vmpy_qf32}};
+}
 
 namespace llvm {
 
@@ -164,11 +166,22 @@ bool HexagonQFPoptimizer::optimizeQfp(MachineInstr *MI,
 
   unsigned Op0F = 0;
   unsigned Op1F = 0;
-  unsigned short InstTy = QFPInstMap[MI->getOpcode()];
+  auto It = QFPInstMap.find(MI->getOpcode());
+  if (It == QFPInstMap.end())
+    return false;
+  unsigned short InstTy = It->second;
 
   // Get the reaching defs of MI, DefMI1 and DefMI2
-  MachineInstr *DefMI1 = MRI->getVRegDef(MI->getOperand(1).getReg());
-  MachineInstr *DefMI2 = MRI->getVRegDef(MI->getOperand(2).getReg());
+  MachineInstr *DefMI1 = nullptr;
+  MachineInstr *DefMI2 = nullptr;
+
+  if (MI->getOperand(1).isReg())
+    DefMI1 = MRI->getVRegDef(MI->getOperand(1).getReg());
+  if (MI->getOperand(2).isReg())
+    DefMI2 = MRI->getVRegDef(MI->getOperand(2).getReg());
+  if (!DefMI1 || !DefMI2)
+    return false;
+
   MachineOperand &Res = MI->getOperand(0);
   MachineInstr *Inst1 = nullptr;
   MachineInstr *Inst2 = nullptr;
@@ -188,19 +201,22 @@ bool HexagonQFPoptimizer::optimizeQfp(MachineInstr *MI,
   unsigned Def2OP = DefMI2->getOpcode();
 
   MachineInstrBuilder MIB;
-  // Check if the both the reaching defs of MI and qf to sf/hf conversions
+  // Case 1: Both reaching defs of MI are qf to sf/hf conversions
   if ((Def1OP == Hexagon::V6_vconv_sf_qf32 &&
        Def2OP == Hexagon::V6_vconv_sf_qf32) ||
       (Def1OP == Hexagon::V6_vconv_hf_qf16 &&
        Def2OP == Hexagon::V6_vconv_hf_qf16)) {
 
     // If the reaching defs of DefMI are W register type, we return
-    if ((Inst1 && MRI->getRegClass(Inst1->getOperand(0).getReg()) ==
-                      &Hexagon::HvxWRRegClass) ||
-        (Inst2 && MRI->getRegClass(Inst2->getOperand(0).getReg()) ==
-                      &Hexagon::HvxWRRegClass))
+    if ((Inst1 && Inst1->getNumOperands() > 0 &&
+         Inst1->getOperand(0).isReg() &&
+         MRI->getRegClass(Inst1->getOperand(0).getReg()) == &Hexagon::HvxWRRegClass) ||
+        (Inst2 && Inst2->getNumOperands() > 0 &&
+         Inst2->getOperand(0).isReg() &&
+         MRI->getRegClass(Inst2->getOperand(0).getReg()) == &Hexagon::HvxWRRegClass))
       return false;
 
+
     // Analyze the use operands of the conversion to get their KILL status
     MachineOperand &Src1 = DefMI1->getOperand(1);
     MachineOperand &Src2 = DefMI2->getOperand(1);
@@ -211,16 +227,23 @@ bool HexagonQFPoptimizer::optimizeQfp(MachineInstr *MI,
     Op1F = getKillRegState(Src2.isKill());
     Src2.setIsKill(false);
 
-    if (MI->getOpcode() != Hexagon::V6_vmpy_qf32_sf)
-      InstTy = QFPInstMap[QFPInstMap[MI->getOpcode()]];
+    if (MI->getOpcode() != Hexagon::V6_vmpy_qf32_sf) {
+      auto OuterIt = QFPInstMap.find(MI->getOpcode());
+      if (OuterIt == QFPInstMap.end())
+        return false;
+      auto InnerIt = QFPInstMap.find(OuterIt->second);
+      if (InnerIt == QFPInstMap.end())
+        return false;
+      InstTy = InnerIt->second;
+    }
 
     MIB = BuildMI(*MBB, MI, MI->getDebugLoc(), HII->get(InstTy), Res.getReg())
               .addReg(Src1.getReg(), Op0F, Src1.getSubReg())
               .addReg(Src2.getReg(), Op1F, Src2.getSubReg());
     LLVM_DEBUG(dbgs() << "\n[Inserting]: "; MIB.getInstr()->dump());
     return true;
 
-    // Check if left operand's reaching def is a conversion to sf/hf
+    // Case 2: Left operand is conversion to sf/hf
   } else if (((Def1OP == Hexagon::V6_vconv_sf_qf32 &&
                Def2OP != Hexagon::V6_vconv_sf_qf32) ||
               (Def1OP == Hexagon::V6_vconv_hf_qf16 &&
@@ -244,7 +267,7 @@ bool HexagonQFPoptimizer::optimizeQfp(MachineInstr *MI,
     LLVM_DEBUG(dbgs() << "\n[Inserting]: "; MIB.getInstr()->dump());
     return true;
 
-    // Check if right operand's reaching def is a conversion tp sf/hf
+    // Case 2: Left operand is conversion to sf/hf
   } else if (((Def1OP != Hexagon::V6_vconv_sf_qf32 &&
                Def2OP == Hexagon::V6_vconv_sf_qf32) ||
               (Def1OP != Hexagon::V6_vconv_hf_qf16 &&