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rastogishubhamrastogishubham
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[DebugInfo][InstrRef] Treat ORRWrr as a copy instr
The insturction selector uses the MachineFunction::copySalvageSSA function to insert DBG_PHIs or identify a defining instruction for a copy-like instruction when finalizing Instruction References. AArch64 has the ORR instruction which is a logical OR with the variants ORRWrr which refers to a register to register variant, and ORRWrs which is a register to a shifted register variant. An ORRWrs where the shift amount is 0, and the zero register ($wzr) is used is considered a copy, for example: $w0 = ORRWrs $wzr, killed $w3, 0 however an ORRWrr with a zero register is not considered a copy $w0 = ORRWr $wzr, killed $w3 This causes an issue in the livedebugvalues pass because in aarch64-isel the instruction is the ORRWrr variant, but is then changed to the ORRWrs variant before the livedebugvalues pass. This causes a mismatch between the two passes which leads to a crash in the livedebugvalues pass. This patch fixes the issue.
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2 files changed

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‎llvm/lib/Target/AArch64/AArch64InstrInfo.cpp

+10-6
Original file line numberDiff line numberDiff line change
@@ -9722,9 +9722,11 @@ AArch64InstrInfo::isCopyInstrImpl(const MachineInstr &MI) const {
97229722

97239723
// AArch64::ORRWrs and AArch64::ORRXrs with WZR/XZR reg
97249724
// and zero immediate operands used as an alias for mov instruction.
9725-
if (MI.getOpcode() == AArch64::ORRWrs &&
9726-
MI.getOperand(1).getReg() == AArch64::WZR &&
9727-
MI.getOperand(3).getImm() == 0x0 &&
9725+
if (((MI.getOpcode() == AArch64::ORRWrs &&
9726+
MI.getOperand(1).getReg() == AArch64::WZR &&
9727+
MI.getOperand(3).getImm() == 0x0) ||
9728+
(MI.getOpcode() == AArch64::ORRWrr &&
9729+
MI.getOperand(1).getReg() == AArch64::WZR)) &&
97289730
// Check that the w->w move is not a zero-extending w->x mov.
97299731
(!MI.getOperand(0).getReg().isVirtual() ||
97309732
MI.getOperand(0).getSubReg() == 0) &&
@@ -9744,9 +9746,11 @@ AArch64InstrInfo::isCopyInstrImpl(const MachineInstr &MI) const {
97449746

97459747
std::optional<DestSourcePair>
97469748
AArch64InstrInfo::isCopyLikeInstrImpl(const MachineInstr &MI) const {
9747-
if (MI.getOpcode() == AArch64::ORRWrs &&
9748-
MI.getOperand(1).getReg() == AArch64::WZR &&
9749-
MI.getOperand(3).getImm() == 0x0)
9749+
if ((MI.getOpcode() == AArch64::ORRWrs &&
9750+
MI.getOperand(1).getReg() == AArch64::WZR &&
9751+
MI.getOperand(3).getImm() == 0x0) ||
9752+
(MI.getOpcode() == AArch64::ORRWrr &&
9753+
MI.getOperand(1).getReg() == AArch64::WZR))
97509754
return DestSourcePair{MI.getOperand(0), MI.getOperand(2)};
97519755
return std::nullopt;
97529756
}

‎llvm/test/CodeGen/AArch64/instr-ref-ldv.ll

+102
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,102 @@
1+
; RUN: llc -O2 -experimental-debug-variable-locations %s -stop-after=livedebugvalues -mtriple=arm64-apple-macosx15.0.0 -o - | FileCheck %s
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3+
; CHECK: $w{{[0-9]+}} = ORRWrs $wzr, killed $w{{[0-9]+}}, 0
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; CHECK-NEXT: DBG_INSTR_REF !{{[0-9]+}}, !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(3, 0), debug-location !{{[0-9]+}}
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6+
; This test makes sure that instruction referenced livedebugvalues pass doesn't crash when an ORRWrr is present before
7+
; aarch64-isel and is converted to an ORRWrs with a shift amount immediate value of 0 before livedebugvalues, in this
8+
; test case the MIR before both passes is shown below:
9+
10+
; Before aarch64-isel
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; %11:gpr32 = ORRWrr $wzr, killed %10:gpr32, debug-location !5; :0
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; %0:gpr64all = SUBREG_TO_REG 0, killed %11:gpr32, %subreg.sub_32, debug-location !5; :0
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; DBG_INSTR_REF !7, !DIExpression(DW_OP_LLVM_arg, 0), %0:gpr64all, debug-location !11; :0 @[ :0 ] line no:0
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; Before livedebugvalues
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; $w0 = ORRWrs $wzr, killed $w3, 0
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; DBG_INSTR_REF !7, !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(3, 0), debug-location !11; :0 @[ :0 ] line no:0
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; The livedebugvalues pass will consider the ORRWrs variant as a copy, therefore the aarch64-isel call to
20+
; salvageCopySSA should do the same.
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%"class.llvm::iterator_range.53" = type { %"class.llvm::opt::arg_iterator.54", %"class.llvm::opt::arg_iterator.54" }
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%"class.llvm::opt::arg_iterator.54" = type { %"class.std::__1::reverse_iterator", %"class.std::__1::reverse_iterator", [2 x %"class.llvm::opt::OptSpecifier"] }
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%"class.std::__1::reverse_iterator" = type { ptr, ptr }
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%"class.llvm::opt::OptSpecifier" = type { i32 }
29+
declare noundef zeroext i1 @_ZNK4llvm3opt6Option7matchesENS0_12OptSpecifierE(ptr noundef nonnull align 8 dereferenceable(16), i64) local_unnamed_addr #1
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define noundef zeroext i1 @_ZNK4llvm3opt7ArgList14hasFlagNoClaimENS0_12OptSpecifierES2_b(ptr noundef nonnull align 8 dereferenceable(184) %this, i64 %Pos.coerce, i64 %Neg.coerce, i1 noundef zeroext %Default) local_unnamed_addr #2 !dbg !9383 {
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entry:
32+
%ref.tmp.i = alloca %"class.llvm::iterator_range.53", align 8
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%coerce.val.ii6 = and i64 %Pos.coerce, 4294967295, !dbg !9393
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#dbg_value(i64 %coerce.val.ii6, !9452, !DIExpression(), !9480)
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%__begin0.sroa.4.0.ref.tmp.sroa_idx.i = getelementptr inbounds i8, ptr %ref.tmp.i, i64 8, !dbg !9489
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%__begin0.sroa.4.0.copyload.i = load ptr, ptr %__begin0.sroa.4.0.ref.tmp.sroa_idx.i, align 8, !dbg !9489
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%__end0.sroa.4.0.end_iterator.i.sroa_idx.i = getelementptr inbounds i8, ptr %ref.tmp.i, i64 48, !dbg !9495
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%__end0.sroa.4.0.copyload.i = load ptr, ptr %__end0.sroa.4.0.end_iterator.i.sroa_idx.i, align 8, !dbg !9495
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%cmp.i.i.i.not.i = icmp eq ptr %__begin0.sroa.4.0.copyload.i, %__end0.sroa.4.0.copyload.i, !dbg !9522
40+
br i1 %cmp.i.i.i.not.i, label %_ZNK4llvm3opt7ArgList17getLastArgNoClaimIJNS0_12OptSpecifierES3_EEEPNS0_3ArgEDpT_.exit.thread, label %_ZNK4llvm3opt7ArgList17getLastArgNoClaimIJNS0_12OptSpecifierES3_EEEPNS0_3ArgEDpT_.exit, !dbg !9523
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_ZNK4llvm3opt7ArgList17getLastArgNoClaimIJNS0_12OptSpecifierES3_EEEPNS0_3ArgEDpT_.exit.thread: ; preds = %entry
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br label %1, !dbg !9525
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_ZNK4llvm3opt7ArgList17getLastArgNoClaimIJNS0_12OptSpecifierES3_EEEPNS0_3ArgEDpT_.exit: ; preds = %entry
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%incdec.ptr.i.i.i = getelementptr inbounds i8, ptr %__begin0.sroa.4.0.copyload.i, i64 -8, !dbg !9526
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%0 = load ptr, ptr %incdec.ptr.i.i.i, align 8, !dbg !9527, !tbaa !9528
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%tobool.not.not = icmp eq ptr %0, null, !dbg !9525
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br i1 %tobool.not.not, label %1, label %cleanup, !dbg !9525
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cleanup: ; preds = %_ZNK4llvm3opt7ArgList17getLastArgNoClaimIJNS0_12OptSpecifierES3_EEEPNS0_3ArgEDpT_.exit
49+
%call13 = call noundef zeroext i1 @_ZNK4llvm3opt6Option7matchesENS0_12OptSpecifierE(ptr noundef nonnull align 8 dereferenceable(16) %0, i64 %coerce.val.ii6) #3, !dbg !9533
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br label %1
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%2 = phi i1 [ %call13, %cleanup ], [ %Default, %_ZNK4llvm3opt7ArgList17getLastArgNoClaimIJNS0_12OptSpecifierES3_EEEPNS0_3ArgEDpT_.exit ], [ %Default, %_ZNK4llvm3opt7ArgList17getLastArgNoClaimIJNS0_12OptSpecifierES3_EEEPNS0_3ArgEDpT_.exit.thread ]
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ret i1 %2, !dbg !9534
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}
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!llvm.module.flags = !{ !2, !6}
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!llvm.dbg.cu = !{!7}
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!2 = !{i32 2, !"Debug Info Version", i32 3}
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!6 = !{i32 7, !"frame-pointer", i32 1}
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!7 = distinct !DICompileUnit(language: DW_LANG_C_plus_plus_14, file: !8, emissionKind: FullDebug, sdk: "MacOSX15.3.sdk")
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!8 = !DIFile(filename: "/Users/shubhamrastogi/Development/llvm-project-instr-ref/llvm-project/llvm/lib/Option/ArgList.cpp", directory: "/Users/shubhamrastogi/Development/llvm-project-instr-ref/llvm-project/build-instr-ref-stage2", checksumkind: CSK_MD5, checksum: "a3198e8ace679c7b1581a26b5583c658")
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!3116 = distinct !DICompositeType(tag: DW_TAG_class_type, size: 32)
61+
!9383 = distinct !DISubprogram( unit: !7, flags: DIFlagArtificial | DIFlagObjectPointer)
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!9391 = distinct !DILexicalBlock(scope: !9383, line: 80, column: 12)
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!9393 = !DILocation( scope: !9391)
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!9395 = distinct !DISubprogram( unit: !7, retainedNodes: !9396)
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!9396 = !{}
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!9400 = distinct !DILocation( scope: !9401, inlinedAt: !9439)
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!9401 = distinct !DISubprogram( unit: !7, retainedNodes: !9436)
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!9436 = !{}
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!9439 = distinct !DILocation( scope: !9440, inlinedAt: !9478)
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!9440 = distinct !DILexicalBlock(scope: !9441, line: 269, column: 5)
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!9441 = distinct !DILexicalBlock(scope: !9442, line: 269, column: 5)
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!9442 = distinct !DISubprogram( unit: !7, retainedNodes: !9450)
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!9450 = !{}
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!9452 = !DILocalVariable( scope: !9442, type: !3116)
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!9478 = distinct !DILocation( scope: !9391)
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!9480 = !DILocation( scope: !9441, inlinedAt: !9478)
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!9484 = distinct !DISubprogram( unit: !7, retainedNodes: !9485)
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!9485 = !{}
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!9488 = distinct !DILocation( scope: !9441, inlinedAt: !9478)
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!9489 = !DILocation( scope: !9484, inlinedAt: !9488)
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!9491 = distinct !DISubprogram( unit: !7, retainedNodes: !9492)
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!9492 = !{}
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!9494 = distinct !DILocation( scope: !9441, inlinedAt: !9478)
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!9495 = !DILocation( scope: !9491, inlinedAt: !9494)
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!9497 = distinct !DISubprogram( unit: !7, retainedNodes: !9500)
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!9500 = !{}
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!9503 = distinct !DILocation( scope: !9441, inlinedAt: !9478)
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!9505 = distinct !DISubprogram( unit: !7, retainedNodes: !9509)
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!9509 = !{}
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!9515 = distinct !DILocation( scope: !9516, inlinedAt: !9520)
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!9516 = distinct !DISubprogram( unit: !7, retainedNodes: !9517)
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!9517 = !{}
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!9520 = distinct !DILocation( scope: !9497, inlinedAt: !9503)
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!9522 = !DILocation( scope: !9505, inlinedAt: !9515)
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!9523 = !DILocation( scope: !9441, inlinedAt: !9478)
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!9525 = !DILocation( scope: !9391)
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!9526 = !DILocation( scope: !9395, inlinedAt: !9400)
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!9527 = !DILocation( scope: !9440, inlinedAt: !9478)
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!9528 = !{!"any pointer", !9530, i64 0}
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!9530 = !{}
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!9533 = !DILocation( scope: !9391)
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!9534 = !DILocation( scope: !9383)

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