[X86] Fix failures on EXPENSIVE_CHECKS builds

Error message

```
*** Bad machine code: Illegal virtual register for instruction ***
- function:    test__blsi_u32
- basic block: %bb.0  (0x7a61208)
- instruction: %5:gr32 = MOV32r0 implicit-def $eflags
- operand 0:   %5:gr32
Expected a GR32_NOREX2 register, but got a GR32 register
```

Reported by RKSimon in #77433

The failure is b/c compiler emits a MOV32r0 with operand GR32 when
fast-isel is enabled.

```
// X86FastISel.cpp
Register SrcReg = fastEmitInst_(X86::MOV32r0, &X86::GR32RegClass)
```

However, before this patch, compiler only allows GR32_NOREX operand
b/c MOV32r0 is a pseudo instruction. In this patch, we relax the
register class of the operand to GR32 b/c MOV32r0 is always expanded
to XOR32rr, which can use EGPR.

The bug was not introduced by #77433 but caught by it.

Author: KanRobert

llvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h

@@ -1260,6 +1260,10 @@ inline bool canUseApxExtendedReg(const MCInstrDesc &Desc) {
   if (Encoding == X86II::EVEX)
     return true;
 
+  unsigned Opcode = Desc.Opcode;
+  // MOV32r0 is always expanded to XOR32rr
+  if (Opcode == X86::MOV32r0)
+    return true;
   // To be conservative, egpr is not used for all pseudo instructions
   // because we are not sure what instruction it will become.
   // FIXME: Could we improve it in X86ExpandPseudo?
@@ -1268,7 +1272,6 @@ inline bool canUseApxExtendedReg(const MCInstrDesc &Desc) {
 
   // MAP OB/TB in legacy encoding space can always use egpr except
   // XSAVE*/XRSTOR*.
-  unsigned Opcode = Desc.Opcode;
   switch (Opcode) {
   default:
     break;