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XinWang10XinWang10
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Fix error
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9 files changed

+166
-21
lines changed

9 files changed

+166
-21
lines changed

‎llvm/include/llvm/Support/X86DisassemblerDecoderCommon.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -140,7 +140,9 @@ enum attributeBits {
140140
ENUM_ENTRY(IC_EVEX, 1, "requires an EVEX prefix") \
141141
ENUM_ENTRY(IC_EVEX_NF, 2, "requires EVEX and NF prefix") \
142142
ENUM_ENTRY(IC_EVEX_XS, 2, "requires EVEX and the XS prefix") \
143+
ENUM_ENTRY(IC_EVEX_XS_ADSIZE, 3, "requires EVEX, XS and the ADSIZE prefix") \
143144
ENUM_ENTRY(IC_EVEX_XD, 2, "requires EVEX and the XD prefix") \
145+
ENUM_ENTRY(IC_EVEX_XD_ADSIZE, 3, "requires EVEX, XD and the ADSIZE prefix") \
144146
ENUM_ENTRY(IC_EVEX_OPSIZE, 2, "requires EVEX and the OpSize prefix") \
145147
ENUM_ENTRY(IC_EVEX_OPSIZE_NF, 3, "requires EVEX, NF and the OpSize prefix") \
146148
ENUM_ENTRY(IC_EVEX_OPSIZE_ADSIZE, 3, \

‎llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -941,6 +941,9 @@ static bool readOpcode(struct InternalInstruction *insn) {
941941
case VEX_LOB_MAP6:
942942
insn->opcodeType = MAP6;
943943
return consume(insn, insn->opcode);
944+
case VEX_LOB_MAP7:
945+
insn->opcodeType = MAP7;
946+
return consume(insn, insn->opcode);
944947
}
945948
} else if (insn->vectorExtensionType == TYPE_VEX_3B) {
946949
switch (mmmmmFromVEX2of3(insn->vectorExtensionPrefix[1])) {

‎llvm/lib/Target/X86/X86InstrSystem.td

Lines changed: 27 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -436,21 +436,34 @@ def WRMSRLIST : I<0x01, MRM_C6, (outs), (ins), "wrmsrlist", []>, TB, XS;
436436
def RDMSRLIST : I<0x01, MRM_C6, (outs), (ins), "rdmsrlist", []>, TB, XD;
437437
}
438438

439-
let Predicates = [HasUSERMSR], mayLoad = 1 in {
440-
def URDMSRrr : I<0xf8, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
441-
"urdmsr\t{$src, $dst|$dst, $src}",
442-
[(set GR64:$dst, (int_x86_urdmsr GR64:$src))]>, T8, XD;
443-
def URDMSRri : Ii32<0xf8, MRM0r, (outs GR64:$dst), (ins i64i32imm:$imm),
444-
"urdmsr\t{$imm, $dst|$dst, $imm}",
445-
[(set GR64:$dst, (int_x86_urdmsr i64immSExt32_su:$imm))]>, T_MAP7, XD, VEX;
439+
multiclass Urdwrmsr<Map rrmap, string suffix> {
440+
let mayLoad = 1 in {
441+
let OpMap = rrmap in
442+
def URDMSRrr#suffix : I<0xf8, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src),
443+
"urdmsr\t{$src, $dst|$dst, $src}",
444+
[(set GR64:$dst, (int_x86_urdmsr GR64:$src))]>, XD, NoCD8;
445+
def URDMSRri#suffix : Ii32<0xf8, MRM0r, (outs GR64:$dst), (ins i64i32imm:$imm),
446+
"urdmsr\t{$imm, $dst|$dst, $imm}",
447+
[(set GR64:$dst, (int_x86_urdmsr i64immSExt32_su:$imm))]>,
448+
T_MAP7, VEX, XD, NoCD8;
446449
}
447-
let Predicates = [HasUSERMSR], mayStore = 1 in {
448-
def UWRMSRrr : I<0xf8, MRMSrcReg, (outs), (ins GR64:$src1, GR64:$src2),
449-
"uwrmsr\t{$src2, $src1|$src1, $src2}",
450-
[(int_x86_uwrmsr GR64:$src1, GR64:$src2)]>, T8, XS;
451-
def UWRMSRir : Ii32<0xf8, MRM0r, (outs), (ins GR64:$src, i64i32imm:$imm),
452-
"uwrmsr\t{$src, $imm|$imm, $src}",
453-
[(int_x86_uwrmsr i64immSExt32_su:$imm, GR64:$src)]>, T_MAP7, XS, VEX;
450+
let mayStore = 1 in {
451+
let OpMap = rrmap in
452+
def UWRMSRrr#suffix : I<0xf8, MRMSrcReg, (outs), (ins GR64:$src1, GR64:$src2),
453+
"uwrmsr\t{$src2, $src1|$src1, $src2}",
454+
[(int_x86_uwrmsr GR64:$src1, GR64:$src2)]>, XS, NoCD8;
455+
def UWRMSRir#suffix : Ii32<0xf8, MRM0r, (outs), (ins GR64:$src, i64i32imm:$imm),
456+
"uwrmsr\t{$src, $imm|$imm, $src}",
457+
[(int_x86_uwrmsr i64immSExt32_su:$imm, GR64:$src)]>,
458+
T_MAP7, VEX, XS, NoCD8;
459+
}
460+
}
461+
462+
let Predicates = [HasUSERMSR, NoEGPR] in
463+
defm "" : Urdwrmsr<T8, "">;
464+
465+
let Predicates = [HasUSERMSR, HasEGPR, In64BitMode] in
466+
defm "" : Urdwrmsr<T_MAP4, "_EVEX">, EVEX;
454467

455468
let Defs = [RAX, RDX], Uses = [ECX] in
456469
def RDPMC : I<0x33, RawFrm, (outs), (ins), "rdpmc", []>, TB;

‎llvm/test/CodeGen/X86/usermsr-intrinsics.ll

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,11 +1,13 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
22
; RUN: llc < %s -verify-machineinstrs -mtriple=x86_64-unknown-unknown --show-mc-encoding -mattr=+usermsr | FileCheck %s --check-prefixes=X64
3+
; RUN: llc < %s -verify-machineinstrs -mtriple=x86_64-unknown-unknown --show-mc-encoding -mattr=+usermsr,+egpr | FileCheck %s --check-prefixes=EGPR
34

45
define i64 @test_int_x86_urdmsr(i64 %A) nounwind {
56
; X64-LABEL: test_int_x86_urdmsr:
67
; X64: # %bb.0:
78
; X64-NEXT: urdmsr %rdi, %rax # encoding: [0xf2,0x0f,0x38,0xf8,0xc7]
89
; X64-NEXT: retq # encoding: [0xc3]
10+
;
911
; EGPR-LABEL: test_int_x86_urdmsr:
1012
; EGPR: # %bb.0:
1113
; EGPR-NEXT: urdmsr %rdi, %rax # EVEX TO LEGACY Compression encoding: [0xf2,0x0f,0x38,0xf8,0xc7]
@@ -19,6 +21,7 @@ define i64 @test_int_x86_urdmsr_const() nounwind {
1921
; X64: # %bb.0:
2022
; X64-NEXT: urdmsr $123, %rax # encoding: [0xc4,0xe7,0x7b,0xf8,0xc0,0x7b,0x00,0x00,0x00]
2123
; X64-NEXT: retq # encoding: [0xc3]
24+
;
2225
; EGPR-LABEL: test_int_x86_urdmsr_const:
2326
; EGPR: # %bb.0:
2427
; EGPR-NEXT: urdmsr $123, %rax # EVEX TO VEX Compression encoding: [0xc4,0xe7,0x7b,0xf8,0xc0,0x7b,0x00,0x00,0x00]
@@ -34,6 +37,7 @@ define i64 @test_int_x86_urdmsr_const_i64() nounwind {
3437
; X64-NEXT: # imm = 0x1FFFFFFFF
3538
; X64-NEXT: urdmsr %rax, %rax # encoding: [0xf2,0x0f,0x38,0xf8,0xc0]
3639
; X64-NEXT: retq # encoding: [0xc3]
40+
;
3741
; EGPR-LABEL: test_int_x86_urdmsr_const_i64:
3842
; EGPR: # %bb.0:
3943
; EGPR-NEXT: movabsq $8589934591, %rax # encoding: [0x48,0xb8,0xff,0xff,0xff,0xff,0x01,0x00,0x00,0x00]
@@ -51,6 +55,7 @@ define void @test_int_x86_uwrmsr(i64 %A, i64 %B) nounwind {
5155
; X64: # %bb.0:
5256
; X64-NEXT: uwrmsr %rsi, %rdi # encoding: [0xf3,0x0f,0x38,0xf8,0xfe]
5357
; X64-NEXT: retq # encoding: [0xc3]
58+
;
5459
; EGPR-LABEL: test_int_x86_uwrmsr:
5560
; EGPR: # %bb.0:
5661
; EGPR-NEXT: uwrmsr %rsi, %rdi # EVEX TO LEGACY Compression encoding: [0xf3,0x0f,0x38,0xf8,0xfe]
@@ -64,6 +69,7 @@ define void @test_int_x86_uwrmsr_const(i64 %A) nounwind {
6469
; X64: # %bb.0:
6570
; X64-NEXT: uwrmsr %rdi, $123 # encoding: [0xc4,0xe7,0x7a,0xf8,0xc7,0x7b,0x00,0x00,0x00]
6671
; X64-NEXT: retq # encoding: [0xc3]
72+
;
6773
; EGPR-LABEL: test_int_x86_uwrmsr_const:
6874
; EGPR: # %bb.0:
6975
; EGPR-NEXT: uwrmsr %rdi, $123 # EVEX TO VEX Compression encoding: [0xc4,0xe7,0x7a,0xf8,0xc7,0x7b,0x00,0x00,0x00]
@@ -79,6 +85,7 @@ define void @test_int_x86_uwrmsr_const_i64(i64 %A) nounwind {
7985
; X64-NEXT: # imm = 0x1FFFFFFFF
8086
; X64-NEXT: uwrmsr %rdi, %rax # encoding: [0xf3,0x0f,0x38,0xf8,0xc7]
8187
; X64-NEXT: retq # encoding: [0xc3]
88+
;
8289
; EGPR-LABEL: test_int_x86_uwrmsr_const_i64:
8390
; EGPR: # %bb.0:
8491
; EGPR-NEXT: movabsq $8589934591, %rax # encoding: [0x48,0xb8,0xff,0xff,0xff,0xff,0x01,0x00,0x00,0x00]

‎llvm/test/MC/Disassembler/X86/apx/user-msr.txt

Lines changed: 38 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,38 @@
1+
# RUN: llvm-mc --disassemble %s -triple=x86_64 | FileCheck %s --check-prefixes=ATT
2+
# RUN: llvm-mc --disassemble %s -triple=x86_64 -x86-asm-syntax=intel --output-asm-variant=1 | FileCheck %s --check-prefixes=INTEL
3+
4+
## urdmsr
5+
6+
# ATT: urdmsr $123, %r9
7+
# INTEL: urdmsr r9, 123
8+
0x62,0xd7,0x7f,0x08,0xf8,0xc1,0x7b,0x00,0x00,0x00
9+
10+
# ATT: urdmsr %r9, %r15
11+
# INTEL: urdmsr r15, r9
12+
0x62,0x54,0x7f,0x08,0xf8,0xf9
13+
14+
# ATT: urdmsr $123, %r19
15+
# INTEL: urdmsr r19, 123
16+
0x62,0xff,0x7f,0x08,0xf8,0xc3,0x7b,0x00,0x00,0x00
17+
18+
# ATT: urdmsr %r19, %r23
19+
# INTEL: urdmsr r23, r19
20+
0x62,0xec,0x7f,0x08,0xf8,0xfb
21+
22+
## uwrmsr
23+
24+
# ATT: uwrmsr %r9, $123
25+
# INTEL: uwrmsr 123, r9
26+
0x62,0xd7,0x7e,0x08,0xf8,0xc1,0x7b,0x00,0x00,0x00
27+
28+
# ATT: uwrmsr %r9, %r15
29+
# INTEL: uwrmsr r15, r9
30+
0x62,0x54,0x7e,0x08,0xf8,0xf9
31+
32+
# ATT: uwrmsr %r19, $123
33+
# INTEL: uwrmsr 123, r19
34+
0x62,0xff,0x7e,0x08,0xf8,0xc3,0x7b,0x00,0x00,0x00
35+
36+
# ATT: uwrmsr %r19, %r23
37+
# INTEL: uwrmsr r23, r19
38+
0x62,0xec,0x7e,0x08,0xf8,0xfb

‎llvm/test/MC/X86/apx/user-msr-att.s

Lines changed: 41 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,41 @@
1+
# RUN: llvm-mc -triple x86_64 --show-encoding %s | FileCheck %s
2+
# RUN: not llvm-mc -triple i386 -show-encoding %s 2>&1 | FileCheck %s --check-prefix=ERROR
3+
4+
# ERROR-COUNT-8: error:
5+
# ERROR-NOT: error:
6+
7+
## urdmsr
8+
9+
# CHECK: {evex} urdmsr $123, %r9
10+
# CHECK: encoding: [0x62,0xd7,0x7f,0x08,0xf8,0xc1,0x7b,0x00,0x00,0x00]
11+
{evex} urdmsr $123, %r9
12+
13+
# CHECK: {evex} urdmsr %r9, %r15
14+
# CHECK: encoding: [0x62,0x54,0x7f,0x08,0xf8,0xf9]
15+
{evex} urdmsr %r9, %r15
16+
17+
# CHECK: urdmsr $123, %r19
18+
# CHECK: encoding: [0x62,0xff,0x7f,0x08,0xf8,0xc3,0x7b,0x00,0x00,0x00]
19+
urdmsr $123, %r19
20+
21+
# CHECK: urdmsr %r19, %r23
22+
# CHECK: encoding: [0x62,0xec,0x7f,0x08,0xf8,0xfb]
23+
urdmsr %r19, %r23
24+
25+
## uwrmsr
26+
27+
# CHECK: {evex} uwrmsr %r9, $123
28+
# CHECK: encoding: [0x62,0xd7,0x7e,0x08,0xf8,0xc1,0x7b,0x00,0x00,0x00]
29+
{evex} uwrmsr %r9, $123
30+
31+
# CHECK: {evex} uwrmsr %r9, %r15
32+
# CHECK: encoding: [0x62,0x54,0x7e,0x08,0xf8,0xf9]
33+
{evex} uwrmsr %r9, %r15
34+
35+
# CHECK: uwrmsr %r19, $123
36+
# CHECK: encoding: [0x62,0xff,0x7e,0x08,0xf8,0xc3,0x7b,0x00,0x00,0x00]
37+
uwrmsr %r19, $123
38+
39+
# CHECK: uwrmsr %r19, %r23
40+
# CHECK: encoding: [0x62,0xec,0x7e,0x08,0xf8,0xfb]
41+
uwrmsr %r19, %r23

‎llvm/test/MC/X86/apx/user-msr-intel.s

Lines changed: 37 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,37 @@
1+
# RUN: llvm-mc -triple x86_64 -x86-asm-syntax=intel -output-asm-variant=1 --show-encoding %s | FileCheck %s
2+
3+
## urdmsr
4+
5+
# CHECK: {evex} urdmsr r9, 123
6+
# CHECK: encoding: [0x62,0xd7,0x7f,0x08,0xf8,0xc1,0x7b,0x00,0x00,0x00]
7+
{evex} urdmsr r9, 123
8+
9+
# CHECK: {evex} urdmsr r15, r9
10+
# CHECK: encoding: [0x62,0x54,0x7f,0x08,0xf8,0xf9]
11+
{evex} urdmsr r15, r9
12+
13+
# CHECK: urdmsr r19, 123
14+
# CHECK: encoding: [0x62,0xff,0x7f,0x08,0xf8,0xc3,0x7b,0x00,0x00,0x00]
15+
urdmsr r19, 123
16+
17+
# CHECK: urdmsr r23, r19
18+
# CHECK: encoding: [0x62,0xec,0x7f,0x08,0xf8,0xfb]
19+
urdmsr r23, r19
20+
21+
## uwrmsr
22+
23+
# CHECK: {evex} uwrmsr 123, r9
24+
# CHECK: encoding: [0x62,0xd7,0x7e,0x08,0xf8,0xc1,0x7b,0x00,0x00,0x00]
25+
{evex} uwrmsr 123, r9
26+
27+
# CHECK: {evex} uwrmsr r15, r9
28+
# CHECK: encoding: [0x62,0x54,0x7e,0x08,0xf8,0xf9]
29+
{evex} uwrmsr r15, r9
30+
31+
# CHECK: uwrmsr 123, r19
32+
# CHECK: encoding: [0x62,0xff,0x7e,0x08,0xf8,0xc3,0x7b,0x00,0x00,0x00]
33+
uwrmsr 123, r19
34+
35+
# CHECK: uwrmsr r23, r19
36+
# CHECK: encoding: [0x62,0xec,0x7e,0x08,0xf8,0xfb]
37+
uwrmsr r23, r19

‎llvm/utils/TableGen/X86DisassemblerTables.cpp

Lines changed: 7 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -214,6 +214,8 @@ static inline bool inheritsFrom(InstructionContext child,
214214
(VEX_LIG && inheritsFrom(child, IC_EVEX_L_OPSIZE)) ||
215215
(VEX_LIG && inheritsFrom(child, IC_EVEX_L2_OPSIZE));
216216
case IC_EVEX_OPSIZE_ADSIZE:
217+
case IC_EVEX_XS_ADSIZE:
218+
case IC_EVEX_XD_ADSIZE:
217219
return false;
218220
case IC_EVEX_K:
219221
return (VEX_LIG && WIG && inheritsFrom(child, IC_EVEX_L_W_K)) ||
@@ -894,8 +896,12 @@ void DisassemblerTables::emitContextTable(raw_ostream &o, unsigned &i) const {
894896
for (unsigned index = 0; index < ATTR_max; ++index) {
895897
o.indent(i * 2);
896898

897-
if ((index & ATTR_EVEX) && (index & ATTR_OPSIZE) && (index & ATTR_ADSIZE))
899+
if ((index & ATTR_EVEX) && (index & ATTR_ADSIZE) && (index & ATTR_OPSIZE))
898900
o << "IC_EVEX_OPSIZE_ADSIZE";
901+
else if ((index & ATTR_EVEX) && (index & ATTR_ADSIZE) && (index & ATTR_XD))
902+
o << "IC_EVEX_XD_ADSIZE";
903+
else if ((index & ATTR_EVEX) && (index & ATTR_ADSIZE) && (index & ATTR_XS))
904+
o << "IC_EVEX_XS_ADSIZE";
899905
else if (index & ATTR_EVEXNF) {
900906
o << "IC_EVEX";
901907
if (index & ATTR_REXW)

‎llvm/utils/TableGen/X86RecognizableInstr.cpp

Lines changed: 4 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -188,6 +188,7 @@ void RecognizableInstr::processInstr(DisassemblerTables &tables,
188188

189189
#define EVEX_NF(n) (HasEVEX_NF ? n##_NF : n)
190190
#define EVEX_B_NF(n) (HasEVEX_B ? EVEX_NF(n##_B) : EVEX_NF(n))
191+
#define EVEX_KB_ADSIZE(n) AdSize == X86Local::AdSize32 ? n##_ADSIZE : EVEX_KB(n)
191192

192193
InstructionContext RecognizableInstr::insnContext() const {
193194
InstructionContext insnContext;
@@ -277,14 +278,11 @@ InstructionContext RecognizableInstr::insnContext() const {
277278
}
278279
// No L, no W
279280
else if (OpPrefix == X86Local::PD) {
280-
if (AdSize == X86Local::AdSize32)
281-
insnContext = IC_EVEX_OPSIZE_ADSIZE;
282-
else
283-
insnContext = EVEX_KB(IC_EVEX_OPSIZE);
281+
insnContext = EVEX_KB_ADSIZE(IC_EVEX_OPSIZE);
284282
} else if (OpPrefix == X86Local::XD)
285-
insnContext = EVEX_KB(IC_EVEX_XD);
283+
insnContext = EVEX_KB_ADSIZE(IC_EVEX_XD);
286284
else if (OpPrefix == X86Local::XS)
287-
insnContext = EVEX_KB(IC_EVEX_XS);
285+
insnContext = EVEX_KB_ADSIZE(IC_EVEX_XS);
288286
else if (OpPrefix == X86Local::PS)
289287
insnContext = EVEX_KB(IC_EVEX);
290288
else {

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