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[X86] Copy X86SchedSkylakeServer.td to X86SchedIceLake.td
Icelake, Rocketlake and Tigerlake targets currently use the SkylakeServer scheduler model, despite being a later microarchitecture, leading to both reported bugs (PR48110) and discrepancies when comparing llvm-mca reports to other profiling tools (OSACA, uops, uica, etc.). And tbh I'm getting sick of llvm-mca getting blamed for what are backend scheduler model issues :-( This patch doesn't attempt to fix any of these discrepancies - there should be no changes in codegen - its a setup patch that copies the skx model, renames all the resources, adds the additional ports (but doesn't reference them yet) and updates the llvm-exegesis pfm counter mappings (based off https://sourceforge.net/p/perfmon2/libpfm4/ci/master/tree/lib/events/intel_icl_events.h). This should make it trivial for anyone with hardware access to use llvm-exegesis reports to iteratively improve the model (my attempts to get hold of a cheap tiger lake box haven't been fruitful yet....). I will copy the SkylakeServer llvm-mca resource tests as follow up commits - the diff should entirely be the resource renames. Differential Revision: https://reviews.llvm.org/D108914
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llvm/lib/Target/X86/X86.td

Lines changed: 5 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -612,6 +612,7 @@ include "X86ScheduleBdVer2.td"
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include "X86ScheduleBtVer2.td"
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include "X86SchedSkylakeClient.td"
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include "X86SchedSkylakeServer.td"
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include "X86SchedIceLake.td"
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//===----------------------------------------------------------------------===//
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// X86 Processor Feature Lists
@@ -1372,13 +1373,13 @@ def : ProcModel<"cooperlake", SkylakeServerModel,
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ProcessorFeatures.CPXFeatures, ProcessorFeatures.CPXTuning>;
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def : ProcModel<"cannonlake", SkylakeServerModel,
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ProcessorFeatures.CNLFeatures, ProcessorFeatures.CNLTuning>;
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def : ProcModel<"icelake-client", SkylakeServerModel,
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def : ProcModel<"icelake-client", IceLakeModel,
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ProcessorFeatures.ICLFeatures, ProcessorFeatures.ICLTuning>;
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def : ProcModel<"rocketlake", SkylakeServerModel,
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def : ProcModel<"rocketlake", IceLakeModel,
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ProcessorFeatures.ICLFeatures, ProcessorFeatures.ICLTuning>;
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def : ProcModel<"icelake-server", SkylakeServerModel,
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def : ProcModel<"icelake-server", IceLakeModel,
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ProcessorFeatures.ICXFeatures, ProcessorFeatures.ICXTuning>;
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def : ProcModel<"tigerlake", SkylakeServerModel,
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def : ProcModel<"tigerlake", IceLakeModel,
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ProcessorFeatures.TGLFeatures, ProcessorFeatures.TGLTuning>;
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def : ProcModel<"sapphirerapids", SkylakeServerModel,
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ProcessorFeatures.SPRFeatures, ProcessorFeatures.SPRTuning>;

llvm/lib/Target/X86/X86PfmCounters.td

Lines changed: 18 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -142,8 +142,24 @@ def SkylakeServerPfmCounters : ProcPfmCounters {
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def : PfmCountersBinding<"skylake-avx512", SkylakeServerPfmCounters>;
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def : PfmCountersBinding<"cascadelake", SkylakeServerPfmCounters>;
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def : PfmCountersBinding<"cannonlake", SkylakeServerPfmCounters>;
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def : PfmCountersBinding<"icelake-client", SkylakeServerPfmCounters>;
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def : PfmCountersBinding<"icelake-server", SkylakeServerPfmCounters>;
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def IceLakePfmCounters : ProcPfmCounters {
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let CycleCounter = UnhaltedCoreCyclesPfmCounter;
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let UopsCounter = UopsIssuedPfmCounter;
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let IssueCounters = [
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PfmIssueCounter<"ICXPort0", "uops_dispatched_port:port_0">,
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PfmIssueCounter<"ICXPort1", "uops_dispatched_port:port_1">,
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PfmIssueCounter<"ICXPort23", "uops_dispatched_port:port_2_3">,
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PfmIssueCounter<"ICXPort49", "uops_dispatched_port:port_4_9">,
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PfmIssueCounter<"ICXPort5", "uops_dispatched_port:port_5">,
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PfmIssueCounter<"ICXPort6", "uops_dispatched_port:port_6">,
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PfmIssueCounter<"ICXPort78", "uops_dispatched_port:port_7_8">
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];
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}
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def : PfmCountersBinding<"icelake-client", IceLakePfmCounters>;
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def : PfmCountersBinding<"icelake-server", IceLakePfmCounters>;
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def : PfmCountersBinding<"rocketlake", IceLakePfmCounters>;
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def : PfmCountersBinding<"tigerlake", IceLakePfmCounters>;
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// AMD X86 Counters.
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// Set basic counters for AMD cpus that we know libpfm4 supports.

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