@@ -68,7 +68,7 @@ class RISCVVectorPeephole : public MachineFunctionPass {
6868 bool convertVMergeToVMv (MachineInstr &MI) const ;
6969 bool foldVMV_V_V (MachineInstr &MI);
7070
71- bool hasSameEEWVLMAX (const MachineInstr &User, const MachineInstr &Src) const ;
71+ bool hasSameEEW (const MachineInstr &User, const MachineInstr &Src) const ;
7272 bool isAllOnesMask (const MachineInstr *MaskDef) const ;
7373 std::optional<unsigned > getConstant (const MachineOperand &VL) const ;
7474 bool ensureDominates (const MachineOperand &Use, MachineInstr &Src) const ;
@@ -98,28 +98,17 @@ static bool isVLKnownLE(const MachineOperand &LHS, const MachineOperand &RHS) {
9898 return LHS.getImm () <= RHS.getImm ();
9999}
100100
101- static unsigned getSEWLMULRatio (const MachineInstr &MI) {
102- RISCVII::VLMUL LMUL = RISCVII::getLMul (MI.getDesc ().TSFlags );
103- unsigned Log2SEW = MI.getOperand (RISCVII::getSEWOpNum (MI.getDesc ())).getImm ();
104- return RISCVVType::getSEWLMULRatio (1 << Log2SEW, LMUL);
105- }
106-
107- // / Given \p User that has an input operand with EEW=SEW, which uses an output
108- // / operand of \p Src with an unknown EEW, return true if their EEWs match and
109- // / they have the same VLMAX.
110- bool RISCVVectorPeephole::hasSameEEWVLMAX (const MachineInstr &User,
111- const MachineInstr &Src) const {
112- if (getSEWLMULRatio (User) != getSEWLMULRatio (Src))
113- return false ;
114- unsigned UserLog2SEW =
101+ // / Given \p User that has an input operand with EEW=SEW, which uses the dest
102+ // / operand of \p Src with an unknown EEW, return true if their EEWs match.
103+ bool RISCVVectorPeephole::hasSameEEW (const MachineInstr &User,
104+ const MachineInstr &Src) const {
105+ unsigned UserSEW =
115106 User.getOperand (RISCVII::getSEWOpNum (User.getDesc ())).getImm ();
116- unsigned SrcLog2SEW =
107+ unsigned SrcSEW =
117108 Src.getOperand (RISCVII::getSEWOpNum (Src.getDesc ())).getImm ();
118- if (RISCV::getDestEEW (TII->get (RISCV::getRVVMCOpcode (Src.getOpcode ())),
119- SrcLog2SEW) != UserLog2SEW)
120- return false ;
121-
122- return true ;
109+ unsigned SrcEEW = RISCV::getDestEEW (
110+ TII->get (RISCV::getRVVMCOpcode (Src.getOpcode ())), SrcSEW);
111+ return SrcEEW == UserSEW;
123112}
124113
125114// Attempt to reduce the VL of an instruction whose sole use is feeding a
@@ -172,8 +161,8 @@ bool RISCVVectorPeephole::tryToReduceVL(MachineInstr &MI) const {
172161 !RISCVII::hasSEWOp (Src->getDesc ().TSFlags ))
173162 return false ;
174163
175- // Src needs to have the same VLMAX and EEW as MI
176- if (!hasSameEEWVLMAX (MI, *Src))
164+ // Src's dest needs to have the same EEW as MI's input.
165+ if (!hasSameEEW (MI, *Src))
177166 return false ;
178167
179168 bool ElementsDependOnVL = RISCVII::elementsDependOnVL (
@@ -518,8 +507,8 @@ bool RISCVVectorPeephole::foldVMV_V_V(MachineInstr &MI) {
518507 !RISCVII::hasVecPolicyOp (Src->getDesc ().TSFlags ))
519508 return false ;
520509
521- // Src needs to have the same VLMAX and EEW as MI
522- if (!hasSameEEWVLMAX (MI, *Src))
510+ // Src's dest needs to have the same EEW as MI's input.
511+ if (!hasSameEEW (MI, *Src))
523512 return false ;
524513
525514 // Src needs to have the same passthru as VMV_V_V
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