Test cases for rem-seteq fold with illegal types

This also briefly tests a larger set of architectures than the more
exhaustive functionality tests for AArch64 and x86.

As requested in D88785

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D98339

Author: nagisa

llvm/test/CodeGen/AArch64/srem-seteq-illegal-types.ll

@@ -0,0 +1,111 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s
+
+define i1 @test_srem_odd(i29 %X) nounwind {
+; CHECK-LABEL: test_srem_odd:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov w9, #33099
+; CHECK-NEXT:    mov w10, #64874
+; CHECK-NEXT:    sbfx w8, w0, #0, #29
+; CHECK-NEXT:    movk w9, #48986, lsl #16
+; CHECK-NEXT:    movk w10, #330, lsl #16
+; CHECK-NEXT:    madd w8, w8, w9, w10
+; CHECK-NEXT:    mov w9, #64213
+; CHECK-NEXT:    movk w9, #661, lsl #16
+; CHECK-NEXT:    cmp w8, w9
+; CHECK-NEXT:    cset w0, lo
+; CHECK-NEXT:    ret
+  %srem = srem i29 %X, 99
+  %cmp = icmp eq i29 %srem, 0
+  ret i1 %cmp
+}
+
+define i1 @test_srem_even(i4 %X) nounwind {
+; CHECK-LABEL: test_srem_even:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov w9, #43691
+; CHECK-NEXT:    sbfx w8, w0, #0, #4
+; CHECK-NEXT:    movk w9, #10922, lsl #16
+; CHECK-NEXT:    smull x9, w8, w9
+; CHECK-NEXT:    lsr x10, x9, #63
+; CHECK-NEXT:    lsr x9, x9, #32
+; CHECK-NEXT:    add w9, w9, w10
+; CHECK-NEXT:    mov w10, #6
+; CHECK-NEXT:    msub w8, w9, w10, w8
+; CHECK-NEXT:    cmp w8, #1 // =1
+; CHECK-NEXT:    cset w0, eq
+; CHECK-NEXT:    ret
+  %srem = srem i4 %X, 6
+  %cmp = icmp eq i4 %srem, 1
+  ret i1 %cmp
+}
+
+define i1 @test_srem_pow2_setne(i6 %X) nounwind {
+; CHECK-LABEL: test_srem_pow2_setne:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    sbfx w8, w0, #0, #6
+; CHECK-NEXT:    ubfx w8, w8, #9, #2
+; CHECK-NEXT:    add w8, w0, w8
+; CHECK-NEXT:    and w8, w8, #0x3c
+; CHECK-NEXT:    sub w8, w0, w8
+; CHECK-NEXT:    tst w8, #0x3f
+; CHECK-NEXT:    cset w0, ne
+; CHECK-NEXT:    ret
+  %srem = srem i6 %X, 4
+  %cmp = icmp ne i6 %srem, 0
+  ret i1 %cmp
+}
+
+define <3 x i1> @test_srem_vec(<3 x i33> %X) nounwind {
+; CHECK-LABEL: test_srem_vec:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov x10, #7281
+; CHECK-NEXT:    movk x10, #29127, lsl #16
+; CHECK-NEXT:    movk x10, #50972, lsl #32
+; CHECK-NEXT:    sbfx x9, x2, #0, #33
+; CHECK-NEXT:    movk x10, #7281, lsl #48
+; CHECK-NEXT:    mov x11, #8589934591
+; CHECK-NEXT:    mov x12, #7282
+; CHECK-NEXT:    movk x12, #29127, lsl #16
+; CHECK-NEXT:    dup v0.2d, x11
+; CHECK-NEXT:    adrp x11, .LCPI3_0
+; CHECK-NEXT:    smulh x10, x9, x10
+; CHECK-NEXT:    movk x12, #50972, lsl #32
+; CHECK-NEXT:    ldr q1, [x11, :lo12:.LCPI3_0]
+; CHECK-NEXT:    adrp x11, .LCPI3_1
+; CHECK-NEXT:    sub x10, x10, x9
+; CHECK-NEXT:    sbfx x8, x1, #0, #33
+; CHECK-NEXT:    movk x12, #7281, lsl #48
+; CHECK-NEXT:    ldr q2, [x11, :lo12:.LCPI3_1]
+; CHECK-NEXT:    asr x11, x10, #3
+; CHECK-NEXT:    add x10, x11, x10, lsr #63
+; CHECK-NEXT:    smulh x11, x8, x12
+; CHECK-NEXT:    add x11, x11, x11, lsr #63
+; CHECK-NEXT:    add x11, x11, x11, lsl #3
+; CHECK-NEXT:    sub x8, x8, x11
+; CHECK-NEXT:    sbfx x11, x0, #0, #33
+; CHECK-NEXT:    smulh x12, x11, x12
+; CHECK-NEXT:    add x12, x12, x12, lsr #63
+; CHECK-NEXT:    add x12, x12, x12, lsl #3
+; CHECK-NEXT:    sub x11, x11, x12
+; CHECK-NEXT:    add x10, x10, x10, lsl #3
+; CHECK-NEXT:    fmov d3, x11
+; CHECK-NEXT:    add x9, x9, x10
+; CHECK-NEXT:    mov v3.d[1], x8
+; CHECK-NEXT:    fmov d4, x9
+; CHECK-NEXT:    and v4.16b, v4.16b, v0.16b
+; CHECK-NEXT:    and v0.16b, v3.16b, v0.16b
+; CHECK-NEXT:    cmeq v0.2d, v0.2d, v1.2d
+; CHECK-NEXT:    cmeq v1.2d, v4.2d, v2.2d
+; CHECK-NEXT:    mvn v0.16b, v0.16b
+; CHECK-NEXT:    mvn v1.16b, v1.16b
+; CHECK-NEXT:    xtn v0.2s, v0.2d
+; CHECK-NEXT:    xtn v1.2s, v1.2d
+; CHECK-NEXT:    mov w1, v0.s[1]
+; CHECK-NEXT:    fmov w0, s0
+; CHECK-NEXT:    fmov w2, s1
+; CHECK-NEXT:    ret
+  %srem = srem <3 x i33> %X, <i33 9, i33 9, i33 -9>
+  %cmp = icmp ne <3 x i33> %srem, <i33 3, i33 -3, i33 3>
+  ret <3 x i1> %cmp
+}

llvm/test/CodeGen/AArch64/urem-seteq-illegal-types.ll

@@ -0,0 +1,117 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s
+
+define i1 @test_urem_odd(i13 %X) nounwind {
+; CHECK-LABEL: test_urem_odd:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov w9, #52429
+; CHECK-NEXT:    and w8, w0, #0x1fff
+; CHECK-NEXT:    movk w9, #52428, lsl #16
+; CHECK-NEXT:    mul w8, w8, w9
+; CHECK-NEXT:    mov w9, #13108
+; CHECK-NEXT:    movk w9, #13107, lsl #16
+; CHECK-NEXT:    cmp w8, w9
+; CHECK-NEXT:    cset w0, lo
+; CHECK-NEXT:    ret
+  %urem = urem i13 %X, 5
+  %cmp = icmp eq i13 %urem, 0
+  ret i1 %cmp
+}
+
+define i1 @test_urem_even(i27 %X) nounwind {
+; CHECK-LABEL: test_urem_even:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov w9, #28087
+; CHECK-NEXT:    and w8, w0, #0x7ffffff
+; CHECK-NEXT:    movk w9, #46811, lsl #16
+; CHECK-NEXT:    mul w8, w8, w9
+; CHECK-NEXT:    mov w9, #9363
+; CHECK-NEXT:    ror w8, w8, #1
+; CHECK-NEXT:    movk w9, #4681, lsl #16
+; CHECK-NEXT:    cmp w8, w9
+; CHECK-NEXT:    cset w0, lo
+; CHECK-NEXT:    ret
+  %urem = urem i27 %X, 14
+  %cmp = icmp eq i27 %urem, 0
+  ret i1 %cmp
+}
+
+define i1 @test_urem_odd_setne(i4 %X) nounwind {
+; CHECK-LABEL: test_urem_odd_setne:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov w9, #52429
+; CHECK-NEXT:    and w8, w0, #0xf
+; CHECK-NEXT:    movk w9, #52428, lsl #16
+; CHECK-NEXT:    mul w8, w8, w9
+; CHECK-NEXT:    mov w9, #858993459
+; CHECK-NEXT:    cmp w8, w9
+; CHECK-NEXT:    cset w0, hi
+; CHECK-NEXT:    ret
+  %urem = urem i4 %X, 5
+  %cmp = icmp ne i4 %urem, 0
+  ret i1 %cmp
+}
+
+define i1 @test_urem_negative_odd(i9 %X) nounwind {
+; CHECK-LABEL: test_urem_negative_odd:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov w9, #57651
+; CHECK-NEXT:    and w8, w0, #0x1ff
+; CHECK-NEXT:    movk w9, #43302, lsl #16
+; CHECK-NEXT:    mul w8, w8, w9
+; CHECK-NEXT:    mov w9, #17191
+; CHECK-NEXT:    movk w9, #129, lsl #16
+; CHECK-NEXT:    cmp w8, w9
+; CHECK-NEXT:    cset w0, hi
+; CHECK-NEXT:    ret
+  %urem = urem i9 %X, -5
+  %cmp = icmp ne i9 %urem, 0
+  ret i1 %cmp
+}
+
+define <3 x i1> @test_urem_vec(<3 x i11> %X) nounwind {
+; CHECK-LABEL: test_urem_vec:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    mov w12, #43691
+; CHECK-NEXT:    and w8, w0, #0x7ff
+; CHECK-NEXT:    movk w12, #43690, lsl #16
+; CHECK-NEXT:    umull x12, w8, w12
+; CHECK-NEXT:    mov w11, #25663
+; CHECK-NEXT:    mov w13, #6
+; CHECK-NEXT:    lsr x12, x12, #34
+; CHECK-NEXT:    and w10, w2, #0x7ff
+; CHECK-NEXT:    movk w11, #160, lsl #16
+; CHECK-NEXT:    msub w8, w12, w13, w8
+; CHECK-NEXT:    mov w12, #18725
+; CHECK-NEXT:    and w9, w1, #0x7ff
+; CHECK-NEXT:    movk w12, #9362, lsl #16
+; CHECK-NEXT:    umull x11, w10, w11
+; CHECK-NEXT:    adrp x13, .LCPI4_0
+; CHECK-NEXT:    umull x12, w9, w12
+; CHECK-NEXT:    lsr x11, x11, #32
+; CHECK-NEXT:    ldr d0, [x13, :lo12:.LCPI4_0]
+; CHECK-NEXT:    lsr x12, x12, #32
+; CHECK-NEXT:    sub w13, w10, w11
+; CHECK-NEXT:    add w11, w11, w13, lsr #1
+; CHECK-NEXT:    sub w13, w9, w12
+; CHECK-NEXT:    add w12, w12, w13, lsr #1
+; CHECK-NEXT:    fmov s1, w8
+; CHECK-NEXT:    mov w8, #2043
+; CHECK-NEXT:    lsr w11, w11, #10
+; CHECK-NEXT:    lsr w12, w12, #2
+; CHECK-NEXT:    msub w8, w11, w8, w10
+; CHECK-NEXT:    sub w10, w12, w12, lsl #3
+; CHECK-NEXT:    add w9, w9, w10
+; CHECK-NEXT:    mov v1.h[1], w9
+; CHECK-NEXT:    mov v1.h[2], w8
+; CHECK-NEXT:    bic v1.4h, #248, lsl #8
+; CHECK-NEXT:    cmeq v0.4h, v1.4h, v0.4h
+; CHECK-NEXT:    mvn v0.8b, v0.8b
+; CHECK-NEXT:    umov w0, v0.h[0]
+; CHECK-NEXT:    umov w1, v0.h[1]
+; CHECK-NEXT:    umov w2, v0.h[2]
+; CHECK-NEXT:    ret
+  %urem = urem <3 x i11> %X, <i11 6, i11 7, i11 -5>
+  %cmp = icmp ne <3 x i11> %urem, <i11 0, i11 1, i11 2>
+  ret <3 x i1> %cmp
+}

llvm/test/CodeGen/AMDGPU/srem-seteq-illegal-types.ll

@@ -0,0 +1,105 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=amdgcn-amd-mesa3d < %s | FileCheck %s
+
+define i1 @test_srem_odd(i29 %X) nounwind {
+; CHECK-LABEL: test_srem_odd:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_bfe_i32 v0, v0, 0, 29
+; CHECK-NEXT:    s_mov_b32 s5, 0xa57eb503
+; CHECK-NEXT:    s_movk_i32 s4, 0x63
+; CHECK-NEXT:    v_mul_hi_i32 v1, v0, s5
+; CHECK-NEXT:    v_add_i32_e32 v1, vcc, v1, v0
+; CHECK-NEXT:    v_lshrrev_b32_e32 v2, 31, v1
+; CHECK-NEXT:    v_ashrrev_i32_e32 v1, 6, v1
+; CHECK-NEXT:    v_add_i32_e32 v1, vcc, v1, v2
+; CHECK-NEXT:    v_mul_lo_u32 v1, v1, s4
+; CHECK-NEXT:    v_sub_i32_e32 v0, vcc, v0, v1
+; CHECK-NEXT:    v_cmp_eq_u32_e32 vcc, 0, v0
+; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc
+; CHECK-NEXT:    s_setpc_b64 s[30:31]
+  %srem = srem i29 %X, 99
+  %cmp = icmp eq i29 %srem, 0
+  ret i1 %cmp
+}
+
+define i1 @test_srem_even(i4 %X) nounwind {
+; CHECK-LABEL: test_srem_even:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_bfe_i32 v0, v0, 0, 4
+; CHECK-NEXT:    s_mov_b32 s4, 0x2aaaaaab
+; CHECK-NEXT:    v_mul_hi_i32 v1, v0, s4
+; CHECK-NEXT:    v_lshrrev_b32_e32 v2, 31, v1
+; CHECK-NEXT:    v_add_i32_e32 v1, vcc, v1, v2
+; CHECK-NEXT:    v_mul_lo_u32 v1, v1, 6
+; CHECK-NEXT:    v_sub_i32_e32 v0, vcc, v0, v1
+; CHECK-NEXT:    v_cmp_eq_u32_e32 vcc, 1, v0
+; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc
+; CHECK-NEXT:    s_setpc_b64 s[30:31]
+  %srem = srem i4 %X, 6
+  %cmp = icmp eq i4 %srem, 1
+  ret i1 %cmp
+}
+
+define i1 @test_srem_pow2_setne(i6 %X) nounwind {
+; CHECK-LABEL: test_srem_pow2_setne:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_bfe_i32 v1, v0, 0, 6
+; CHECK-NEXT:    v_bfe_u32 v1, v1, 9, 2
+; CHECK-NEXT:    v_add_i32_e32 v1, vcc, v0, v1
+; CHECK-NEXT:    v_and_b32_e32 v1, 60, v1
+; CHECK-NEXT:    v_sub_i32_e32 v0, vcc, v0, v1
+; CHECK-NEXT:    v_and_b32_e32 v0, 63, v0
+; CHECK-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v0
+; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc
+; CHECK-NEXT:    s_setpc_b64 s[30:31]
+  %srem = srem i6 %X, 4
+  %cmp = icmp ne i6 %srem, 0
+  ret i1 %cmp
+}
+
+define <3 x i1> @test_srem_vec(<3 x i31> %X) nounwind {
+; CHECK-LABEL: test_srem_vec:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; CHECK-NEXT:    v_bfe_i32 v3, v2, 0, 31
+; CHECK-NEXT:    v_bfe_i32 v4, v1, 0, 31
+; CHECK-NEXT:    v_bfe_i32 v5, v0, 0, 31
+; CHECK-NEXT:    s_mov_b32 s6, 0x38e38e39
+; CHECK-NEXT:    s_mov_b32 s7, 0xc71c71c7
+; CHECK-NEXT:    s_brev_b32 s4, -2
+; CHECK-NEXT:    s_mov_b32 s5, 0x7ffffffd
+; CHECK-NEXT:    v_mul_hi_i32 v5, v5, s6
+; CHECK-NEXT:    v_mul_hi_i32 v4, v4, s6
+; CHECK-NEXT:    v_mul_hi_i32 v3, v3, s7
+; CHECK-NEXT:    v_lshrrev_b32_e32 v6, 31, v5
+; CHECK-NEXT:    v_lshrrev_b32_e32 v5, 1, v5
+; CHECK-NEXT:    v_lshrrev_b32_e32 v7, 31, v4
+; CHECK-NEXT:    v_lshrrev_b32_e32 v4, 1, v4
+; CHECK-NEXT:    v_lshrrev_b32_e32 v8, 31, v3
+; CHECK-NEXT:    v_lshrrev_b32_e32 v3, 1, v3
+; CHECK-NEXT:    v_add_i32_e32 v5, vcc, v5, v6
+; CHECK-NEXT:    v_add_i32_e32 v4, vcc, v4, v7
+; CHECK-NEXT:    v_add_i32_e32 v3, vcc, v3, v8
+; CHECK-NEXT:    v_mul_lo_u32 v5, v5, 9
+; CHECK-NEXT:    v_mul_lo_u32 v4, v4, 9
+; CHECK-NEXT:    v_mul_lo_u32 v3, v3, -9
+; CHECK-NEXT:    v_sub_i32_e32 v0, vcc, v0, v5
+; CHECK-NEXT:    v_sub_i32_e32 v1, vcc, v1, v4
+; CHECK-NEXT:    v_sub_i32_e32 v2, vcc, v2, v3
+; CHECK-NEXT:    v_and_b32_e32 v2, s4, v2
+; CHECK-NEXT:    v_and_b32_e32 v1, s4, v1
+; CHECK-NEXT:    v_and_b32_e32 v0, s4, v0
+; CHECK-NEXT:    v_cmp_ne_u32_e32 vcc, 3, v0
+; CHECK-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc
+; CHECK-NEXT:    v_cmp_ne_u32_e32 vcc, s5, v1
+; CHECK-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc
+; CHECK-NEXT:    v_cmp_ne_u32_e32 vcc, 3, v2
+; CHECK-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc
+; CHECK-NEXT:    s_setpc_b64 s[30:31]
+  %srem = srem <3 x i31> %X, <i31 9, i31 9, i31 -9>
+  %cmp = icmp ne <3 x i31> %srem, <i31 3, i31 -3, i31 3>
+  ret <3 x i1> %cmp
+}