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[RISCV] Allow folding vmerge with implicit passthru when true has tied dest (#78565)
We currently don't fold a vmerge if it has an implicit-def passthru and its true operand also has a passthru (i.e. tied dest). This restriction was added in https://reviews.llvm.org/D151596, back whenever we had separate TU/TA pseudos. It looks like it was added because the policy might not have been handled correctly. However the policy should be set correctly if we relax this restriction today, since we compute the policy differently now that we have removed the TU/TA distinction in our pseudos. We use a TUMU policy, and relax it to TAMU iff the vmerge's passthru is implicit-def. The reasoning behind this being that the tail elements always come from the vmerge's passthru[^1], so if vmerge's passthru is implicit-def then the tail is also implicit-def. So a tail agnostic policy is OK. [^1]: unless the VL was shrunk, but in this case which case we conservatively use TUMU.
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‎llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp‎

Lines changed: 0 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -3749,11 +3749,6 @@ bool RISCVDAGToDAGISel::performCombineVMergeAndVOps(SDNode *N) {
37493749
// If True has a merge operand then it needs to be the same as vmerge's False,
37503750
// since False will be used for the result's merge operand.
37513751
if (HasTiedDest && !isImplicitDef(True->getOperand(0))) {
3752-
// The vmerge instruction must be TU.
3753-
// FIXME: This could be relaxed, but we need to handle the policy for the
3754-
// resulting op correctly.
3755-
if (isImplicitDef(Merge))
3756-
return false;
37573752
SDValue MergeOpTrue = True->getOperand(0);
37583753
if (False != MergeOpTrue)
37593754
return false;
@@ -3763,9 +3758,6 @@ bool RISCVDAGToDAGISel::performCombineVMergeAndVOps(SDNode *N) {
37633758
// going to keep the mask from True.
37643759
if (IsMasked) {
37653760
assert(HasTiedDest && "Expected tied dest");
3766-
// The vmerge instruction must be TU.
3767-
if (isImplicitDef(Merge))
3768-
return false;
37693761
// FIXME: Support mask agnostic True instruction which would have an
37703762
// undef merge operand.
37713763
if (Mask && !usesAllOnesMask(Mask, Glue))

‎llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-vops.ll‎

Lines changed: 34 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1144,3 +1144,37 @@ define <vscale x 2 x double> @vpmerge_vfwsub.w_tied(<vscale x 2 x double> %passt
11441144
%b = call <vscale x 2 x double> @llvm.vp.merge.nxv2f64(<vscale x 2 x i1> %mask, <vscale x 2 x double> %a, <vscale x 2 x double> %passthru, i32 %vl)
11451145
ret <vscale x 2 x double> %b
11461146
}
1147+
1148+
define <vscale x 2 x i32> @true_tied_dest_vmerge_implicit_passthru(<vscale x 2 x i32> %passthru, <vscale x 2 x i32> %x, <vscale x 2 x i32> %y, <vscale x 2 x i1> %m, i64 %avl) {
1149+
; CHECK-LABEL: true_tied_dest_vmerge_implicit_passthru:
1150+
; CHECK: # %bb.0:
1151+
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
1152+
; CHECK-NEXT: vmacc.vv v8, v9, v10, v0.t
1153+
; CHECK-NEXT: ret
1154+
%a = call <vscale x 2 x i32> @llvm.riscv.vmacc.nxv2i32.nxv2i32(<vscale x 2 x i32> %passthru, <vscale x 2 x i32> %x, <vscale x 2 x i32> %y, i64 %avl, i64 0)
1155+
%b = call <vscale x 2 x i32> @llvm.riscv.vmerge.nxv2i32.nxv2i32(
1156+
<vscale x 2 x i32> poison,
1157+
<vscale x 2 x i32> %passthru,
1158+
<vscale x 2 x i32> %a,
1159+
<vscale x 2 x i1> %m,
1160+
i64 %avl
1161+
)
1162+
ret <vscale x 2 x i32> %b
1163+
}
1164+
1165+
define <vscale x 2 x i32> @true_mask_vmerge_implicit_passthru(<vscale x 2 x i32> %passthru, <vscale x 2 x i32> %x, <vscale x 2 x i32> %y, <vscale x 2 x i1> %m, i64 %avl) {
1166+
; CHECK-LABEL: true_mask_vmerge_implicit_passthru:
1167+
; CHECK: # %bb.0:
1168+
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu
1169+
; CHECK-NEXT: vadd.vv v8, v9, v10, v0.t
1170+
; CHECK-NEXT: ret
1171+
%a = call <vscale x 2 x i32> @llvm.riscv.vadd.mask.nxv2i32.nxv2i32(<vscale x 2 x i32> %passthru, <vscale x 2 x i32> %x, <vscale x 2 x i32> %y, <vscale x 2 x i1> %m, i64 %avl, i64 0)
1172+
%b = call <vscale x 2 x i32> @llvm.riscv.vmerge.nxv2i32.nxv2i32(
1173+
<vscale x 2 x i32> poison,
1174+
<vscale x 2 x i32> %passthru,
1175+
<vscale x 2 x i32> %a,
1176+
<vscale x 2 x i1> shufflevector(<vscale x 2 x i1> insertelement(<vscale x 2 x i1> poison, i1 true, i32 0), <vscale x 2 x i1> poison, <vscale x 2 x i32> zeroinitializer),
1177+
i64 %avl
1178+
)
1179+
ret <vscale x 2 x i32> %b
1180+
}

‎llvm/test/CodeGen/RISCV/rvv/vmadd-vp.ll‎

Lines changed: 44 additions & 66 deletions
Original file line numberDiff line numberDiff line change
@@ -81,9 +81,8 @@ define <vscale x 1 x i8> @vmadd_vv_nxv1i8_ta(<vscale x 1 x i8> %a, <vscale x 1 x
8181
define <vscale x 1 x i8> @vmadd_vx_nxv1i8_ta(<vscale x 1 x i8> %a, i8 %b, <vscale x 1 x i8> %c, <vscale x 1 x i1> %m, i32 zeroext %evl) {
8282
; CHECK-LABEL: vmadd_vx_nxv1i8_ta:
8383
; CHECK: # %bb.0:
84-
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma
85-
; CHECK-NEXT: vmacc.vx v9, a0, v8
86-
; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
84+
; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu
85+
; CHECK-NEXT: vmadd.vx v8, a0, v9, v0.t
8786
; CHECK-NEXT: ret
8887
%elt.head = insertelement <vscale x 1 x i8> poison, i8 %b, i32 0
8988
%vb = shufflevector <vscale x 1 x i8> %elt.head, <vscale x 1 x i8> poison, <vscale x 1 x i32> zeroinitializer
@@ -170,9 +169,8 @@ define <vscale x 2 x i8> @vmadd_vv_nxv2i8_ta(<vscale x 2 x i8> %a, <vscale x 2 x
170169
define <vscale x 2 x i8> @vmadd_vx_nxv2i8_ta(<vscale x 2 x i8> %a, i8 %b, <vscale x 2 x i8> %c, <vscale x 2 x i1> %m, i32 zeroext %evl) {
171170
; CHECK-LABEL: vmadd_vx_nxv2i8_ta:
172171
; CHECK: # %bb.0:
173-
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma
174-
; CHECK-NEXT: vmacc.vx v9, a0, v8
175-
; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
172+
; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu
173+
; CHECK-NEXT: vmadd.vx v8, a0, v9, v0.t
176174
; CHECK-NEXT: ret
177175
%elt.head = insertelement <vscale x 2 x i8> poison, i8 %b, i32 0
178176
%vb = shufflevector <vscale x 2 x i8> %elt.head, <vscale x 2 x i8> poison, <vscale x 2 x i32> zeroinitializer
@@ -259,9 +257,8 @@ define <vscale x 4 x i8> @vmadd_vv_nxv4i8_ta(<vscale x 4 x i8> %a, <vscale x 4 x
259257
define <vscale x 4 x i8> @vmadd_vx_nxv4i8_ta(<vscale x 4 x i8> %a, i8 %b, <vscale x 4 x i8> %c, <vscale x 4 x i1> %m, i32 zeroext %evl) {
260258
; CHECK-LABEL: vmadd_vx_nxv4i8_ta:
261259
; CHECK: # %bb.0:
262-
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
263-
; CHECK-NEXT: vmacc.vx v9, a0, v8
264-
; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
260+
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu
261+
; CHECK-NEXT: vmadd.vx v8, a0, v9, v0.t
265262
; CHECK-NEXT: ret
266263
%elt.head = insertelement <vscale x 4 x i8> poison, i8 %b, i32 0
267264
%vb = shufflevector <vscale x 4 x i8> %elt.head, <vscale x 4 x i8> poison, <vscale x 4 x i32> zeroinitializer
@@ -348,9 +345,8 @@ define <vscale x 8 x i8> @vmadd_vv_nxv8i8_ta(<vscale x 8 x i8> %a, <vscale x 8 x
348345
define <vscale x 8 x i8> @vmadd_vx_nxv8i8_ta(<vscale x 8 x i8> %a, i8 %b, <vscale x 8 x i8> %c, <vscale x 8 x i1> %m, i32 zeroext %evl) {
349346
; CHECK-LABEL: vmadd_vx_nxv8i8_ta:
350347
; CHECK: # %bb.0:
351-
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma
352-
; CHECK-NEXT: vmacc.vx v9, a0, v8
353-
; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
348+
; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu
349+
; CHECK-NEXT: vmadd.vx v8, a0, v9, v0.t
354350
; CHECK-NEXT: ret
355351
%elt.head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0
356352
%vb = shufflevector <vscale x 8 x i8> %elt.head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
@@ -437,9 +433,8 @@ define <vscale x 16 x i8> @vmadd_vv_nxv16i8_ta(<vscale x 16 x i8> %a, <vscale x
437433
define <vscale x 16 x i8> @vmadd_vx_nxv16i8_ta(<vscale x 16 x i8> %a, i8 %b, <vscale x 16 x i8> %c, <vscale x 16 x i1> %m, i32 zeroext %evl) {
438434
; CHECK-LABEL: vmadd_vx_nxv16i8_ta:
439435
; CHECK: # %bb.0:
440-
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma
441-
; CHECK-NEXT: vmacc.vx v10, a0, v8
442-
; CHECK-NEXT: vmerge.vvm v8, v8, v10, v0
436+
; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu
437+
; CHECK-NEXT: vmadd.vx v8, a0, v10, v0.t
443438
; CHECK-NEXT: ret
444439
%elt.head = insertelement <vscale x 16 x i8> poison, i8 %b, i32 0
445440
%vb = shufflevector <vscale x 16 x i8> %elt.head, <vscale x 16 x i8> poison, <vscale x 16 x i32> zeroinitializer
@@ -526,9 +521,8 @@ define <vscale x 32 x i8> @vmadd_vv_nxv32i8_ta(<vscale x 32 x i8> %a, <vscale x
526521
define <vscale x 32 x i8> @vmadd_vx_nxv32i8_ta(<vscale x 32 x i8> %a, i8 %b, <vscale x 32 x i8> %c, <vscale x 32 x i1> %m, i32 zeroext %evl) {
527522
; CHECK-LABEL: vmadd_vx_nxv32i8_ta:
528523
; CHECK: # %bb.0:
529-
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma
530-
; CHECK-NEXT: vmacc.vx v12, a0, v8
531-
; CHECK-NEXT: vmerge.vvm v8, v8, v12, v0
524+
; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu
525+
; CHECK-NEXT: vmadd.vx v8, a0, v12, v0.t
532526
; CHECK-NEXT: ret
533527
%elt.head = insertelement <vscale x 32 x i8> poison, i8 %b, i32 0
534528
%vb = shufflevector <vscale x 32 x i8> %elt.head, <vscale x 32 x i8> poison, <vscale x 32 x i32> zeroinitializer
@@ -618,9 +612,8 @@ define <vscale x 64 x i8> @vmadd_vv_nxv64i8_ta(<vscale x 64 x i8> %a, <vscale x
618612
define <vscale x 64 x i8> @vmadd_vx_nxv64i8_ta(<vscale x 64 x i8> %a, i8 %b, <vscale x 64 x i8> %c, <vscale x 64 x i1> %m, i32 zeroext %evl) {
619613
; CHECK-LABEL: vmadd_vx_nxv64i8_ta:
620614
; CHECK: # %bb.0:
621-
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma
622-
; CHECK-NEXT: vmacc.vx v16, a0, v8
623-
; CHECK-NEXT: vmerge.vvm v8, v8, v16, v0
615+
; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu
616+
; CHECK-NEXT: vmadd.vx v8, a0, v16, v0.t
624617
; CHECK-NEXT: ret
625618
%elt.head = insertelement <vscale x 64 x i8> poison, i8 %b, i32 0
626619
%vb = shufflevector <vscale x 64 x i8> %elt.head, <vscale x 64 x i8> poison, <vscale x 64 x i32> zeroinitializer
@@ -707,9 +700,8 @@ define <vscale x 1 x i16> @vmadd_vv_nxv1i16_ta(<vscale x 1 x i16> %a, <vscale x
707700
define <vscale x 1 x i16> @vmadd_vx_nxv1i16_ta(<vscale x 1 x i16> %a, i16 %b, <vscale x 1 x i16> %c, <vscale x 1 x i1> %m, i32 zeroext %evl) {
708701
; CHECK-LABEL: vmadd_vx_nxv1i16_ta:
709702
; CHECK: # %bb.0:
710-
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma
711-
; CHECK-NEXT: vmacc.vx v9, a0, v8
712-
; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
703+
; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu
704+
; CHECK-NEXT: vmadd.vx v8, a0, v9, v0.t
713705
; CHECK-NEXT: ret
714706
%elt.head = insertelement <vscale x 1 x i16> poison, i16 %b, i32 0
715707
%vb = shufflevector <vscale x 1 x i16> %elt.head, <vscale x 1 x i16> poison, <vscale x 1 x i32> zeroinitializer
@@ -796,9 +788,8 @@ define <vscale x 2 x i16> @vmadd_vv_nxv2i16_ta(<vscale x 2 x i16> %a, <vscale x
796788
define <vscale x 2 x i16> @vmadd_vx_nxv2i16_ta(<vscale x 2 x i16> %a, i16 %b, <vscale x 2 x i16> %c, <vscale x 2 x i1> %m, i32 zeroext %evl) {
797789
; CHECK-LABEL: vmadd_vx_nxv2i16_ta:
798790
; CHECK: # %bb.0:
799-
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma
800-
; CHECK-NEXT: vmacc.vx v9, a0, v8
801-
; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
791+
; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu
792+
; CHECK-NEXT: vmadd.vx v8, a0, v9, v0.t
802793
; CHECK-NEXT: ret
803794
%elt.head = insertelement <vscale x 2 x i16> poison, i16 %b, i32 0
804795
%vb = shufflevector <vscale x 2 x i16> %elt.head, <vscale x 2 x i16> poison, <vscale x 2 x i32> zeroinitializer
@@ -885,9 +876,8 @@ define <vscale x 4 x i16> @vmadd_vv_nxv4i16_ta(<vscale x 4 x i16> %a, <vscale x
885876
define <vscale x 4 x i16> @vmadd_vx_nxv4i16_ta(<vscale x 4 x i16> %a, i16 %b, <vscale x 4 x i16> %c, <vscale x 4 x i1> %m, i32 zeroext %evl) {
886877
; CHECK-LABEL: vmadd_vx_nxv4i16_ta:
887878
; CHECK: # %bb.0:
888-
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
889-
; CHECK-NEXT: vmacc.vx v9, a0, v8
890-
; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
879+
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu
880+
; CHECK-NEXT: vmadd.vx v8, a0, v9, v0.t
891881
; CHECK-NEXT: ret
892882
%elt.head = insertelement <vscale x 4 x i16> poison, i16 %b, i32 0
893883
%vb = shufflevector <vscale x 4 x i16> %elt.head, <vscale x 4 x i16> poison, <vscale x 4 x i32> zeroinitializer
@@ -974,9 +964,8 @@ define <vscale x 8 x i16> @vmadd_vv_nxv8i16_ta(<vscale x 8 x i16> %a, <vscale x
974964
define <vscale x 8 x i16> @vmadd_vx_nxv8i16_ta(<vscale x 8 x i16> %a, i16 %b, <vscale x 8 x i16> %c, <vscale x 8 x i1> %m, i32 zeroext %evl) {
975965
; CHECK-LABEL: vmadd_vx_nxv8i16_ta:
976966
; CHECK: # %bb.0:
977-
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma
978-
; CHECK-NEXT: vmacc.vx v10, a0, v8
979-
; CHECK-NEXT: vmerge.vvm v8, v8, v10, v0
967+
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu
968+
; CHECK-NEXT: vmadd.vx v8, a0, v10, v0.t
980969
; CHECK-NEXT: ret
981970
%elt.head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0
982971
%vb = shufflevector <vscale x 8 x i16> %elt.head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
@@ -1063,9 +1052,8 @@ define <vscale x 16 x i16> @vmadd_vv_nxv16i16_ta(<vscale x 16 x i16> %a, <vscale
10631052
define <vscale x 16 x i16> @vmadd_vx_nxv16i16_ta(<vscale x 16 x i16> %a, i16 %b, <vscale x 16 x i16> %c, <vscale x 16 x i1> %m, i32 zeroext %evl) {
10641053
; CHECK-LABEL: vmadd_vx_nxv16i16_ta:
10651054
; CHECK: # %bb.0:
1066-
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma
1067-
; CHECK-NEXT: vmacc.vx v12, a0, v8
1068-
; CHECK-NEXT: vmerge.vvm v8, v8, v12, v0
1055+
; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu
1056+
; CHECK-NEXT: vmadd.vx v8, a0, v12, v0.t
10691057
; CHECK-NEXT: ret
10701058
%elt.head = insertelement <vscale x 16 x i16> poison, i16 %b, i32 0
10711059
%vb = shufflevector <vscale x 16 x i16> %elt.head, <vscale x 16 x i16> poison, <vscale x 16 x i32> zeroinitializer
@@ -1155,9 +1143,8 @@ define <vscale x 32 x i16> @vmadd_vv_nxv32i16_ta(<vscale x 32 x i16> %a, <vscale
11551143
define <vscale x 32 x i16> @vmadd_vx_nxv32i16_ta(<vscale x 32 x i16> %a, i16 %b, <vscale x 32 x i16> %c, <vscale x 32 x i1> %m, i32 zeroext %evl) {
11561144
; CHECK-LABEL: vmadd_vx_nxv32i16_ta:
11571145
; CHECK: # %bb.0:
1158-
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma
1159-
; CHECK-NEXT: vmacc.vx v16, a0, v8
1160-
; CHECK-NEXT: vmerge.vvm v8, v8, v16, v0
1146+
; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu
1147+
; CHECK-NEXT: vmadd.vx v8, a0, v16, v0.t
11611148
; CHECK-NEXT: ret
11621149
%elt.head = insertelement <vscale x 32 x i16> poison, i16 %b, i32 0
11631150
%vb = shufflevector <vscale x 32 x i16> %elt.head, <vscale x 32 x i16> poison, <vscale x 32 x i32> zeroinitializer
@@ -1244,9 +1231,8 @@ define <vscale x 1 x i32> @vmadd_vv_nxv1i32_ta(<vscale x 1 x i32> %a, <vscale x
12441231
define <vscale x 1 x i32> @vmadd_vx_nxv1i32_ta(<vscale x 1 x i32> %a, i32 %b, <vscale x 1 x i32> %c, <vscale x 1 x i1> %m, i32 zeroext %evl) {
12451232
; CHECK-LABEL: vmadd_vx_nxv1i32_ta:
12461233
; CHECK: # %bb.0:
1247-
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma
1248-
; CHECK-NEXT: vmacc.vx v9, a0, v8
1249-
; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
1234+
; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu
1235+
; CHECK-NEXT: vmadd.vx v8, a0, v9, v0.t
12501236
; CHECK-NEXT: ret
12511237
%elt.head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 0
12521238
%vb = shufflevector <vscale x 1 x i32> %elt.head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer
@@ -1333,9 +1319,8 @@ define <vscale x 2 x i32> @vmadd_vv_nxv2i32_ta(<vscale x 2 x i32> %a, <vscale x
13331319
define <vscale x 2 x i32> @vmadd_vx_nxv2i32_ta(<vscale x 2 x i32> %a, i32 %b, <vscale x 2 x i32> %c, <vscale x 2 x i1> %m, i32 zeroext %evl) {
13341320
; CHECK-LABEL: vmadd_vx_nxv2i32_ta:
13351321
; CHECK: # %bb.0:
1336-
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma
1337-
; CHECK-NEXT: vmacc.vx v9, a0, v8
1338-
; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
1322+
; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu
1323+
; CHECK-NEXT: vmadd.vx v8, a0, v9, v0.t
13391324
; CHECK-NEXT: ret
13401325
%elt.head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0
13411326
%vb = shufflevector <vscale x 2 x i32> %elt.head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
@@ -1422,9 +1407,8 @@ define <vscale x 4 x i32> @vmadd_vv_nxv4i32_ta(<vscale x 4 x i32> %a, <vscale x
14221407
define <vscale x 4 x i32> @vmadd_vx_nxv4i32_ta(<vscale x 4 x i32> %a, i32 %b, <vscale x 4 x i32> %c, <vscale x 4 x i1> %m, i32 zeroext %evl) {
14231408
; CHECK-LABEL: vmadd_vx_nxv4i32_ta:
14241409
; CHECK: # %bb.0:
1425-
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma
1426-
; CHECK-NEXT: vmacc.vx v10, a0, v8
1427-
; CHECK-NEXT: vmerge.vvm v8, v8, v10, v0
1410+
; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu
1411+
; CHECK-NEXT: vmadd.vx v8, a0, v10, v0.t
14281412
; CHECK-NEXT: ret
14291413
%elt.head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0
14301414
%vb = shufflevector <vscale x 4 x i32> %elt.head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
@@ -1511,9 +1495,8 @@ define <vscale x 8 x i32> @vmadd_vv_nxv8i32_ta(<vscale x 8 x i32> %a, <vscale x
15111495
define <vscale x 8 x i32> @vmadd_vx_nxv8i32_ta(<vscale x 8 x i32> %a, i32 %b, <vscale x 8 x i32> %c, <vscale x 8 x i1> %m, i32 zeroext %evl) {
15121496
; CHECK-LABEL: vmadd_vx_nxv8i32_ta:
15131497
; CHECK: # %bb.0:
1514-
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma
1515-
; CHECK-NEXT: vmacc.vx v12, a0, v8
1516-
; CHECK-NEXT: vmerge.vvm v8, v8, v12, v0
1498+
; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu
1499+
; CHECK-NEXT: vmadd.vx v8, a0, v12, v0.t
15171500
; CHECK-NEXT: ret
15181501
%elt.head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
15191502
%vb = shufflevector <vscale x 8 x i32> %elt.head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
@@ -1603,9 +1586,8 @@ define <vscale x 16 x i32> @vmadd_vv_nxv16i32_ta(<vscale x 16 x i32> %a, <vscale
16031586
define <vscale x 16 x i32> @vmadd_vx_nxv16i32_ta(<vscale x 16 x i32> %a, i32 %b, <vscale x 16 x i32> %c, <vscale x 16 x i1> %m, i32 zeroext %evl) {
16041587
; CHECK-LABEL: vmadd_vx_nxv16i32_ta:
16051588
; CHECK: # %bb.0:
1606-
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma
1607-
; CHECK-NEXT: vmacc.vx v16, a0, v8
1608-
; CHECK-NEXT: vmerge.vvm v8, v8, v16, v0
1589+
; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu
1590+
; CHECK-NEXT: vmadd.vx v8, a0, v16, v0.t
16091591
; CHECK-NEXT: ret
16101592
%elt.head = insertelement <vscale x 16 x i32> poison, i32 %b, i32 0
16111593
%vb = shufflevector <vscale x 16 x i32> %elt.head, <vscale x 16 x i32> poison, <vscale x 16 x i32> zeroinitializer
@@ -1739,9 +1721,8 @@ define <vscale x 1 x i64> @vmadd_vx_nxv1i64_ta(<vscale x 1 x i64> %a, i64 %b, <v
17391721
;
17401722
; RV64-LABEL: vmadd_vx_nxv1i64_ta:
17411723
; RV64: # %bb.0:
1742-
; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, ma
1743-
; RV64-NEXT: vmacc.vx v9, a0, v8
1744-
; RV64-NEXT: vmerge.vvm v8, v8, v9, v0
1724+
; RV64-NEXT: vsetvli zero, a1, e64, m1, ta, mu
1725+
; RV64-NEXT: vmadd.vx v8, a0, v9, v0.t
17451726
; RV64-NEXT: ret
17461727
%elt.head = insertelement <vscale x 1 x i64> poison, i64 %b, i32 0
17471728
%vb = shufflevector <vscale x 1 x i64> %elt.head, <vscale x 1 x i64> poison, <vscale x 1 x i32> zeroinitializer
@@ -1875,9 +1856,8 @@ define <vscale x 2 x i64> @vmadd_vx_nxv2i64_ta(<vscale x 2 x i64> %a, i64 %b, <v
18751856
;
18761857
; RV64-LABEL: vmadd_vx_nxv2i64_ta:
18771858
; RV64: # %bb.0:
1878-
; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, ma
1879-
; RV64-NEXT: vmacc.vx v10, a0, v8
1880-
; RV64-NEXT: vmerge.vvm v8, v8, v10, v0
1859+
; RV64-NEXT: vsetvli zero, a1, e64, m2, ta, mu
1860+
; RV64-NEXT: vmadd.vx v8, a0, v10, v0.t
18811861
; RV64-NEXT: ret
18821862
%elt.head = insertelement <vscale x 2 x i64> poison, i64 %b, i32 0
18831863
%vb = shufflevector <vscale x 2 x i64> %elt.head, <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
@@ -2011,9 +1991,8 @@ define <vscale x 4 x i64> @vmadd_vx_nxv4i64_ta(<vscale x 4 x i64> %a, i64 %b, <v
20111991
;
20121992
; RV64-LABEL: vmadd_vx_nxv4i64_ta:
20131993
; RV64: # %bb.0:
2014-
; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, ma
2015-
; RV64-NEXT: vmacc.vx v12, a0, v8
2016-
; RV64-NEXT: vmerge.vvm v8, v8, v12, v0
1994+
; RV64-NEXT: vsetvli zero, a1, e64, m4, ta, mu
1995+
; RV64-NEXT: vmadd.vx v8, a0, v12, v0.t
20171996
; RV64-NEXT: ret
20181997
%elt.head = insertelement <vscale x 4 x i64> poison, i64 %b, i32 0
20191998
%vb = shufflevector <vscale x 4 x i64> %elt.head, <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer
@@ -2150,9 +2129,8 @@ define <vscale x 8 x i64> @vmadd_vx_nxv8i64_ta(<vscale x 8 x i64> %a, i64 %b, <v
21502129
;
21512130
; RV64-LABEL: vmadd_vx_nxv8i64_ta:
21522131
; RV64: # %bb.0:
2153-
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, ma
2154-
; RV64-NEXT: vmacc.vx v16, a0, v8
2155-
; RV64-NEXT: vmerge.vvm v8, v8, v16, v0
2132+
; RV64-NEXT: vsetvli zero, a1, e64, m8, ta, mu
2133+
; RV64-NEXT: vmadd.vx v8, a0, v16, v0.t
21562134
; RV64-NEXT: ret
21572135
%elt.head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
21582136
%vb = shufflevector <vscale x 8 x i64> %elt.head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer

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