[X86] Support encoding optimization fo immediate for ndd instructions

Author: XinWang10

llvm/lib/Target/X86/MCTargetDesc/X86EncodingOptimizationForImmediate.def

@@ -69,4 +69,76 @@ ENTRY(IMUL64rri32, IMUL64rri8)
 ENTRY(PUSH16i, PUSH16i8)
 ENTRY(PUSH32i, PUSH32i8)
 ENTRY(PUSH64i32, PUSH64i8)
+ENTRY(ADC16mi_ND, ADC16mi8_ND)
+ENTRY(ADC16ri_ND, ADC16ri8_ND)
+ENTRY(ADC32mi_ND, ADC32mi8_ND)
+ENTRY(ADC32ri_ND, ADC32ri8_ND)
+ENTRY(ADC64mi32_ND, ADC64mi8_ND)
+ENTRY(ADC64ri32_ND, ADC64ri8_ND)
+ENTRY(SBB16mi_ND, SBB16mi8_ND)
+ENTRY(SBB16ri_ND, SBB16ri8_ND)
+ENTRY(SBB32mi_ND, SBB32mi8_ND)
+ENTRY(SBB32ri_ND, SBB32ri8_ND)
+ENTRY(SBB64mi32_ND, SBB64mi8_ND)
+ENTRY(SBB64ri32_ND, SBB64ri8_ND)
+ENTRY(ADD16mi_ND, ADD16mi8_ND)
+ENTRY(ADD16ri_ND, ADD16ri8_ND)
+ENTRY(ADD32mi_ND, ADD32mi8_ND)
+ENTRY(ADD32ri_ND, ADD32ri8_ND)
+ENTRY(ADD64mi32_ND, ADD64mi8_ND)
+ENTRY(ADD64ri32_ND, ADD64ri8_ND)
+ENTRY(AND16mi_ND, AND16mi8_ND)
+ENTRY(AND16ri_ND, AND16ri8_ND)
+ENTRY(AND32mi_ND, AND32mi8_ND)
+ENTRY(AND32ri_ND, AND32ri8_ND)
+ENTRY(AND64mi32_ND, AND64mi8_ND)
+ENTRY(AND64ri32_ND, AND64ri8_ND)
+ENTRY(OR16mi_ND, OR16mi8_ND)
+ENTRY(OR16ri_ND, OR16ri8_ND)
+ENTRY(OR32mi_ND, OR32mi8_ND)
+ENTRY(OR32ri_ND, OR32ri8_ND)
+ENTRY(OR64mi32_ND, OR64mi8_ND)
+ENTRY(OR64ri32_ND, OR64ri8_ND)
+ENTRY(SUB16mi_ND, SUB16mi8_ND)
+ENTRY(SUB16ri_ND, SUB16ri8_ND)
+ENTRY(SUB32mi_ND, SUB32mi8_ND)
+ENTRY(SUB32ri_ND, SUB32ri8_ND)
+ENTRY(SUB64mi32_ND, SUB64mi8_ND)
+ENTRY(SUB64ri32_ND, SUB64ri8_ND)
+ENTRY(XOR16mi_ND, XOR16mi8_ND)
+ENTRY(XOR16ri_ND, XOR16ri8_ND)
+ENTRY(XOR32mi_ND, XOR32mi8_ND)
+ENTRY(XOR32ri_ND, XOR32ri8_ND)
+ENTRY(XOR64mi32_ND, XOR64mi8_ND)
+ENTRY(XOR64ri32_ND, XOR64ri8_ND)
+ENTRY(ADD16mi_NF_ND, ADD16mi8_NF_ND)
+ENTRY(ADD16ri_NF_ND, ADD16ri8_NF_ND)
+ENTRY(ADD32mi_NF_ND, ADD32mi8_NF_ND)
+ENTRY(ADD32ri_NF_ND, ADD32ri8_NF_ND)
+ENTRY(ADD64mi32_NF_ND, ADD64mi8_NF_ND)
+ENTRY(ADD64ri32_NF_ND, ADD64ri8_NF_ND)
+ENTRY(AND16mi_NF_ND, AND16mi8_NF_ND)
+ENTRY(AND16ri_NF_ND, AND16ri8_NF_ND)
+ENTRY(AND32mi_NF_ND, AND32mi8_NF_ND)
+ENTRY(AND32ri_NF_ND, AND32ri8_NF_ND)
+ENTRY(AND64mi32_NF_ND, AND64mi8_NF_ND)
+ENTRY(AND64ri32_NF_ND, AND64ri8_NF_ND)
+ENTRY(OR16mi_NF_ND, OR16mi8_NF_ND)
+ENTRY(OR16ri_NF_ND, OR16ri8_NF_ND)
+ENTRY(OR32mi_NF_ND, OR32mi8_NF_ND)
+ENTRY(OR32ri_NF_ND, OR32ri8_NF_ND)
+ENTRY(OR64mi32_NF_ND, OR64mi8_NF_ND)
+ENTRY(OR64ri32_NF_ND, OR64ri8_NF_ND)
+ENTRY(SUB16mi_NF_ND, SUB16mi8_NF_ND)
+ENTRY(SUB16ri_NF_ND, SUB16ri8_NF_ND)
+ENTRY(SUB32mi_NF_ND, SUB32mi8_NF_ND)
+ENTRY(SUB32ri_NF_ND, SUB32ri8_NF_ND)
+ENTRY(SUB64mi32_NF_ND, SUB64mi8_NF_ND)
+ENTRY(SUB64ri32_NF_ND, SUB64ri8_NF_ND)
+ENTRY(XOR16mi_NF_ND, XOR16mi8_NF_ND)
+ENTRY(XOR16ri_NF_ND, XOR16ri8_NF_ND)
+ENTRY(XOR32mi_NF_ND, XOR32mi8_NF_ND)
+ENTRY(XOR32ri_NF_ND, XOR32ri8_NF_ND)
+ENTRY(XOR64mi32_NF_ND, XOR64mi8_NF_ND)
+ENTRY(XOR64ri32_NF_ND, XOR64ri8_NF_ND)
 #undef ENTRY

llvm/test/CodeGen/X86/apx/adc.ll

@@ -112,8 +112,8 @@ define i64 @adc64rm(i64 %a, ptr %ptr, i64 %x, i64 %y) nounwind {
 define i16 @adc16ri8(i16 %a, i16 %x, i16 %y) nounwind {
 ; CHECK-LABEL: adc16ri8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    cmpw %si, %dx # encoding: [0x66,0x39,0xf2]
-; CHECK-NEXT:    adcw $0, %di, %ax # encoding: [0x62,0xf4,0x7d,0x18,0x81,0xd7,0x00,0x00]
+; CHECK-NEXT:    subw %si, %dx, %ax # encoding: [0x62,0xf4,0x7d,0x18,0x29,0xf2]
+; CHECK-NEXT:    adcw $0, %di, %ax # encoding: [0x62,0xf4,0x7d,0x18,0x83,0xd7,0x00]
 ; CHECK-NEXT:    addl $123, %eax # EVEX TO LEGACY Compression encoding: [0x83,0xc0,0x7b]
 ; CHECK-NEXT:    # kill: def $ax killed $ax killed $eax
 ; CHECK-NEXT:    retq # encoding: [0xc3]
@@ -127,8 +127,8 @@ define i16 @adc16ri8(i16 %a, i16 %x, i16 %y) nounwind {
 define i32 @adc32ri8(i32 %a, i32 %x, i32 %y) nounwind {
 ; CHECK-LABEL: adc32ri8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    cmpl %esi, %edx # encoding: [0x39,0xf2]
-; CHECK-NEXT:    adcl $123, %edi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x81,0xd7,0x7b,0x00,0x00,0x00]
+; CHECK-NEXT:    subl %esi, %edx, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x29,0xf2]
+; CHECK-NEXT:    adcl $123, %edi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x83,0xd7,0x7b]
 ; CHECK-NEXT:    retq # encoding: [0xc3]
   %s = add i32 %a, 123
   %k = icmp ugt i32 %x, %y
@@ -140,8 +140,8 @@ define i32 @adc32ri8(i32 %a, i32 %x, i32 %y) nounwind {
 define i64 @adc64ri8(i64 %a, i64 %x, i64 %y) nounwind {
 ; CHECK-LABEL: adc64ri8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    cmpq %rsi, %rdx # encoding: [0x48,0x39,0xf2]
-; CHECK-NEXT:    adcq $123, %rdi, %rax # encoding: [0x62,0xf4,0xfc,0x18,0x81,0xd7,0x7b,0x00,0x00,0x00]
+; CHECK-NEXT:    subq %rsi, %rdx, %rax # encoding: [0x62,0xf4,0xfc,0x18,0x29,0xf2]
+; CHECK-NEXT:    adcq $123, %rdi, %rax # encoding: [0x62,0xf4,0xfc,0x18,0x83,0xd7,0x7b]
 ; CHECK-NEXT:    retq # encoding: [0xc3]
   %s = add i64 %a, 123
   %k = icmp ugt i64 %x, %y
@@ -166,8 +166,8 @@ define i8 @adc8ri(i8 %a, i8 %x, i8 %y) nounwind {
 define i16 @adc16ri(i16 %a, i16 %x, i16 %y) nounwind {
 ; CHECK-LABEL: adc16ri:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    cmpw %si, %dx # encoding: [0x66,0x39,0xf2]
-; CHECK-NEXT:    adcw $0, %di, %ax # encoding: [0x62,0xf4,0x7d,0x18,0x81,0xd7,0x00,0x00]
+; CHECK-NEXT:    subw %si, %dx, %ax # encoding: [0x62,0xf4,0x7d,0x18,0x29,0xf2]
+; CHECK-NEXT:    adcw $0, %di, %ax # encoding: [0x62,0xf4,0x7d,0x18,0x83,0xd7,0x00]
 ; CHECK-NEXT:    addl $1234, %eax # EVEX TO LEGACY Compression encoding: [0x05,0xd2,0x04,0x00,0x00]
 ; CHECK-NEXT:    # imm = 0x4D2
 ; CHECK-NEXT:    # kill: def $ax killed $ax killed $eax
@@ -266,8 +266,8 @@ define i64 @adc64mr(i64 %a, ptr %ptr, i64 %x, i64 %y) nounwind {
 define i16 @adc16mi8(ptr %ptr, i16 %x, i16 %y) nounwind {
 ; CHECK-LABEL: adc16mi8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    cmpw %si, %dx # encoding: [0x66,0x39,0xf2]
-; CHECK-NEXT:    adcw $0, (%rdi), %ax # encoding: [0x62,0xf4,0x7d,0x18,0x81,0x17,0x00,0x00]
+; CHECK-NEXT:    subw %si, %dx, %ax # encoding: [0x62,0xf4,0x7d,0x18,0x29,0xf2]
+; CHECK-NEXT:    adcw $0, (%rdi), %ax # encoding: [0x62,0xf4,0x7d,0x18,0x83,0x17,0x00]
 ; CHECK-NEXT:    addl $123, %eax # EVEX TO LEGACY Compression encoding: [0x83,0xc0,0x7b]
 ; CHECK-NEXT:    # kill: def $ax killed $ax killed $eax
 ; CHECK-NEXT:    retq # encoding: [0xc3]
@@ -282,8 +282,8 @@ define i16 @adc16mi8(ptr %ptr, i16 %x, i16 %y) nounwind {
 define i32 @adc32mi8(ptr %ptr, i32 %x, i32 %y) nounwind {
 ; CHECK-LABEL: adc32mi8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    cmpl %esi, %edx # encoding: [0x39,0xf2]
-; CHECK-NEXT:    adcl $123, (%rdi), %eax # encoding: [0x62,0xf4,0x7c,0x18,0x81,0x17,0x7b,0x00,0x00,0x00]
+; CHECK-NEXT:    subl %esi, %edx, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x29,0xf2]
+; CHECK-NEXT:    adcl $123, (%rdi), %eax # encoding: [0x62,0xf4,0x7c,0x18,0x83,0x17,0x7b]
 ; CHECK-NEXT:    retq # encoding: [0xc3]
   %a = load i32, ptr %ptr
   %s = add i32 %a, 123
@@ -296,8 +296,8 @@ define i32 @adc32mi8(ptr %ptr, i32 %x, i32 %y) nounwind {
 define i64 @adc64mi8(ptr %ptr, i64 %x, i64 %y) nounwind {
 ; CHECK-LABEL: adc64mi8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    cmpq %rsi, %rdx # encoding: [0x48,0x39,0xf2]
-; CHECK-NEXT:    adcq $123, (%rdi), %rax # encoding: [0x62,0xf4,0xfc,0x18,0x81,0x17,0x7b,0x00,0x00,0x00]
+; CHECK-NEXT:    subq %rsi, %rdx, %rax # encoding: [0x62,0xf4,0xfc,0x18,0x29,0xf2]
+; CHECK-NEXT:    adcq $123, (%rdi), %rax # encoding: [0x62,0xf4,0xfc,0x18,0x83,0x17,0x7b]
 ; CHECK-NEXT:    retq # encoding: [0xc3]
   %a = load i64, ptr %ptr
   %s = add i64 %a, 123
@@ -324,8 +324,8 @@ define i8 @adc8mi(ptr %ptr, i8 %x, i8 %y) nounwind {
 define i16 @adc16mi(ptr %ptr, i16 %x, i16 %y) nounwind {
 ; CHECK-LABEL: adc16mi:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    cmpw %si, %dx # encoding: [0x66,0x39,0xf2]
-; CHECK-NEXT:    adcw $0, (%rdi), %ax # encoding: [0x62,0xf4,0x7d,0x18,0x81,0x17,0x00,0x00]
+; CHECK-NEXT:    subw %si, %dx, %ax # encoding: [0x62,0xf4,0x7d,0x18,0x29,0xf2]
+; CHECK-NEXT:    adcw $0, (%rdi), %ax # encoding: [0x62,0xf4,0x7d,0x18,0x83,0x17,0x00]
 ; CHECK-NEXT:    addl $1234, %eax # EVEX TO LEGACY Compression encoding: [0x05,0xd2,0x04,0x00,0x00]
 ; CHECK-NEXT:    # imm = 0x4D2
 ; CHECK-NEXT:    # kill: def $ax killed $ax killed $eax
@@ -446,8 +446,8 @@ define void @adc8mi_legacy(ptr %ptr, i8 %x, i8 %y) nounwind {
 define void @adc16mi_legacy(ptr %ptr, i16 %x, i16 %y) nounwind {
 ; CHECK-LABEL: adc16mi_legacy:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    cmpw %si, %dx # encoding: [0x66,0x39,0xf2]
-; CHECK-NEXT:    adcw $0, (%rdi), %ax # encoding: [0x62,0xf4,0x7d,0x18,0x81,0x17,0x00,0x00]
+; CHECK-NEXT:    subw %si, %dx, %ax # encoding: [0x62,0xf4,0x7d,0x18,0x29,0xf2]
+; CHECK-NEXT:    adcw $0, (%rdi), %ax # encoding: [0x62,0xf4,0x7d,0x18,0x83,0x17,0x00]
 ; CHECK-NEXT:    addl $1234, %eax # EVEX TO LEGACY Compression encoding: [0x05,0xd2,0x04,0x00,0x00]
 ; CHECK-NEXT:    # imm = 0x4D2
 ; CHECK-NEXT:    movw %ax, (%rdi) # encoding: [0x66,0x89,0x07]

llvm/test/CodeGen/X86/apx/add.ll

@@ -89,7 +89,7 @@ entry:
 define i16 @add16ri8(i16 noundef %a) {
 ; CHECK-LABEL: add16ri8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    addl $123, %edi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x81,0xc7,0x7b,0x00,0x00,0x00]
+; CHECK-NEXT:    addl $123, %edi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x83,0xc7,0x7b]
 ; CHECK-NEXT:    # kill: def $ax killed $ax killed $eax
 ; CHECK-NEXT:    retq # encoding: [0xc3]
 entry:
@@ -100,7 +100,7 @@ entry:
 define i32 @add32ri8(i32 noundef %a) {
 ; CHECK-LABEL: add32ri8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    addl $123, %edi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x81,0xc7,0x7b,0x00,0x00,0x00]
+; CHECK-NEXT:    addl $123, %edi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x83,0xc7,0x7b]
 ; CHECK-NEXT:    retq # encoding: [0xc3]
 entry:
     %add = add i32 %a, 123
@@ -110,7 +110,7 @@ entry:
 define i64 @add64ri8(i64 noundef %a) {
 ; CHECK-LABEL: add64ri8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    addq $123, %rdi, %rax # encoding: [0x62,0xf4,0xfc,0x18,0x81,0xc7,0x7b,0x00,0x00,0x00]
+; CHECK-NEXT:    addq $123, %rdi, %rax # encoding: [0x62,0xf4,0xfc,0x18,0x83,0xc7,0x7b]
 ; CHECK-NEXT:    retq # encoding: [0xc3]
 entry:
     %add = add i64 %a, 123
@@ -221,7 +221,7 @@ entry:
 define i32 @add32mi8(ptr %a) {
 ; CHECK-LABEL: add32mi8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    addl $123, (%rdi), %eax # encoding: [0x62,0xf4,0x7c,0x18,0x81,0x07,0x7b,0x00,0x00,0x00]
+; CHECK-NEXT:    addl $123, (%rdi), %eax # encoding: [0x62,0xf4,0x7c,0x18,0x83,0x07,0x7b]
 ; CHECK-NEXT:    retq # encoding: [0xc3]
 entry:
   %t= load i32, ptr %a
@@ -232,7 +232,7 @@ entry:
 define i64 @add64mi8(ptr %a) {
 ; CHECK-LABEL: add64mi8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    addq $123, (%rdi), %rax # encoding: [0x62,0xf4,0xfc,0x18,0x81,0x07,0x7b,0x00,0x00,0x00]
+; CHECK-NEXT:    addq $123, (%rdi), %rax # encoding: [0x62,0xf4,0xfc,0x18,0x83,0x07,0x7b]
 ; CHECK-NEXT:    retq # encoding: [0xc3]
 entry:
   %t= load i64, ptr %a
@@ -405,7 +405,7 @@ entry:
 define i16 @addflag16ri8(i16 noundef %a) {
 ; CHECK-LABEL: addflag16ri8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    addw $123, %di, %cx # encoding: [0x62,0xf4,0x75,0x18,0x81,0xc7,0x7b,0x00]
+; CHECK-NEXT:    addw $123, %di, %cx # encoding: [0x62,0xf4,0x75,0x18,0x83,0xc7,0x7b]
 ; CHECK-NEXT:    movl $65535, %eax # encoding: [0xb8,0xff,0xff,0x00,0x00]
 ; CHECK-NEXT:    # imm = 0xFFFF
 ; CHECK-NEXT:    cmovael %ecx, %eax # encoding: [0x0f,0x43,0xc1]
@@ -419,7 +419,7 @@ entry:
 define i32 @addflag32ri8(i32 noundef %a) {
 ; CHECK-LABEL: addflag32ri8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    addl $123, %edi, %ecx # encoding: [0x62,0xf4,0x74,0x18,0x81,0xc7,0x7b,0x00,0x00,0x00]
+; CHECK-NEXT:    addl $123, %edi, %ecx # encoding: [0x62,0xf4,0x74,0x18,0x83,0xc7,0x7b]
 ; CHECK-NEXT:    movl $-1, %eax # encoding: [0xb8,0xff,0xff,0xff,0xff]
 ; CHECK-NEXT:    cmovael %ecx, %eax # encoding: [0x0f,0x43,0xc1]
 ; CHECK-NEXT:    retq # encoding: [0xc3]
@@ -431,7 +431,7 @@ entry:
 define i64 @addflag64ri8(i64 noundef %a) {
 ; CHECK-LABEL: addflag64ri8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    addq $123, %rdi, %rcx # encoding: [0x62,0xf4,0xf4,0x18,0x81,0xc7,0x7b,0x00,0x00,0x00]
+; CHECK-NEXT:    addq $123, %rdi, %rcx # encoding: [0x62,0xf4,0xf4,0x18,0x83,0xc7,0x7b]
 ; CHECK-NEXT:    movq $-1, %rax # encoding: [0x48,0xc7,0xc0,0xff,0xff,0xff,0xff]
 ; CHECK-NEXT:    cmovaeq %rcx, %rax # encoding: [0x48,0x0f,0x43,0xc1]
 ; CHECK-NEXT:    retq # encoding: [0xc3]

llvm/test/CodeGen/X86/apx/and.ll

@@ -90,7 +90,7 @@ entry:
 define i16 @and16ri8(i16 noundef %a) {
 ; CHECK-LABEL: and16ri8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    andl $123, %edi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x81,0xe7,0x7b,0x00,0x00,0x00]
+; CHECK-NEXT:    andl $123, %edi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x83,0xe7,0x7b]
 ; CHECK-NEXT:    # kill: def $ax killed $ax killed $eax
 ; CHECK-NEXT:    retq # encoding: [0xc3]
 entry:
@@ -101,7 +101,7 @@ entry:
 define i32 @and32ri8(i32 noundef %a) {
 ; CHECK-LABEL: and32ri8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    andl $123, %edi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x81,0xe7,0x7b,0x00,0x00,0x00]
+; CHECK-NEXT:    andl $123, %edi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x83,0xe7,0x7b]
 ; CHECK-NEXT:    retq # encoding: [0xc3]
 entry:
     %and = and i32 %a, 123
@@ -111,7 +111,7 @@ entry:
 define i64 @and64ri8(i64 noundef %a) {
 ; CHECK-LABEL: and64ri8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    andl $123, %edi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x81,0xe7,0x7b,0x00,0x00,0x00]
+; CHECK-NEXT:    andl $123, %edi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x83,0xe7,0x7b]
 ; CHECK-NEXT:    retq # encoding: [0xc3]
 entry:
     %and = and i64 %a, 123
@@ -222,7 +222,7 @@ entry:
 define i32 @and32mi8(ptr %a) {
 ; CHECK-LABEL: and32mi8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    andl $123, (%rdi), %eax # encoding: [0x62,0xf4,0x7c,0x18,0x81,0x27,0x7b,0x00,0x00,0x00]
+; CHECK-NEXT:    andl $123, (%rdi), %eax # encoding: [0x62,0xf4,0x7c,0x18,0x83,0x27,0x7b]
 ; CHECK-NEXT:    retq # encoding: [0xc3]
 entry:
   %t= load i32, ptr %a
@@ -482,7 +482,7 @@ define i1 @andflag64ri(i64 %a) {
 define i1 @andflag16ri8(i16 %a) {
 ; CHECK-LABEL: andflag16ri8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    andw $-124, %di, %cx # encoding: [0x62,0xf4,0x75,0x18,0x81,0xe7,0x84,0xff]
+; CHECK-NEXT:    andw $-124, %di, %cx # encoding: [0x62,0xf4,0x75,0x18,0x83,0xe7,0x84]
 ; CHECK-NEXT:    sete %al # encoding: [0x0f,0x94,0xc0]
 ; CHECK-NEXT:    movw %cx, d64(%rip) # encoding: [0x66,0x89,0x0d,A,A,A,A]
 ; CHECK-NEXT:    # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
@@ -497,7 +497,7 @@ define i1 @andflag16ri8(i16 %a) {
 define i1 @andflag32ri8(i32 %a) {
 ; CHECK-LABEL: andflag32ri8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    andl $123, %edi, %ecx # encoding: [0x62,0xf4,0x74,0x18,0x81,0xe7,0x7b,0x00,0x00,0x00]
+; CHECK-NEXT:    andl $123, %edi, %ecx # encoding: [0x62,0xf4,0x74,0x18,0x83,0xe7,0x7b]
 ; CHECK-NEXT:    sete %al # encoding: [0x0f,0x94,0xc0]
 ; CHECK-NEXT:    movl %ecx, d64(%rip) # encoding: [0x89,0x0d,A,A,A,A]
 ; CHECK-NEXT:    # fixup A - offset: 2, value: d64-4, kind: reloc_riprel_4byte
@@ -511,7 +511,7 @@ define i1 @andflag32ri8(i32 %a) {
 define i1 @andflag64ri8(i64 %a) {
 ; CHECK-LABEL: andflag64ri8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    andq $123, %rdi, %rcx # encoding: [0x62,0xf4,0xf4,0x18,0x81,0xe7,0x7b,0x00,0x00,0x00]
+; CHECK-NEXT:    andq $123, %rdi, %rcx # encoding: [0x62,0xf4,0xf4,0x18,0x83,0xe7,0x7b]
 ; CHECK-NEXT:    sete %al # encoding: [0x0f,0x94,0xc0]
 ; CHECK-NEXT:    movq %rcx, d64(%rip) # encoding: [0x48,0x89,0x0d,A,A,A,A]
 ; CHECK-NEXT:    # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte

llvm/test/CodeGen/X86/apx/or.ll

@@ -90,7 +90,7 @@ entry:
 define i16 @or16ri8(i16 noundef %a) {
 ; CHECK-LABEL: or16ri8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    orl $123, %edi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x81,0xcf,0x7b,0x00,0x00,0x00]
+; CHECK-NEXT:    orl $123, %edi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x83,0xcf,0x7b]
 ; CHECK-NEXT:    # kill: def $ax killed $ax killed $eax
 ; CHECK-NEXT:    retq # encoding: [0xc3]
 entry:
@@ -101,7 +101,7 @@ entry:
 define i32 @or32ri8(i32 noundef %a) {
 ; CHECK-LABEL: or32ri8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    orl $123, %edi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x81,0xcf,0x7b,0x00,0x00,0x00]
+; CHECK-NEXT:    orl $123, %edi, %eax # encoding: [0x62,0xf4,0x7c,0x18,0x83,0xcf,0x7b]
 ; CHECK-NEXT:    retq # encoding: [0xc3]
 entry:
     %or = or i32 %a, 123
@@ -111,7 +111,7 @@ entry:
 define i64 @or64ri8(i64 noundef %a) {
 ; CHECK-LABEL: or64ri8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    orq $123, %rdi, %rax # encoding: [0x62,0xf4,0xfc,0x18,0x81,0xcf,0x7b,0x00,0x00,0x00]
+; CHECK-NEXT:    orq $123, %rdi, %rax # encoding: [0x62,0xf4,0xfc,0x18,0x83,0xcf,0x7b]
 ; CHECK-NEXT:    retq # encoding: [0xc3]
 entry:
     %or = or i64 %a, 123
@@ -222,7 +222,7 @@ entry:
 define i32 @or32mi8(ptr %a) {
 ; CHECK-LABEL: or32mi8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    orl $123, (%rdi), %eax # encoding: [0x62,0xf4,0x7c,0x18,0x81,0x0f,0x7b,0x00,0x00,0x00]
+; CHECK-NEXT:    orl $123, (%rdi), %eax # encoding: [0x62,0xf4,0x7c,0x18,0x83,0x0f,0x7b]
 ; CHECK-NEXT:    retq # encoding: [0xc3]
 entry:
   %t= load i32, ptr %a
@@ -233,7 +233,7 @@ entry:
 define i64 @or64mi8(ptr %a) {
 ; CHECK-LABEL: or64mi8:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    orq $123, (%rdi), %rax # encoding: [0x62,0xf4,0xfc,0x18,0x81,0x0f,0x7b,0x00,0x00,0x00]
+; CHECK-NEXT:    orq $123, (%rdi), %rax # encoding: [0x62,0xf4,0xfc,0x18,0x83,0x0f,0x7b]
 ; CHECK-NEXT:    retq # encoding: [0xc3]
 entry:
   %t= load i64, ptr %a
@@ -480,7 +480,7 @@ define i1 @orflag64ri(i64 %a) {
 define i1 @orflag16ri8(i16 %a) {
 ; CHECK-LABEL: orflag16ri8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    orw $-124, %di, %cx # encoding: [0x62,0xf4,0x75,0x18,0x81,0xcf,0x84,0xff]
+; CHECK-NEXT:    orw $-124, %di, %cx # encoding: [0x62,0xf4,0x75,0x18,0x83,0xcf,0x84]
 ; CHECK-NEXT:    sete %al # encoding: [0x0f,0x94,0xc0]
 ; CHECK-NEXT:    movw %cx, d64(%rip) # encoding: [0x66,0x89,0x0d,A,A,A,A]
 ; CHECK-NEXT:    # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte
@@ -495,7 +495,7 @@ define i1 @orflag16ri8(i16 %a) {
 define i1 @orflag32ri8(i32 %a) {
 ; CHECK-LABEL: orflag32ri8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    orl $123, %edi, %ecx # encoding: [0x62,0xf4,0x74,0x18,0x81,0xcf,0x7b,0x00,0x00,0x00]
+; CHECK-NEXT:    orl $123, %edi, %ecx # encoding: [0x62,0xf4,0x74,0x18,0x83,0xcf,0x7b]
 ; CHECK-NEXT:    sete %al # encoding: [0x0f,0x94,0xc0]
 ; CHECK-NEXT:    movl %ecx, d64(%rip) # encoding: [0x89,0x0d,A,A,A,A]
 ; CHECK-NEXT:    # fixup A - offset: 2, value: d64-4, kind: reloc_riprel_4byte
@@ -509,7 +509,7 @@ define i1 @orflag32ri8(i32 %a) {
 define i1 @orflag64ri8(i64 %a) {
 ; CHECK-LABEL: orflag64ri8:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    orq $123, %rdi, %rcx # encoding: [0x62,0xf4,0xf4,0x18,0x81,0xcf,0x7b,0x00,0x00,0x00]
+; CHECK-NEXT:    orq $123, %rdi, %rcx # encoding: [0x62,0xf4,0xf4,0x18,0x83,0xcf,0x7b]
 ; CHECK-NEXT:    sete %al # encoding: [0x0f,0x94,0xc0]
 ; CHECK-NEXT:    movq %rcx, d64(%rip) # encoding: [0x48,0x89,0x0d,A,A,A,A]
 ; CHECK-NEXT:    # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte