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[AMDGPU][True16][MC] Support v_swap_b16. (#100442)
support V_SWAP_B16 true16 encoding in asm/disasm for GFX11/12 Co-authored-by: guochen2 <guochen2@amd.com>
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‎llvm/lib/Target/AMDGPU/SIInstrFormats.td‎

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Original file line numberDiff line numberDiff line change
@@ -321,6 +321,12 @@ def VOPDstOperand_t16Lo128 : VOPDstOperand <VGPR_16_Lo128> {
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let DecoderMethod = "DecodeVGPR_16_Lo128RegisterClass";
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}
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// Source-encoded destination operand for instructions like v_swap_b16.
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def VOPSrcEncodedDstOperand_t16Lo128 : VOPDstOperand <VGPR_16_Lo128> {
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let EncoderMethod = VSrcT_b16_Lo128.EncoderMethod;
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let DecoderMethod = VSrcT_b16_Lo128.DecoderMethod;
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}
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class VINTRPe <bits<2> op> : Enc32 {
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bits<8> vdst;
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bits<8> vsrc;

‎llvm/lib/Target/AMDGPU/VOP1Instructions.td‎

Lines changed: 16 additions & 1 deletion
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@@ -730,7 +730,21 @@ def V_ACCVGPR_MOV_B32 : VOP1_Pseudo<"v_accvgpr_mov_b32", VOPProfileAccMov, [], 1
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let isAsCheapAsAMove = 1;
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}
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def VOP_SWAP_I16 : VOPProfile_True16<VOP_I16_I16> {
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let Outs32 = (outs VOPDstOperand_t16Lo128:$vdst,
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VOPSrcEncodedDstOperand_t16Lo128:$vdst1);
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let Ins32 = (ins VOPSrcEncodedDstOperand_t16Lo128:$src0,
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VOPDstOperand_t16Lo128:$src1);
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let Asm32 = " $vdst, $src0";
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}
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let SubtargetPredicate = isGFX11Plus in {
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def V_SWAP_B16 : VOP1_Pseudo<"v_swap_b16", VOP_SWAP_I16, [], /* VOP1Only= */true> {
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let Constraints = "$vdst = $src1, $vdst1 = $src0";
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let DisableEncoding = "$vdst1, $src1";
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let SchedRW = [Write64Bit, Write64Bit];
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let True16Predicate = UseRealTrue16Insts;
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}
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// Restrict src0 to be VGPR
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def V_PERMLANE64_B32 : VOP1_Pseudo<"v_permlane64_b32", VOP_MOVRELS,
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[], /*VOP1Only=*/ 1> {
@@ -953,7 +967,8 @@ defm V_CTZ_I32_B32 : VOP1_Real_FULL_with_name_gfx11_gfx12<0x03a,
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"V_FFBL_B32", "v_ctz_i32_b32">;
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defm V_CLS_I32 : VOP1_Real_FULL_with_name_gfx11_gfx12<0x03b,
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"V_FFBH_I32", "v_cls_i32">;
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defm V_PERMLANE64_B32 : VOP1Only_Real_gfx11_gfx12<0x067>;
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defm V_SWAP_B16 : VOP1Only_Real_gfx11_gfx12<0x066>;
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defm V_PERMLANE64_B32 : VOP1Only_Real_gfx11_gfx12<0x067>;
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defm V_MOV_B16_t16 : VOP1_Real_FULL_t16_gfx11_gfx12<0x01c, "v_mov_b16">;
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defm V_NOT_B16_fake16 : VOP1_Real_FULL_t16_gfx11_gfx12<0x069, "v_not_b16">;
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defm V_CVT_I32_I16_fake16 : VOP1_Real_FULL_t16_gfx11_gfx12<0x06a, "v_cvt_i32_i16">;

‎llvm/test/MC/AMDGPU/gfx10_unsupported.s‎

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Original file line numberDiff line numberDiff line change
@@ -3287,6 +3287,9 @@ v_subrev_u32_e64 v255, s[12:13], v1, v2
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v_subrev_u32_sdwa v1, vcc, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:BYTE_2
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// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
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v_swap_b16 v0.l, v0.l
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// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
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v_wmma_bf16_16x16x16_bf16 v[16:19], 1.0, v[8:15], v[16:19]
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// CHECK: :[[@LINE-1]]:{{[0-9]+}}: error: instruction not supported on this GPU
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‎llvm/test/MC/AMDGPU/gfx11_asm_vop1.s‎

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Original file line numberDiff line numberDiff line change
@@ -3448,6 +3448,15 @@ v_sqrt_f64 v[5:6], src_scc
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v_sqrt_f64 v[254:255], 0xaf123456
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// GFX11: encoding: [0xff,0x68,0xfc,0x7f,0x56,0x34,0x12,0xaf]
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v_swap_b16 v5.l, v1.h
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// GFX11: encoding: [0x81,0xcd,0x0a,0x7e]
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v_swap_b16 v5.h, v1.l
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// GFX11: encoding: [0x01,0xcd,0x0a,0x7f]
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v_swap_b16 v127.l, v127.l
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// GFX11: encoding: [0x7f,0xcd,0xfe,0x7e]
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v_swap_b32 v5, v1
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// GFX11: encoding: [0x01,0xcb,0x0a,0x7e]
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‎llvm/test/MC/AMDGPU/gfx11_asm_vop1_t16_err.s‎

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Original file line numberDiff line numberDiff line change
@@ -211,6 +211,18 @@ v_sqrt_f16_e32 v255.l, v1.l
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v_sqrt_f16_e32 v5.l, v199.l
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// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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v_swap_b16_e32 v128.l, v0.l
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// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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v_swap_b16_e32 v0.l, s0
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// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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v_swap_b16_e32 v0.l, 0
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// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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v_swap_b16_e32 v0.l, 0xfe0b
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// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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v_trunc_f16_e32 v128, 0xfe0b
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// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
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‎llvm/test/MC/AMDGPU/gfx12_asm_vop1.s‎

Lines changed: 9 additions & 0 deletions
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@@ -3460,6 +3460,15 @@ v_sqrt_f64 v[5:6], src_scc
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v_sqrt_f64 v[254:255], 0xaf123456
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// GFX12: v_sqrt_f64_e32 v[254:255], 0xaf123456 ; encoding: [0xff,0x68,0xfc,0x7f,0x56,0x34,0x12,0xaf]
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v_swap_b16 v5.l, v1.h
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// GFX12: v_swap_b16 v5.l, v1.h ; encoding: [0x81,0xcd,0x0a,0x7e]
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v_swap_b16 v5.h, v1.l
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// GFX12: v_swap_b16 v5.h, v1.l ; encoding: [0x01,0xcd,0x0a,0x7f]
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v_swap_b16 v127.l, v127.l
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// GFX12: v_swap_b16 v127.l, v127.l ; encoding: [0x7f,0xcd,0xfe,0x7e]
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v_swap_b32 v5, v1
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// GFX12: v_swap_b32 v5, v1 ; encoding: [0x01,0xcb,0x0a,0x7e]
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‎llvm/test/MC/AMDGPU/gfx12_asm_vop1_t16_err.s‎

Lines changed: 15 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -201,6 +201,21 @@ v_sqrt_f16_e32 v255, v1
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v_sqrt_f16_e32 v5, v199
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// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
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v_swap_b16_e32 v128.l, v0.l
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// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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v_swap_b16_e32 v0.l, v255.l
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// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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v_swap_b16_e32 v0.l, s0
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// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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v_swap_b16_e32 v0.l, 0
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// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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v_swap_b16_e32 v0.l, 0xfe0b
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// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
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v_trunc_f16_e32 v128, 0xfe0b
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// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: operands are not valid for this GPU or mode
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‎llvm/test/MC/Disassembler/AMDGPU/decode-err.txt‎

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -19,6 +19,18 @@
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# W64: [[@LINE+1]]:1: warning: invalid instruction encoding
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0xff,0x04,0x02,0xc9,0x03,0x03,0x06,0x05,0x56,0x34,0x12,0xaf
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# GFX11: v_swap_b16 v5.h, s1/*Invalid register, operand has 'VGPR_16_Lo128' register class*/ ; encoding: [0x01,0xcc,0x0a,0x7f]
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# GFX12: v_swap_b16 v5.h, s1/*Invalid register, operand has 'VGPR_16_Lo128' register class*/ ; encoding: [0x01,0xcc,0x0a,0x7f]
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0x01,0xcc,0x0a,0x7f
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# GFX11: v_swap_b16 v5.h, 0x3c00/*Invalid immediate*/ ; encoding: [0x00,0xcc,0x0a,0x7f]
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# GFX12: v_swap_b16 v5.h, 0x3c00/*Invalid immediate*/ ; encoding: [0x00,0xcc,0x0a,0x7f]
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0xf2,0xcc,0x0a,0x7f
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# GFX11: v_swap_b16 v5.h, 0x78563412/*Invalid immediate*/ ; encoding: [0x12,0xcc,0x0a,0x7f]
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# GFX12: v_swap_b16 v5.h, 0x78563412/*Invalid immediate*/ ; encoding: [0x12,0xcc,0x0a,0x7f]
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0xff,0xcc,0x0a,0x7f,0x12,0x34,0x56,0x78
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# W32: v_wmma_f32_16x16x16_f16 v[16:23], v[0:7], v[8:15], v[16:23] ; encoding: [0x10,0x40,0x40,0xcc,0x00,0x11,0x42,0x1c]
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# W64: v_wmma_f32_16x16x16_f16 v[16:19], v[0:7], v[8:15], v[16:19] ; encoding: [0x10,0x40,0x40,0xcc,0x00,0x11,0x42,0x1c]
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0x10,0x40,0x40,0xcc,0x00,0x11,0x42,0x1c

‎llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop1.txt‎

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3344,6 +3344,12 @@
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# GFX11: v_sqrt_f64_e32 v[254:255], 0xaf123456 ; encoding: [0xff,0x68,0xfc,0x7f,0x56,0x34,0x12,0xaf]
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0xff,0x68,0xfc,0x7f,0x56,0x34,0x12,0xaf
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3347+
# GFX11-TRUE16: v_swap_b16 v5.l, v1.h ; encoding: [0x81,0xcd,0x0a,0x7e]
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0x81,0xcd,0x0a,0x7e
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3350+
# GFX11-TRUE16: v_swap_b16 v5.h, v1.l ; encoding: [0x01,0xcd,0x0a,0x7f]
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0x01,0xcd,0x0a,0x7f
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# GFX11: v_swap_b32 v5, v1 ; encoding: [0x01,0xcb,0x0a,0x7e]
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0x01,0xcb,0x0a,0x7e
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