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[WIP] [CodeGen] Enable TrapUnreachable by default for all targets.
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106 files changed

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Diff for: ‎llvm/include/llvm/Target/TargetOptions.h

+1-1
Original file line numberDiff line numberDiff line change
@@ -145,7 +145,7 @@ namespace llvm {
145145
DataSections(false), IgnoreXCOFFVisibility(false),
146146
XCOFFTracebackTable(true), UniqueSectionNames(true),
147147
UniqueBasicBlockSectionNames(false), SeparateNamedSections(false),
148-
TrapUnreachable(false), NoTrapAfterNoreturn(false), TLSSize(0),
148+
TrapUnreachable(true), NoTrapAfterNoreturn(true), TLSSize(0),
149149
EmulatedTLS(false), EnableTLSDESC(false), EnableIPRA(false),
150150
EmitStackSizeSection(false), EnableMachineOutliner(false),
151151
EnableMachineFunctionSplitter(false), SupportsDefaultOutlining(false),

Diff for: ‎llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp

+5-10
Original file line numberDiff line numberDiff line change
@@ -3807,16 +3807,11 @@ bool IRTranslator::emitSPDescriptorFailure(StackProtectorDescriptor &SPD,
38073807
return false;
38083808
}
38093809

3810-
// On PS4/PS5, the "return address" must still be within the calling
3811-
// function, even if it's at the very end, so emit an explicit TRAP here.
3812-
// WebAssembly needs an unreachable instruction after a non-returning call,
3813-
// because the function return type can be different from __stack_chk_fail's
3814-
// return type (void).
3815-
const TargetMachine &TM = MF->getTarget();
3816-
if (TM.getTargetTriple().isPS() || TM.getTargetTriple().isWasm()) {
3817-
LLVM_DEBUG(dbgs() << "Unhandled trap emission for stack protector fail\n");
3818-
return false;
3819-
}
3810+
// Emit a trap instruction if we are required to do so.
3811+
const TargetOptions &TargetOpts = TLI->getTargetMachine().Options;
3812+
if (TargetOpts.TrapUnreachable && !TargetOpts.NoTrapAfterNoreturn)
3813+
CurBuilder->buildInstr(TargetOpcode::G_TRAP);
3814+
38203815
return true;
38213816
}
38223817

Diff for: ‎llvm/lib/CodeGen/LLVMTargetMachine.cpp

+13-8
Original file line numberDiff line numberDiff line change
@@ -33,11 +33,11 @@
3333
#include "llvm/Target/TargetOptions.h"
3434
using namespace llvm;
3535

36-
static cl::opt<bool>
37-
EnableTrapUnreachable("trap-unreachable", cl::Hidden,
38-
cl::desc("Enable generating trap for unreachable"));
36+
cl::opt<bool> EnableTrapUnreachable(
37+
"trap-unreachable", cl::Hidden,
38+
cl::desc("Enable generating trap for unreachable"));
3939

40-
static cl::opt<bool> EnableNoTrapAfterNoreturn(
40+
cl::opt<bool> EnableNoTrapAfterNoreturn(
4141
"no-trap-after-noreturn", cl::Hidden,
4242
cl::desc("Do not emit a trap instruction for 'unreachable' IR instructions "
4343
"after noreturn calls, even if --trap-unreachable is set."));
@@ -96,10 +96,15 @@ LLVMTargetMachine::LLVMTargetMachine(const Target &T,
9696
this->CMModel = CM;
9797
this->OptLevel = OL;
9898

99-
if (EnableTrapUnreachable)
100-
this->Options.TrapUnreachable = true;
101-
if (EnableNoTrapAfterNoreturn)
102-
this->Options.NoTrapAfterNoreturn = true;
99+
if (EnableTrapUnreachable.getNumOccurrences())
100+
this->Options.TrapUnreachable = EnableTrapUnreachable;
101+
102+
if (EnableNoTrapAfterNoreturn.getNumOccurrences())
103+
this->Options.NoTrapAfterNoreturn = EnableNoTrapAfterNoreturn;
104+
105+
// Keep all traps in debug environments.
106+
else if (OL == CodeGenOptLevel::None)
107+
this->Options.NoTrapAfterNoreturn = false;
103108
}
104109

105110
TargetTransformInfo

Diff for: ‎llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

+4-9
Original file line numberDiff line numberDiff line change
@@ -3183,15 +3183,10 @@ SelectionDAGBuilder::visitSPDescriptorFailure(StackProtectorDescriptor &SPD) {
31833183
SDValue Chain = TLI.makeLibCall(DAG, RTLIB::STACKPROTECTOR_CHECK_FAIL,
31843184
MVT::isVoid, {}, CallOptions, getCurSDLoc())
31853185
.second;
3186-
// On PS4/PS5, the "return address" must still be within the calling
3187-
// function, even if it's at the very end, so emit an explicit TRAP here.
3188-
// Passing 'true' for doesNotReturn above won't generate the trap for us.
3189-
if (TM.getTargetTriple().isPS())
3190-
Chain = DAG.getNode(ISD::TRAP, getCurSDLoc(), MVT::Other, Chain);
3191-
// WebAssembly needs an unreachable instruction after a non-returning call,
3192-
// because the function return type can be different from __stack_chk_fail's
3193-
// return type (void).
3194-
if (TM.getTargetTriple().isWasm())
3186+
3187+
// If our current target options require us to add a trap instruction, do so.
3188+
const TargetOptions &TargetOpts = DAG.getTarget().Options;
3189+
if (TargetOpts.TrapUnreachable && !TargetOpts.NoTrapAfterNoreturn)
31953190
Chain = DAG.getNode(ISD::TRAP, getCurSDLoc(), MVT::Other, Chain);
31963191

31973192
DAG.setRoot(Chain);

Diff for: ‎llvm/lib/Target/AArch64/AArch64TargetMachine.cpp

+1-5
Original file line numberDiff line numberDiff line change
@@ -360,11 +360,6 @@ AArch64TargetMachine::AArch64TargetMachine(const Target &T, const Triple &TT,
360360
TLOF(createTLOF(getTargetTriple())), isLittle(LittleEndian) {
361361
initAsmInfo();
362362

363-
if (TT.isOSBinFormatMachO()) {
364-
this->Options.TrapUnreachable = true;
365-
this->Options.NoTrapAfterNoreturn = true;
366-
}
367-
368363
if (getMCAsmInfo()->usesWindowsCFI()) {
369364
// Unwinding can get confused if the last instruction in an
370365
// exception-handling region (function, funclet, try block, etc.)
@@ -373,6 +368,7 @@ AArch64TargetMachine::AArch64TargetMachine(const Target &T, const Triple &TT,
373368
// FIXME: We could elide the trap if the next instruction would be in
374369
// the same region anyway.
375370
this->Options.TrapUnreachable = true;
371+
this->Options.NoTrapAfterNoreturn = false;
376372
}
377373

378374
if (this->Options.TLSSize == 0) // default

Diff for: ‎llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp

+6
Original file line numberDiff line numberDiff line change
@@ -396,6 +396,8 @@ static cl::opt<bool>
396396
cl::desc("Enable AMDGPUAttributorPass"),
397397
cl::init(true), cl::Hidden);
398398

399+
extern cl::opt<bool> EnableTrapUnreachable;
400+
399401
extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUTarget() {
400402
// Register the target
401403
RegisterTargetMachine<R600TargetMachine> X(getTheR600Target());
@@ -612,6 +614,10 @@ AMDGPUTargetMachine::AMDGPUTargetMachine(const Target &T, const Triple &TT,
612614
FS, Options, getEffectiveRelocModel(RM),
613615
getEffectiveCodeModel(CM, CodeModel::Small), OptLevel),
614616
TLOF(createTLOF(getTargetTriple())) {
617+
// FIXME: There are some scenarios where targets may not have hardware traps,
618+
// and external calls to `abort` also fail. For now, do a blanket-disable.
619+
if (!EnableTrapUnreachable.getNumOccurrences())
620+
this->Options.TrapUnreachable = false;
615621
initAsmInfo();
616622
if (TT.getArch() == Triple::amdgcn) {
617623
if (getMCSubtargetInfo()->checkFeatures("+wavefrontsize64"))

Diff for: ‎llvm/lib/Target/ARM/ARMTargetMachine.cpp

-5
Original file line numberDiff line numberDiff line change
@@ -251,11 +251,6 @@ ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, const Triple &TT,
251251
this->Options.EABIVersion = EABI::EABI5;
252252
}
253253

254-
if (TT.isOSBinFormatMachO()) {
255-
this->Options.TrapUnreachable = true;
256-
this->Options.NoTrapAfterNoreturn = true;
257-
}
258-
259254
// ARM supports the debug entry values.
260255
setSupportsDebugEntryValues(true);
261256

Diff for: ‎llvm/lib/Target/BPF/BPFTargetMachine.cpp

+8
Original file line numberDiff line numberDiff line change
@@ -34,6 +34,8 @@
3434
#include <optional>
3535
using namespace llvm;
3636

37+
extern cl::opt<bool> EnableTrapUnreachable;
38+
3739
static cl::
3840
opt<bool> DisableMIPeephole("disable-bpf-peephole", cl::Hidden,
3941
cl::desc("Disable machine peepholes for BPF"));
@@ -74,6 +76,12 @@ BPFTargetMachine::BPFTargetMachine(const Target &T, const Triple &TT,
7476
getEffectiveCodeModel(CM, CodeModel::Small), OL),
7577
TLOF(std::make_unique<TargetLoweringObjectFileELF>()),
7678
Subtarget(TT, std::string(CPU), std::string(FS), *this) {
79+
// FIXME: If the user has not explicitly enabled TrapUnreachable,
80+
// disable it. We do not have an explicit trap opcode and external calls
81+
// to abort are a no-no.
82+
if (!EnableTrapUnreachable.getNumOccurrences())
83+
this->Options.TrapUnreachable = false;
84+
7785
initAsmInfo();
7886

7987
BPFMCAsmInfo *MAI =

Diff for: ‎llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp

+7
Original file line numberDiff line numberDiff line change
@@ -146,6 +146,8 @@ static cl::opt<bool> EnableInstSimplify("hexagon-instsimplify", cl::Hidden,
146146
cl::init(true),
147147
cl::desc("Enable instsimplify"));
148148

149+
extern cl::opt<bool> EnableTrapUnreachable;
150+
149151
/// HexagonTargetMachineModule - Note that this is used on hosts that
150152
/// cannot link in a library unless there are references into the
151153
/// library. In particular, it seems that it is not possible to get
@@ -284,6 +286,11 @@ HexagonTargetMachine::HexagonTargetMachine(const Target &T, const Triple &TT,
284286
(HexagonNoOpt ? CodeGenOptLevel::None : OL)),
285287
TLOF(std::make_unique<HexagonTargetObjectFile>()),
286288
Subtarget(Triple(TT), CPU, FS, *this) {
289+
// FIXME: If the user has not explicitly enabled TrapUnreachable,
290+
// disable it. We currently seem to have problems with EH_RETURN lowering.
291+
if (!EnableTrapUnreachable.getNumOccurrences())
292+
this->Options.TrapUnreachable = false;
293+
287294
initializeHexagonCopyHoistingPass(*PassRegistry::getPassRegistry());
288295
initializeHexagonExpandCondsetsPass(*PassRegistry::getPassRegistry());
289296
initializeHexagonLoopAlignPass(*PassRegistry::getPassRegistry());

Diff for: ‎llvm/lib/Target/X86/X86TargetMachine.cpp

+4-3
Original file line numberDiff line numberDiff line change
@@ -242,10 +242,11 @@ X86TargetMachine::X86TargetMachine(const Target &T, const Triple &TT,
242242
OL),
243243
TLOF(createTLOF(getTargetTriple())), IsJIT(JIT) {
244244
// On PS4/PS5, the "return address" of a 'noreturn' call must still be within
245-
// the calling function, and TrapUnreachable is an easy way to get that.
246-
if (TT.isPS() || TT.isOSBinFormatMachO()) {
245+
// the calling function, and unsetting NoTrapAfterNoreturn
246+
// is an easy way to get that.
247+
if (TT.isPS()) {
247248
this->Options.TrapUnreachable = true;
248-
this->Options.NoTrapAfterNoreturn = TT.isOSBinFormatMachO();
249+
this->Options.NoTrapAfterNoreturn = false;
249250
}
250251

251252
setMachineOutliner(true);

Diff for: ‎llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-switch.ll

+16
Original file line numberDiff line numberDiff line change
@@ -137,6 +137,8 @@ define i32 @test_cfg_remap_multiple_preds(i32 %in) {
137137
; CHECK-NEXT: bb.2.odd:
138138
; CHECK-NEXT: successors:
139139
; CHECK-NEXT: {{ $}}
140+
; CHECK-NEXT: G_TRAP
141+
; CHECK-NEXT: {{ $}}
140142
; CHECK-NEXT: bb.3.next:
141143
; CHECK-NEXT: G_BR %bb.5
142144
; CHECK-NEXT: {{ $}}
@@ -1147,18 +1149,28 @@ define void @jt_2_tables_phi_edge_from_second() {
11471149
; CHECK-NEXT: bb.2.if.then:
11481150
; CHECK-NEXT: successors:
11491151
; CHECK-NEXT: {{ $}}
1152+
; CHECK-NEXT: G_TRAP
1153+
; CHECK-NEXT: {{ $}}
11501154
; CHECK-NEXT: bb.3.sw.bb2.i41:
11511155
; CHECK-NEXT: successors:
11521156
; CHECK-NEXT: {{ $}}
1157+
; CHECK-NEXT: G_TRAP
1158+
; CHECK-NEXT: {{ $}}
11531159
; CHECK-NEXT: bb.4.sw.bb7.i44:
11541160
; CHECK-NEXT: successors:
11551161
; CHECK-NEXT: {{ $}}
1162+
; CHECK-NEXT: G_TRAP
1163+
; CHECK-NEXT: {{ $}}
11561164
; CHECK-NEXT: bb.5.sw.bb8.i45:
11571165
; CHECK-NEXT: successors:
11581166
; CHECK-NEXT: {{ $}}
1167+
; CHECK-NEXT: G_TRAP
1168+
; CHECK-NEXT: {{ $}}
11591169
; CHECK-NEXT: bb.6.sw.bb13.i47:
11601170
; CHECK-NEXT: successors:
11611171
; CHECK-NEXT: {{ $}}
1172+
; CHECK-NEXT: G_TRAP
1173+
; CHECK-NEXT: {{ $}}
11621174
; CHECK-NEXT: bb.7.sw.bb14.i48:
11631175
; CHECK-NEXT: [[ICMP5:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[DEF1]](s32), [[C5]]
11641176
; CHECK-NEXT: G_BRCOND [[ICMP5]](s1), %bb.10
@@ -1202,6 +1214,8 @@ define void @jt_2_tables_phi_edge_from_second() {
12021214
; CHECK-NEXT: bb.8.sw.default.i49:
12031215
; CHECK-NEXT: successors:
12041216
; CHECK-NEXT: {{ $}}
1217+
; CHECK-NEXT: G_TRAP
1218+
; CHECK-NEXT: {{ $}}
12051219
; CHECK-NEXT: bb.9.sw.bb1.i:
12061220
; CHECK-NEXT: G_BR %bb.16
12071221
; CHECK-NEXT: {{ $}}
@@ -1234,6 +1248,7 @@ define void @jt_2_tables_phi_edge_from_second() {
12341248
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
12351249
; CHECK-NEXT: BL @jt_2_tables_phi_edge_from_second, csr_aarch64_aapcs, implicit-def $lr, implicit $sp
12361250
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
1251+
; CHECK-NEXT: G_TRAP
12371252
; CHECK-NEXT: {{ $}}
12381253
; CHECK-NEXT: bb.18.while.end:
12391254
; CHECK-NEXT: [[PHI1:%[0-9]+]]:_(s32) = G_PHI [[C21]](s32), %bb.30, [[PHI]](s32), %bb.16
@@ -1460,6 +1475,7 @@ define i1 @i1_value_cmp_is_signed(i1) {
14601475
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
14611476
; CHECK-NEXT: BL @bar, csr_aarch64_aapcs, implicit-def $lr, implicit $sp
14621477
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
1478+
; CHECK-NEXT: G_TRAP
14631479
; CHECK-NEXT: {{ $}}
14641480
; CHECK-NEXT: bb.3.OkValue:
14651481
; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s8) = G_ZEXT [[TRUNC1]](s1)

Diff for: ‎llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll

+1-2
Original file line numberDiff line numberDiff line change
@@ -431,8 +431,7 @@ end:
431431

432432
; CHECK-LABEL: name: unreachable
433433
; CHECK: G_ADD
434-
; CHECK-NEXT: {{^$}}
435-
; CHECK-NEXT: ...
434+
; CHECK-NEXT: G_TRAP
436435
define void @unreachable(i32 %a) {
437436
%sum = add i32 %a, %a
438437
unreachable

Diff for: ‎llvm/test/CodeGen/AArch64/arm64-big-endian-eh.ll

+1-1
Original file line numberDiff line numberDiff line change
@@ -71,6 +71,6 @@ declare void @_ZSt9terminatev()
7171
; CHECK-LABEL: Contents of section .eh_frame:
7272
; CHECK-NEXT: {{^ 0000}}
7373
; CHECK-NEXT: {{^ 0010}}
74-
; CHECK-NEXT: 0020 0000000c 00440e10 9e040000 0000001c .....D..........
74+
; CHECK-NEXT: 0020 00000010 00440e10 9e040000 0000001c .....D..........
7575
; CHECK-NEXT: 0030 00000000 017a504c 5200017c 1e0b9c00 .....zPLR..|....
7676

Diff for: ‎llvm/test/CodeGen/AArch64/ptrauth-invoke.ll

+1
Original file line numberDiff line numberDiff line change
@@ -173,6 +173,7 @@ continuebb:
173173
; ELF-NEXT: blrab x19, x17
174174
; ELF-NEXT: [[POSTCALL:.L.*]]:
175175
; ELF-NEXT: // %bb.1:
176+
; ELF-NEXT: brk #0x1
176177
; ELF-NEXT: [[LPADBB:.LBB[0-9_]+]]:
177178
; ELF-NEXT: [[LPAD:.L.*]]:
178179
; ELF-NEXT: mov x19, x1

Diff for: ‎llvm/test/CodeGen/ARM/ifcvt-branch-weight-bug.ll

+1-1
Original file line numberDiff line numberDiff line change
@@ -22,7 +22,7 @@ entry:
2222
; for.body -> for.cond.backedge (100%)
2323
; -> cond.false.i (0%)
2424
; CHECK: bb.1.for.body:
25-
; CHECK: successors: %bb.2(0x80000000), %bb.5(0x00000000)
25+
; CHECK: successors: %bb.2(0x80000000), %bb.4(0x00000000)
2626
for.body:
2727
br i1 undef, label %for.cond.backedge, label %lor.lhs.false.i, !prof !1
2828

Diff for: ‎llvm/test/CodeGen/ARM/machine-sink-multidef.ll

+2-1
Original file line numberDiff line numberDiff line change
@@ -23,7 +23,8 @@ define arm_aapcscc void @g() {
2323
; CHECK-NEXT: push {r11, lr}
2424
; CHECK-NEXT: ldr r1, [r1, #4]
2525
; CHECK-NEXT: bl k
26-
; CHECK-NEXT: .p2align 2
26+
; CHECK-NEXT: .inst 0xe7ffdefe
27+
; CHECK-NEXT: .p2align 2 @ trap
2728
; CHECK-NEXT: @ %bb.2:
2829
; CHECK-NEXT: .LCPI0_0:
2930
; CHECK-NEXT: .long f

Diff for: ‎llvm/test/CodeGen/ARM/sub-cmp-peephole.ll

+8-2
Original file line numberDiff line numberDiff line change
@@ -270,8 +270,11 @@ define i32 @cmp_slt0(i32 %a, i32 %b, i32 %x, i32 %y) {
270270
; CHECK-NEXT: @ %bb.1: @ %if.else
271271
; CHECK-NEXT: mov r0, #0
272272
; CHECK-NEXT: bl exit
273-
; CHECK-NEXT: .LBB11_2: @ %if.then
273+
; CHECK-NEXT: .inst 0xe7ffdefe
274+
; CHECK-NEXT: .LBB11_2: @ trap
275+
; CHECK-NEXT: @ %if.then
274276
; CHECK-NEXT: bl abort
277+
; CHECK-NEXT: .inst 0xe7ffdefe
275278
entry:
276279
%load = load i32, ptr @t, align 4
277280
%sub = sub i32 %load, 17
@@ -302,9 +305,12 @@ define i32 @cmp_ult0(i32 %a, i32 %b, i32 %x, i32 %y) {
302305
; CHECK-NEXT: bhs .LBB12_2
303306
; CHECK-NEXT: @ %bb.1: @ %if.then
304307
; CHECK-NEXT: bl abort
305-
; CHECK-NEXT: .LBB12_2: @ %if.else
308+
; CHECK-NEXT: .inst 0xe7ffdefe
309+
; CHECK-NEXT: .LBB12_2: @ trap
310+
; CHECK-NEXT: @ %if.else
306311
; CHECK-NEXT: mov r0, #0
307312
; CHECK-NEXT: bl exit
313+
; CHECK-NEXT: .inst 0xe7ffdefe
308314
entry:
309315
%load = load i32, ptr @t, align 4
310316
%sub = sub i32 %load, 17

Diff for: ‎llvm/test/CodeGen/ARM/trap-unreachable.ll

+1-1
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
1-
; RUN: llc -mtriple=thumbv7 -trap-unreachable < %s | FileCheck %s --check-prefixes CHECK,TRAP_UNREACHABLE
1+
; RUN: llc -mtriple=thumbv7 -trap-unreachable -no-trap-after-noreturn=false < %s | FileCheck %s --check-prefixes CHECK,TRAP_UNREACHABLE
22
; RUN: llc -mtriple=thumbv7 -trap-unreachable -no-trap-after-noreturn < %s | FileCheck %s --check-prefixes CHECK,NTANR
33

44
define void @test_trap_unreachable() #0 {

Diff for: ‎llvm/test/CodeGen/ARM/v8m.base-jumptable_alignment.ll

+6-7
Original file line numberDiff line numberDiff line change
@@ -18,9 +18,9 @@ define void @main() {
1818
; CHECK-NEXT: ldr r0, [r0]
1919
; CHECK-NEXT: movs r0, #0
2020
; CHECK-NEXT: cmp r0, #0
21-
; CHECK-NEXT: beq .LBB0_7
21+
; CHECK-NEXT: beq .LBB0_6
2222
; CHECK-NEXT: @ %bb.1: @ %for.cond7.preheader.i.lr.ph.i.i
23-
; CHECK-NEXT: bne .LBB0_7
23+
; CHECK-NEXT: bne .LBB0_6
2424
; CHECK-NEXT: .LBB0_2: @ %for.cond14.preheader.us.i.i.i
2525
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
2626
; CHECK-NEXT: cbnz r0, .LBB0_6
@@ -35,8 +35,8 @@ define void @main() {
3535
; CHECK-NEXT: .LJTI0_0:
3636
; CHECK-NEXT: b.w .LBB0_5
3737
; CHECK-NEXT: b.w .LBB0_6
38-
; CHECK-NEXT: b.w .LBB0_8
39-
; CHECK-NEXT: b.w .LBB0_7
38+
; CHECK-NEXT: b.w .LBB0_6
39+
; CHECK-NEXT: b.w .LBB0_6
4040
; CHECK-NEXT: b.w .LBB0_6
4141
; CHECK-NEXT: b.w .LBB0_6
4242
; CHECK-NEXT: b.w .LBB0_6
@@ -48,9 +48,8 @@ define void @main() {
4848
; CHECK-NEXT: .LBB0_5: @ %for.cond14.preheader.us.i.i.i
4949
; CHECK-NEXT: @ in Loop: Header=BB0_2 Depth=1
5050
; CHECK-NEXT: b .LBB0_2
51-
; CHECK-NEXT: .LBB0_6: @ %func_1.exit.loopexit
52-
; CHECK-NEXT: .LBB0_7: @ %for.end476.i.i.i.loopexit
53-
; CHECK-NEXT: .LBB0_8: @ %lbl_1394.i.i.i.loopexit
51+
; CHECK-NEXT: .LBB0_6: @ %lbl_1394.i.i.i.loopexit
52+
; CHECK-NEXT: .inst.n 0xdefe
5453
entry:
5554
%0 = load volatile ptr, ptr @g_566, align 4
5655
br label %func_16.exit.i.i.i

Diff for: ‎llvm/test/CodeGen/ARM/vcge.ll

+1
Original file line numberDiff line numberDiff line change
@@ -289,6 +289,7 @@ define void @test_vclez_fp(ptr %A) nounwind optsize {
289289
; CHECK-NEXT: vuzp.8 d16, d18
290290
; CHECK-NEXT: vadd.i8 d16, d16, d17
291291
; CHECK-NEXT: vst1.8 {d16}, [r0]
292+
; CHECK-NEXT: .inst 0xe7ffdefe
292293
entry:
293294
%ld = load <4 x float>, ptr %A
294295
%0 = fcmp ole <4 x float> %ld, zeroinitializer

Diff for: ‎llvm/test/CodeGen/ARM/vector-DAGCombine.ll

+2
Original file line numberDiff line numberDiff line change
@@ -27,6 +27,7 @@ bb.i19: ; preds = %bb.i19, %bb3
2727
define void @test_illegal_build_vector() nounwind {
2828
; CHECK-LABEL: test_illegal_build_vector:
2929
; CHECK: @ %bb.0: @ %entry
30+
; CHECK-NEXT: .inst 0xe7ffdefe
3031
entry:
3132
store <2 x i64> undef, ptr undef, align 16
3233
%0 = load <16 x i8>, ptr undef, align 16 ; <<16 x i8>> [#uses=1]
@@ -40,6 +41,7 @@ entry:
4041
define void @test_pr22678() {
4142
; CHECK-LABEL: test_pr22678:
4243
; CHECK: @ %bb.0:
44+
; CHECK-NEXT: .inst 0xe7ffdefe
4345
%1 = fptoui <16 x float> undef to <16 x i8>
4446
store <16 x i8> %1, ptr undef
4547
ret void

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