Skip to content

Commit c1ef7c7

Browse files
jmmartinezjmmartinez
committed
[AMDGPU] Add missing cases for V_INDIRECT_REG_{READ/WRITE}_GPR_IDX and V/S_INDIRECT_REG_WRITE_MOVREL
A buildbot failure in #170323 when expensive checks were used highlighted that some of these patterns were missing. This patch adds V_INDIRECT_REG_{READ/WRITE}_GPR_IDX and V/S_INDIRECT_REG_WRITE_MOVREL for V6 and V7 vector sizes
1 parent 2967815 commit c1ef7c7

File tree

4 files changed

+297
-0
lines changed

4 files changed

+297
-0
lines changed

‎llvm/lib/Target/AMDGPU/SIInstrInfo.cpp‎

Lines changed: 24 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1394,6 +1394,10 @@ SIInstrInfo::getIndirectGPRIDXPseudo(unsigned VecSize,
13941394
return get(AMDGPU::V_INDIRECT_REG_READ_GPR_IDX_B32_V4);
13951395
if (VecSize <= 160) // 20 bytes
13961396
return get(AMDGPU::V_INDIRECT_REG_READ_GPR_IDX_B32_V5);
1397+
if (VecSize <= 192) // 24 bytes
1398+
return get(AMDGPU::V_INDIRECT_REG_READ_GPR_IDX_B32_V6);
1399+
if (VecSize <= 224) // 28 bytes
1400+
return get(AMDGPU::V_INDIRECT_REG_READ_GPR_IDX_B32_V7);
13971401
if (VecSize <= 256) // 32 bytes
13981402
return get(AMDGPU::V_INDIRECT_REG_READ_GPR_IDX_B32_V8);
13991403
if (VecSize <= 288) // 36 bytes
@@ -1422,6 +1426,10 @@ SIInstrInfo::getIndirectGPRIDXPseudo(unsigned VecSize,
14221426
return get(AMDGPU::V_INDIRECT_REG_WRITE_GPR_IDX_B32_V4);
14231427
if (VecSize <= 160) // 20 bytes
14241428
return get(AMDGPU::V_INDIRECT_REG_WRITE_GPR_IDX_B32_V5);
1429+
if (VecSize <= 192) // 24 bytes
1430+
return get(AMDGPU::V_INDIRECT_REG_WRITE_GPR_IDX_B32_V6);
1431+
if (VecSize <= 224) // 28 bytes
1432+
return get(AMDGPU::V_INDIRECT_REG_WRITE_GPR_IDX_B32_V7);
14251433
if (VecSize <= 256) // 32 bytes
14261434
return get(AMDGPU::V_INDIRECT_REG_WRITE_GPR_IDX_B32_V8);
14271435
if (VecSize <= 288) // 36 bytes
@@ -1451,6 +1459,10 @@ static unsigned getIndirectVGPRWriteMovRelPseudoOpc(unsigned VecSize) {
14511459
return AMDGPU::V_INDIRECT_REG_WRITE_MOVREL_B32_V4;
14521460
if (VecSize <= 160) // 20 bytes
14531461
return AMDGPU::V_INDIRECT_REG_WRITE_MOVREL_B32_V5;
1462+
if (VecSize <= 192) // 24 bytes
1463+
return AMDGPU::V_INDIRECT_REG_WRITE_MOVREL_B32_V6;
1464+
if (VecSize <= 224) // 28 bytes
1465+
return AMDGPU::V_INDIRECT_REG_WRITE_MOVREL_B32_V7;
14541466
if (VecSize <= 256) // 32 bytes
14551467
return AMDGPU::V_INDIRECT_REG_WRITE_MOVREL_B32_V8;
14561468
if (VecSize <= 288) // 36 bytes
@@ -1480,6 +1492,10 @@ static unsigned getIndirectSGPRWriteMovRelPseudo32(unsigned VecSize) {
14801492
return AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B32_V4;
14811493
if (VecSize <= 160) // 20 bytes
14821494
return AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B32_V5;
1495+
if (VecSize <= 192) // 24 bytes
1496+
return AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B32_V6;
1497+
if (VecSize <= 224) // 28 bytes
1498+
return AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B32_V7;
14831499
if (VecSize <= 256) // 32 bytes
14841500
return AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B32_V8;
14851501
if (VecSize <= 288) // 36 bytes
@@ -2244,6 +2260,8 @@ bool SIInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
22442260
case AMDGPU::V_INDIRECT_REG_WRITE_MOVREL_B32_V3:
22452261
case AMDGPU::V_INDIRECT_REG_WRITE_MOVREL_B32_V4:
22462262
case AMDGPU::V_INDIRECT_REG_WRITE_MOVREL_B32_V5:
2263+
case AMDGPU::V_INDIRECT_REG_WRITE_MOVREL_B32_V6:
2264+
case AMDGPU::V_INDIRECT_REG_WRITE_MOVREL_B32_V7:
22472265
case AMDGPU::V_INDIRECT_REG_WRITE_MOVREL_B32_V8:
22482266
case AMDGPU::V_INDIRECT_REG_WRITE_MOVREL_B32_V9:
22492267
case AMDGPU::V_INDIRECT_REG_WRITE_MOVREL_B32_V10:
@@ -2256,6 +2274,8 @@ bool SIInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
22562274
case AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B32_V3:
22572275
case AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B32_V4:
22582276
case AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B32_V5:
2277+
case AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B32_V6:
2278+
case AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B32_V7:
22592279
case AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B32_V8:
22602280
case AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B32_V9:
22612281
case AMDGPU::S_INDIRECT_REG_WRITE_MOVREL_B32_V10:
@@ -2303,6 +2323,8 @@ bool SIInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
23032323
case AMDGPU::V_INDIRECT_REG_WRITE_GPR_IDX_B32_V3:
23042324
case AMDGPU::V_INDIRECT_REG_WRITE_GPR_IDX_B32_V4:
23052325
case AMDGPU::V_INDIRECT_REG_WRITE_GPR_IDX_B32_V5:
2326+
case AMDGPU::V_INDIRECT_REG_WRITE_GPR_IDX_B32_V6:
2327+
case AMDGPU::V_INDIRECT_REG_WRITE_GPR_IDX_B32_V7:
23062328
case AMDGPU::V_INDIRECT_REG_WRITE_GPR_IDX_B32_V8:
23072329
case AMDGPU::V_INDIRECT_REG_WRITE_GPR_IDX_B32_V9:
23082330
case AMDGPU::V_INDIRECT_REG_WRITE_GPR_IDX_B32_V10:
@@ -2347,6 +2369,8 @@ bool SIInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
23472369
case AMDGPU::V_INDIRECT_REG_READ_GPR_IDX_B32_V3:
23482370
case AMDGPU::V_INDIRECT_REG_READ_GPR_IDX_B32_V4:
23492371
case AMDGPU::V_INDIRECT_REG_READ_GPR_IDX_B32_V5:
2372+
case AMDGPU::V_INDIRECT_REG_READ_GPR_IDX_B32_V6:
2373+
case AMDGPU::V_INDIRECT_REG_READ_GPR_IDX_B32_V7:
23502374
case AMDGPU::V_INDIRECT_REG_READ_GPR_IDX_B32_V8:
23512375
case AMDGPU::V_INDIRECT_REG_READ_GPR_IDX_B32_V9:
23522376
case AMDGPU::V_INDIRECT_REG_READ_GPR_IDX_B32_V10:

‎llvm/lib/Target/AMDGPU/SIInstructions.td‎

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1026,6 +1026,8 @@ def V_INDIRECT_REG_WRITE_MOVREL_B32_V2 : V_INDIRECT_REG_WRITE_MOVREL_B32_pseudo<
10261026
def V_INDIRECT_REG_WRITE_MOVREL_B32_V3 : V_INDIRECT_REG_WRITE_MOVREL_B32_pseudo<VReg_96>;
10271027
def V_INDIRECT_REG_WRITE_MOVREL_B32_V4 : V_INDIRECT_REG_WRITE_MOVREL_B32_pseudo<VReg_128>;
10281028
def V_INDIRECT_REG_WRITE_MOVREL_B32_V5 : V_INDIRECT_REG_WRITE_MOVREL_B32_pseudo<VReg_160>;
1029+
def V_INDIRECT_REG_WRITE_MOVREL_B32_V6 : V_INDIRECT_REG_WRITE_MOVREL_B32_pseudo<VReg_192>;
1030+
def V_INDIRECT_REG_WRITE_MOVREL_B32_V7 : V_INDIRECT_REG_WRITE_MOVREL_B32_pseudo<VReg_224>;
10291031
def V_INDIRECT_REG_WRITE_MOVREL_B32_V8 : V_INDIRECT_REG_WRITE_MOVREL_B32_pseudo<VReg_256>;
10301032
def V_INDIRECT_REG_WRITE_MOVREL_B32_V9 : V_INDIRECT_REG_WRITE_MOVREL_B32_pseudo<VReg_288>;
10311033
def V_INDIRECT_REG_WRITE_MOVREL_B32_V10 : V_INDIRECT_REG_WRITE_MOVREL_B32_pseudo<VReg_320>;
@@ -1039,6 +1041,8 @@ def S_INDIRECT_REG_WRITE_MOVREL_B32_V2 : S_INDIRECT_REG_WRITE_MOVREL_B32_pseudo<
10391041
def S_INDIRECT_REG_WRITE_MOVREL_B32_V3 : S_INDIRECT_REG_WRITE_MOVREL_B32_pseudo<SReg_96>;
10401042
def S_INDIRECT_REG_WRITE_MOVREL_B32_V4 : S_INDIRECT_REG_WRITE_MOVREL_B32_pseudo<SReg_128>;
10411043
def S_INDIRECT_REG_WRITE_MOVREL_B32_V5 : S_INDIRECT_REG_WRITE_MOVREL_B32_pseudo<SReg_160>;
1044+
def S_INDIRECT_REG_WRITE_MOVREL_B32_V6 : S_INDIRECT_REG_WRITE_MOVREL_B32_pseudo<SReg_192>;
1045+
def S_INDIRECT_REG_WRITE_MOVREL_B32_V7 : S_INDIRECT_REG_WRITE_MOVREL_B32_pseudo<SReg_224>;
10421046
def S_INDIRECT_REG_WRITE_MOVREL_B32_V8 : S_INDIRECT_REG_WRITE_MOVREL_B32_pseudo<SReg_256>;
10431047
def S_INDIRECT_REG_WRITE_MOVREL_B32_V9 : S_INDIRECT_REG_WRITE_MOVREL_B32_pseudo<SReg_288>;
10441048
def S_INDIRECT_REG_WRITE_MOVREL_B32_V10 : S_INDIRECT_REG_WRITE_MOVREL_B32_pseudo<SReg_320>;
@@ -1071,6 +1075,8 @@ def V_INDIRECT_REG_WRITE_GPR_IDX_B32_V2 : V_INDIRECT_REG_WRITE_GPR_IDX_pseudo<VR
10711075
def V_INDIRECT_REG_WRITE_GPR_IDX_B32_V3 : V_INDIRECT_REG_WRITE_GPR_IDX_pseudo<VReg_96>;
10721076
def V_INDIRECT_REG_WRITE_GPR_IDX_B32_V4 : V_INDIRECT_REG_WRITE_GPR_IDX_pseudo<VReg_128>;
10731077
def V_INDIRECT_REG_WRITE_GPR_IDX_B32_V5 : V_INDIRECT_REG_WRITE_GPR_IDX_pseudo<VReg_160>;
1078+
def V_INDIRECT_REG_WRITE_GPR_IDX_B32_V6 : V_INDIRECT_REG_WRITE_GPR_IDX_pseudo<VReg_192>;
1079+
def V_INDIRECT_REG_WRITE_GPR_IDX_B32_V7 : V_INDIRECT_REG_WRITE_GPR_IDX_pseudo<VReg_224>;
10741080
def V_INDIRECT_REG_WRITE_GPR_IDX_B32_V8 : V_INDIRECT_REG_WRITE_GPR_IDX_pseudo<VReg_256>;
10751081
def V_INDIRECT_REG_WRITE_GPR_IDX_B32_V9 : V_INDIRECT_REG_WRITE_GPR_IDX_pseudo<VReg_288>;
10761082
def V_INDIRECT_REG_WRITE_GPR_IDX_B32_V10 : V_INDIRECT_REG_WRITE_GPR_IDX_pseudo<VReg_320>;
@@ -1091,6 +1097,8 @@ def V_INDIRECT_REG_READ_GPR_IDX_B32_V2 : V_INDIRECT_REG_READ_GPR_IDX_pseudo<VReg
10911097
def V_INDIRECT_REG_READ_GPR_IDX_B32_V3 : V_INDIRECT_REG_READ_GPR_IDX_pseudo<VReg_96>;
10921098
def V_INDIRECT_REG_READ_GPR_IDX_B32_V4 : V_INDIRECT_REG_READ_GPR_IDX_pseudo<VReg_128>;
10931099
def V_INDIRECT_REG_READ_GPR_IDX_B32_V5 : V_INDIRECT_REG_READ_GPR_IDX_pseudo<VReg_160>;
1100+
def V_INDIRECT_REG_READ_GPR_IDX_B32_V6 : V_INDIRECT_REG_READ_GPR_IDX_pseudo<VReg_192>;
1101+
def V_INDIRECT_REG_READ_GPR_IDX_B32_V7 : V_INDIRECT_REG_READ_GPR_IDX_pseudo<VReg_224>;
10941102
def V_INDIRECT_REG_READ_GPR_IDX_B32_V8 : V_INDIRECT_REG_READ_GPR_IDX_pseudo<VReg_256>;
10951103
def V_INDIRECT_REG_READ_GPR_IDX_B32_V9 : V_INDIRECT_REG_READ_GPR_IDX_pseudo<VReg_288>;
10961104
def V_INDIRECT_REG_READ_GPR_IDX_B32_V10 : V_INDIRECT_REG_READ_GPR_IDX_pseudo<VReg_320>;

‎llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-extract-vector-elt.mir‎

Lines changed: 126 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -964,3 +964,129 @@ body: |
964964
%2:vgpr(s32) = G_EXTRACT_VECTOR_ELT %0, %1
965965
S_ENDPGM 0, implicit %2
966966
...
967+
968+
---
969+
name: extract_vector_elt_s_s32_v6s32
970+
legalized: true
971+
regBankSelected: true
972+
973+
body: |
974+
bb.0:
975+
liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5, $sgpr6
976+
977+
; MOVREL-LABEL: name: extract_vector_elt_s_s32_v6s32
978+
; MOVREL: liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5, $sgpr6
979+
; MOVREL-NEXT: {{ $}}
980+
; MOVREL-NEXT: [[COPY:%[0-9]+]]:sgpr_192 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5
981+
; MOVREL-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr6
982+
; MOVREL-NEXT: $m0 = COPY [[COPY1]]
983+
; MOVREL-NEXT: [[S_MOVRELS_B32_:%[0-9]+]]:sreg_32 = S_MOVRELS_B32 [[COPY]].sub0, implicit $m0, implicit [[COPY]]
984+
; MOVREL-NEXT: S_ENDPGM 0, implicit [[S_MOVRELS_B32_]]
985+
;
986+
; GPRIDX-LABEL: name: extract_vector_elt_s_s32_v6s32
987+
; GPRIDX: liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5, $sgpr6
988+
; GPRIDX-NEXT: {{ $}}
989+
; GPRIDX-NEXT: [[COPY:%[0-9]+]]:sgpr_192 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5
990+
; GPRIDX-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr6
991+
; GPRIDX-NEXT: $m0 = COPY [[COPY1]]
992+
; GPRIDX-NEXT: [[S_MOVRELS_B32_:%[0-9]+]]:sreg_32 = S_MOVRELS_B32 [[COPY]].sub0, implicit $m0, implicit [[COPY]]
993+
; GPRIDX-NEXT: S_ENDPGM 0, implicit [[S_MOVRELS_B32_]]
994+
%0:sgpr(<6 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5
995+
%1:sgpr(s32) = COPY $sgpr6
996+
%2:sgpr(s32) = G_EXTRACT_VECTOR_ELT %0, %1
997+
S_ENDPGM 0, implicit %2
998+
...
999+
1000+
---
1001+
name: extract_vector_elt_s_s32_v7s32
1002+
legalized: true
1003+
regBankSelected: true
1004+
1005+
body: |
1006+
bb.0:
1007+
liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6, $sgpr7
1008+
1009+
; MOVREL-LABEL: name: extract_vector_elt_s_s32_v7s32
1010+
; MOVREL: liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6, $sgpr7
1011+
; MOVREL-NEXT: {{ $}}
1012+
; MOVREL-NEXT: [[COPY:%[0-9]+]]:sgpr_224 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6
1013+
; MOVREL-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr7
1014+
; MOVREL-NEXT: $m0 = COPY [[COPY1]]
1015+
; MOVREL-NEXT: [[S_MOVRELS_B32_:%[0-9]+]]:sreg_32 = S_MOVRELS_B32 [[COPY]].sub0, implicit $m0, implicit [[COPY]]
1016+
; MOVREL-NEXT: S_ENDPGM 0, implicit [[S_MOVRELS_B32_]]
1017+
;
1018+
; GPRIDX-LABEL: name: extract_vector_elt_s_s32_v7s32
1019+
; GPRIDX: liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6, $sgpr7
1020+
; GPRIDX-NEXT: {{ $}}
1021+
; GPRIDX-NEXT: [[COPY:%[0-9]+]]:sgpr_224 = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6
1022+
; GPRIDX-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr7
1023+
; GPRIDX-NEXT: $m0 = COPY [[COPY1]]
1024+
; GPRIDX-NEXT: [[S_MOVRELS_B32_:%[0-9]+]]:sreg_32 = S_MOVRELS_B32 [[COPY]].sub0, implicit $m0, implicit [[COPY]]
1025+
; GPRIDX-NEXT: S_ENDPGM 0, implicit [[S_MOVRELS_B32_]]
1026+
%0:sgpr(<7 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6
1027+
%1:sgpr(s32) = COPY $sgpr7
1028+
%2:sgpr(s32) = G_EXTRACT_VECTOR_ELT %0, %1
1029+
S_ENDPGM 0, implicit %2
1030+
...
1031+
1032+
---
1033+
name: extract_vector_elt_v_s32_v6s32
1034+
legalized: true
1035+
regBankSelected: true
1036+
1037+
body: |
1038+
bb.0:
1039+
liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5, $sgpr2
1040+
1041+
; MOVREL-LABEL: name: extract_vector_elt_v_s32_v6s32
1042+
; MOVREL: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5, $sgpr2
1043+
; MOVREL-NEXT: {{ $}}
1044+
; MOVREL-NEXT: [[COPY:%[0-9]+]]:vreg_192 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5
1045+
; MOVREL-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
1046+
; MOVREL-NEXT: $m0 = COPY [[COPY1]]
1047+
; MOVREL-NEXT: [[V_MOVRELS_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOVRELS_B32_e32 [[COPY]].sub0, implicit $m0, implicit $exec, implicit [[COPY]]
1048+
; MOVREL-NEXT: S_ENDPGM 0, implicit [[V_MOVRELS_B32_e32_]]
1049+
;
1050+
; GPRIDX-LABEL: name: extract_vector_elt_v_s32_v6s32
1051+
; GPRIDX: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5, $sgpr2
1052+
; GPRIDX-NEXT: {{ $}}
1053+
; GPRIDX-NEXT: [[COPY:%[0-9]+]]:vreg_192 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5
1054+
; GPRIDX-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
1055+
; GPRIDX-NEXT: [[V_INDIRECT_REG_READ_GPR_IDX_B32_V6_:%[0-9]+]]:vgpr_32 = V_INDIRECT_REG_READ_GPR_IDX_B32_V6 [[COPY]], [[COPY1]], 3, implicit-def $m0, implicit $m0, implicit $exec
1056+
; GPRIDX-NEXT: S_ENDPGM 0, implicit [[V_INDIRECT_REG_READ_GPR_IDX_B32_V6_]]
1057+
%0:vgpr(<6 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5
1058+
%1:sgpr(s32) = COPY $sgpr2
1059+
%2:vgpr(s32) = G_EXTRACT_VECTOR_ELT %0, %1
1060+
S_ENDPGM 0, implicit %2
1061+
...
1062+
1063+
---
1064+
name: extract_vector_elt_v_s32_v7s32
1065+
legalized: true
1066+
regBankSelected: true
1067+
1068+
body: |
1069+
bb.0:
1070+
liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6, $sgpr2
1071+
1072+
; MOVREL-LABEL: name: extract_vector_elt_v_s32_v7s32
1073+
; MOVREL: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6, $sgpr2
1074+
; MOVREL-NEXT: {{ $}}
1075+
; MOVREL-NEXT: [[COPY:%[0-9]+]]:vreg_224 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6
1076+
; MOVREL-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
1077+
; MOVREL-NEXT: $m0 = COPY [[COPY1]]
1078+
; MOVREL-NEXT: [[V_MOVRELS_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOVRELS_B32_e32 [[COPY]].sub0, implicit $m0, implicit $exec, implicit [[COPY]]
1079+
; MOVREL-NEXT: S_ENDPGM 0, implicit [[V_MOVRELS_B32_e32_]]
1080+
;
1081+
; GPRIDX-LABEL: name: extract_vector_elt_v_s32_v7s32
1082+
; GPRIDX: liveins: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6, $sgpr2
1083+
; GPRIDX-NEXT: {{ $}}
1084+
; GPRIDX-NEXT: [[COPY:%[0-9]+]]:vreg_224 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6
1085+
; GPRIDX-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2
1086+
; GPRIDX-NEXT: [[V_INDIRECT_REG_READ_GPR_IDX_B32_V7_:%[0-9]+]]:vgpr_32 = V_INDIRECT_REG_READ_GPR_IDX_B32_V7 [[COPY]], [[COPY1]], 3, implicit-def $m0, implicit $m0, implicit $exec
1087+
; GPRIDX-NEXT: S_ENDPGM 0, implicit [[V_INDIRECT_REG_READ_GPR_IDX_B32_V7_]]
1088+
%0:vgpr(<7 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6
1089+
%1:sgpr(s32) = COPY $sgpr2
1090+
%2:vgpr(s32) = G_EXTRACT_VECTOR_ELT %0, %1
1091+
S_ENDPGM 0, implicit %2
1092+
...

0 commit comments

Comments
 (0)