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[CodeGen] Add flags to RDDSP and WRDSP at emission time
This allows us to remove the hack that requires we remove the dead flag from the physical register.
1 parent 362594a commit c9e4f1a

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6 files changed

+64
-42
lines changed

6 files changed

+64
-42
lines changed

‎llvm/lib/CodeGen/LiveVariables.cpp

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -534,10 +534,6 @@ void LiveVariables::runOnInstr(MachineInstr &MI,
534534
UseRegs.push_back(MOReg);
535535
} else {
536536
assert(MO.isDef());
537-
// FIXME: We should not remove any dead flags. However the MIPS RDDSP
538-
// instruction needs it at the moment: http://llvm.org/PR27116.
539-
if (MOReg.isPhysical() && !MRI->isReserved(MOReg))
540-
MO.setIsDead(false);
541537
DefRegs.push_back(MOReg);
542538
}
543539
}

‎llvm/lib/Target/Mips/MipsDSPInstrInfo.td

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1470,3 +1470,11 @@ let AddedComplexity = 20 in {
14701470
let AdditionalPredicates = [NotInMicroMips] in {
14711471
def : DSPInstAlias<"wrdsp $rt", (WRDSP GPR32Opnd:$rt, 0x1F), 1>;
14721472
}
1473+
1474+
def RDDSP_Pseudo : Pseudo<(outs GPR32Opnd:$rd), (ins uimm10:$mask), []> {
1475+
let usesCustomInserter = 1;
1476+
}
1477+
1478+
def WRDSP_Pseudo : Pseudo<(outs), (ins GPR32Opnd:$rs, uimm10:$mask), []> {
1479+
let usesCustomInserter = 1;
1480+
}

‎llvm/lib/Target/Mips/MipsISelLowering.cpp

Lines changed: 51 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1411,6 +1411,53 @@ static MachineBasicBlock *insertDivByZeroTrap(MachineInstr &MI,
14111411
return &MBB;
14121412
}
14131413

1414+
MachineBasicBlock::iterator
1415+
MipsTargetLowering::emitRDDSP(MachineInstr &MI, MachineBasicBlock *BB) const {
1416+
const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1417+
unsigned DestReg = MI.getOperand(0).getReg();
1418+
unsigned Mask = MI.getOperand(1).getImm();
1419+
auto MIB = BuildMI(*BB, MI, MI.getDebugLoc(), TII.get(Mips::RDDSP), DestReg)
1420+
.addImm(Mask);
1421+
if (Mask & 1)
1422+
MIB.addReg(Mips::DSPPos, RegState::Implicit);
1423+
if (Mask & 2)
1424+
MIB.addReg(Mips::DSPSCount, RegState::Implicit);
1425+
if (Mask & 4)
1426+
MIB.addReg(Mips::DSPCarry, RegState::Implicit);
1427+
if (Mask & 8)
1428+
MIB.addReg(Mips::DSPOutFlag, RegState::Implicit);
1429+
if (Mask & 16)
1430+
MIB.addReg(Mips::DSPCCond, RegState::Implicit);
1431+
if (Mask & 32)
1432+
MIB.addReg(Mips::DSPEFI, RegState::Implicit);
1433+
MI.eraseFromParent();
1434+
return MIB;
1435+
}
1436+
1437+
MachineBasicBlock::iterator
1438+
MipsTargetLowering::emitWRDSP(MachineInstr &MI, MachineBasicBlock *BB) const {
1439+
const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1440+
unsigned SrcReg = MI.getOperand(0).getReg();
1441+
unsigned Mask = MI.getOperand(1).getImm();
1442+
auto MIB = BuildMI(*BB, MI, MI.getDebugLoc(), TII.get(Mips::WRDSP))
1443+
.addReg(SrcReg)
1444+
.addImm(Mask);
1445+
if (Mask & 1)
1446+
MIB.addReg(Mips::DSPPos, RegState::ImplicitDefine);
1447+
if (Mask & 2)
1448+
MIB.addReg(Mips::DSPSCount, RegState::ImplicitDefine);
1449+
if (Mask & 4)
1450+
MIB.addReg(Mips::DSPCarry, RegState::ImplicitDefine);
1451+
if (Mask & 8)
1452+
MIB.addReg(Mips::DSPOutFlag, RegState::ImplicitDefine);
1453+
if (Mask & 16)
1454+
MIB.addReg(Mips::DSPCCond, RegState::ImplicitDefine);
1455+
if (Mask & 32)
1456+
MIB.addReg(Mips::DSPEFI, RegState::ImplicitDefine);
1457+
MI.eraseFromParent();
1458+
return MIB;
1459+
}
1460+
14141461
MachineBasicBlock *
14151462
MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
14161463
MachineBasicBlock *BB) const {
@@ -1579,6 +1626,10 @@ MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
15791626
return emitSTR_W(MI, BB);
15801627
case Mips::STR_D:
15811628
return emitSTR_D(MI, BB);
1629+
case Mips::RDDSP_Pseudo:
1630+
return emitRDDSP(MI, BB);
1631+
case Mips::WRDSP_Pseudo:
1632+
return emitWRDSP(MI, BB);
15821633
}
15831634
}
15841635

‎llvm/lib/Target/Mips/MipsISelLowering.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -744,6 +744,8 @@ class TargetRegisterClass;
744744
MachineBasicBlock *emitLDR_D(MachineInstr &MI, MachineBasicBlock *BB) const;
745745
MachineBasicBlock *emitSTR_W(MachineInstr &MI, MachineBasicBlock *BB) const;
746746
MachineBasicBlock *emitSTR_D(MachineInstr &MI, MachineBasicBlock *BB) const;
747+
MachineBasicBlock *emitRDDSP(MachineInstr &MI, MachineBasicBlock *BB) const;
748+
MachineBasicBlock *emitWRDSP(MachineInstr &MI, MachineBasicBlock *BB) const;
747749
};
748750

749751
/// Create MipsTargetLowering objects.

‎llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp

Lines changed: 3 additions & 35 deletions
Original file line numberDiff line numberDiff line change
@@ -44,32 +44,6 @@ void MipsSEDAGToDAGISelLegacy::getAnalysisUsage(AnalysisUsage &AU) const {
4444
SelectionDAGISelLegacy::getAnalysisUsage(AU);
4545
}
4646

47-
void MipsSEDAGToDAGISel::addDSPCtrlRegOperands(bool IsDef, MachineInstr &MI,
48-
MachineFunction &MF) {
49-
MachineInstrBuilder MIB(MF, &MI);
50-
unsigned Mask = MI.getOperand(1).getImm();
51-
unsigned Flag =
52-
IsDef ? RegState::ImplicitDefine : RegState::Implicit | RegState::Undef;
53-
54-
if (Mask & 1)
55-
MIB.addReg(Mips::DSPPos, Flag);
56-
57-
if (Mask & 2)
58-
MIB.addReg(Mips::DSPSCount, Flag);
59-
60-
if (Mask & 4)
61-
MIB.addReg(Mips::DSPCarry, Flag);
62-
63-
if (Mask & 8)
64-
MIB.addReg(Mips::DSPOutFlag, Flag);
65-
66-
if (Mask & 16)
67-
MIB.addReg(Mips::DSPCCond, Flag);
68-
69-
if (Mask & 32)
70-
MIB.addReg(Mips::DSPEFI, Flag);
71-
}
72-
7347
MCRegister MipsSEDAGToDAGISel::getMSACtrlReg(const SDValue RegIdx) const {
7448
uint64_t RegNum = RegIdx->getAsZExtVal();
7549
return Mips::MSACtrlRegClass.getRegister(RegNum);
@@ -155,12 +129,6 @@ void MipsSEDAGToDAGISel::processFunctionAfterISel(MachineFunction &MF) {
155129
for (auto &MBB: MF) {
156130
for (auto &MI: MBB) {
157131
switch (MI.getOpcode()) {
158-
case Mips::RDDSP:
159-
addDSPCtrlRegOperands(false, MI, MF);
160-
break;
161-
case Mips::WRDSP:
162-
addDSPCtrlRegOperands(true, MI, MF);
163-
break;
164132
case Mips::BuildPairF64_64:
165133
case Mips::ExtractElementF64_64:
166134
if (!Subtarget->useOddSPReg()) {
@@ -231,8 +199,8 @@ void MipsSEDAGToDAGISel::selectAddE(SDNode *Node, const SDLoc &DL) const {
231199

232200
SDValue OuFlag = CurDAG->getTargetConstant(20, DL, MVT::i32);
233201

234-
SDNode *DSPCtrlField = CurDAG->getMachineNode(Mips::RDDSP, DL, MVT::i32,
235-
MVT::Glue, CstOne, InGlue);
202+
SDNode *DSPCtrlField = CurDAG->getMachineNode(
203+
Mips::RDDSP_Pseudo, DL, MVT::i32, MVT::Glue, CstOne, InGlue);
236204

237205
SDNode *Carry = CurDAG->getMachineNode(
238206
Mips::EXT, DL, MVT::i32, SDValue(DSPCtrlField, 0), OuFlag, CstOne);
@@ -253,7 +221,7 @@ void MipsSEDAGToDAGISel::selectAddE(SDNode *Node, const SDLoc &DL) const {
253221
SDNode *DSPCtrlFinal =
254222
CurDAG->getMachineNode(Mips::INS, DL, MVT::i32, InsOps);
255223

256-
SDNode *WrDSP = CurDAG->getMachineNode(Mips::WRDSP, DL, MVT::Glue,
224+
SDNode *WrDSP = CurDAG->getMachineNode(Mips::WRDSP_Pseudo, DL, MVT::Glue,
257225
SDValue(DSPCtrlFinal, 0), CstOne);
258226

259227
SDValue Operands[3] = {LHS, RHS, SDValue(WrDSP, 0)};

‎llvm/lib/Target/Mips/MipsSEISelDAGToDAG.h

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -27,9 +27,6 @@ class MipsSEDAGToDAGISel : public MipsDAGToDAGISel {
2727

2828
bool runOnMachineFunction(MachineFunction &MF) override;
2929

30-
void addDSPCtrlRegOperands(bool IsDef, MachineInstr &MI,
31-
MachineFunction &MF);
32-
3330
MCRegister getMSACtrlReg(const SDValue RegIdx) const;
3431

3532
bool replaceUsesWithZeroReg(MachineRegisterInfo *MRI, const MachineInstr&);

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