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[CodeGen] Consider imm offsets when sorting framerefs
LocalStackSlotAllocation pass disallows negative offsets wrt to a base register. The pass ends up introducing a new register for such frame references. This patch helps LocalStackSlotAlloca to additionally consider the immediate offset of an instruction, when sorting frame refs - hence, avoiding negative offsets and maximizing reuse of the existing registers. Resolves #155902
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5 files changed

+298
-43
lines changed

5 files changed

+298
-43
lines changed

‎llvm/lib/CodeGen/LocalStackSlotAllocation.cpp‎

Lines changed: 24 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -51,6 +51,7 @@ namespace {
5151
class FrameRef {
5252
MachineBasicBlock::iterator MI; // Instr referencing the frame
5353
int64_t LocalOffset; // Local offset of the frame idx referenced
54+
int64_t InstrOffset; // Offset of the instruction from the frame index
5455
int FrameIdx; // The frame index
5556

5657
// Order reference instruction appears in program. Used to ensure
@@ -59,16 +60,17 @@ namespace {
5960
unsigned Order;
6061

6162
public:
62-
FrameRef(MachineInstr *I, int64_t Offset, int Idx, unsigned Ord) :
63-
MI(I), LocalOffset(Offset), FrameIdx(Idx), Order(Ord) {}
63+
FrameRef(MachineInstr *I, int64_t Offset, int64_t InstrOffset, int Idx, unsigned Ord) :
64+
MI(I), LocalOffset(Offset), InstrOffset(InstrOffset), FrameIdx(Idx), Order(Ord) {}
6465

6566
bool operator<(const FrameRef &RHS) const {
66-
return std::tie(LocalOffset, FrameIdx, Order) <
67-
std::tie(RHS.LocalOffset, RHS.FrameIdx, RHS.Order);
67+
return std::make_tuple(LocalOffset + InstrOffset, FrameIdx, Order) <
68+
std::make_tuple(RHS.LocalOffset + RHS.InstrOffset, RHS.FrameIdx, RHS.Order);
6869
}
6970

7071
MachineBasicBlock::iterator getMachineInstr() const { return MI; }
7172
int64_t getLocalOffset() const { return LocalOffset; }
73+
int64_t getInstrOffset() const { return InstrOffset; }
7274
int getFrameIndex() const { return FrameIdx; }
7375
};
7476

@@ -335,20 +337,27 @@ bool LocalStackSlotImpl::insertFrameReferenceRegisters(MachineFunction &Fn) {
335337
// than that, but the increased register pressure makes that a
336338
// tricky thing to balance. Investigate if re-materializing these
337339
// becomes an issue.
338-
for (const MachineOperand &MO : MI.operands()) {
340+
for (unsigned OpIdx = 0, OpEnd = MI.getNumOperands(); OpIdx != OpEnd;
341+
++OpIdx) {
342+
const MachineOperand &MO = MI.getOperand(OpIdx);
339343
// Consider replacing all frame index operands that reference
340344
// an object allocated in the local block.
341-
if (MO.isFI()) {
342-
// Don't try this with values not in the local block.
343-
if (!MFI.isObjectPreAllocated(MO.getIndex()))
344-
break;
345-
int Idx = MO.getIndex();
346-
int64_t LocalOffset = LocalOffsets[Idx];
347-
if (!TRI->needsFrameBaseReg(&MI, LocalOffset))
348-
break;
349-
FrameReferenceInsns.push_back(FrameRef(&MI, LocalOffset, Idx, Order++));
345+
if (!MO.isFI())
346+
continue;
347+
348+
int FrameIdx = MO.getIndex();
349+
// Don't try this with values not in the local block.
350+
if (!MFI.isObjectPreAllocated(FrameIdx))
351+
break;
352+
353+
int64_t LocalOffset = LocalOffsets[FrameIdx];
354+
if (!TRI->needsFrameBaseReg(&MI, LocalOffset))
350355
break;
351-
}
356+
357+
int64_t InstrOffset = TRI->getFrameIndexInstrOffset(&MI, OpIdx);
358+
FrameReferenceInsns.emplace_back(&MI, LocalOffset, InstrOffset,
359+
FrameIdx, Order++);
360+
break;
352361
}
353362
}
354363
}

‎llvm/test/CodeGen/AMDGPU/flat-scratch-neg-offset-bug-155902.ll‎

Lines changed: 230 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,230 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
2+
; RUN: llc -O0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx950 < %s | FileCheck %s --check-prefix=GFX950
3+
4+
; Ensure we don't crash with: "Cannot scavenge register in FI elimination!"
5+
define amdgpu_kernel void @issue155902(i64 %arg, i64 %arg1, i64 %arg2, i64 %arg3, i64 %arg4, i64 %arg5, i64 %arg6, i64 %arg7, i64 %arg8, i64 %arg9, i64 %arg10, i64 %arg11, i64 %arg12, i64 %arg13, i64 %arg14, i64 %arg15, i64 %arg16, i64 %arg17, i64 %arg18, i64 %arg19, i64 %arg20, i64 %arg21, i64 %arg22, i64 %arg23, i64 %arg24, i64 %arg25, i64 %arg26, i64 %arg27, i64 %arg28, i64 %arg29, i64 %arg30, i64 %arg31, i64 %arg32, i64 %arg33, i64 %arg34, i64 %arg35, i64 %arg36, i64 %arg37, i64 %arg38, i64 %arg39, i64 %arg40, i64 %arg41, i64 %arg42, i64 %arg43, i64 %arg44, i64 %arg45, i64 %arg46, i64 %arg47, i64 %arg48, i64 %arg49) {
6+
; GFX950-LABEL: issue155902:
7+
; GFX950: ; %bb.0: ; %bb
8+
; GFX950-NEXT: s_mov_b32 s33, 0x4008
9+
; GFX950-NEXT: s_mov_b64 s[2:3], s[4:5]
10+
; GFX950-NEXT: s_load_dwordx2 s[0:1], s[2:3], 0x0
11+
; GFX950-NEXT: s_load_dwordx2 vcc, s[2:3], 0x8
12+
; GFX950-NEXT: s_load_dwordx2 s[98:99], s[2:3], 0x10
13+
; GFX950-NEXT: s_load_dwordx2 s[96:97], s[2:3], 0x18
14+
; GFX950-NEXT: s_load_dwordx2 s[94:95], s[2:3], 0x20
15+
; GFX950-NEXT: s_load_dwordx2 s[92:93], s[2:3], 0x28
16+
; GFX950-NEXT: s_load_dwordx2 s[90:91], s[2:3], 0x30
17+
; GFX950-NEXT: s_load_dwordx2 s[88:89], s[2:3], 0x38
18+
; GFX950-NEXT: s_load_dwordx2 s[86:87], s[2:3], 0x40
19+
; GFX950-NEXT: s_load_dwordx2 s[84:85], s[2:3], 0x48
20+
; GFX950-NEXT: s_load_dwordx2 s[82:83], s[2:3], 0x50
21+
; GFX950-NEXT: s_load_dwordx2 s[80:81], s[2:3], 0x58
22+
; GFX950-NEXT: s_load_dwordx2 s[78:79], s[2:3], 0x60
23+
; GFX950-NEXT: s_load_dwordx2 s[76:77], s[2:3], 0x68
24+
; GFX950-NEXT: s_load_dwordx2 s[74:75], s[2:3], 0x70
25+
; GFX950-NEXT: s_load_dwordx2 s[72:73], s[2:3], 0x78
26+
; GFX950-NEXT: s_load_dwordx2 s[70:71], s[2:3], 0x80
27+
; GFX950-NEXT: s_load_dwordx2 s[68:69], s[2:3], 0x88
28+
; GFX950-NEXT: s_load_dwordx2 s[66:67], s[2:3], 0x90
29+
; GFX950-NEXT: s_load_dwordx2 s[64:65], s[2:3], 0x98
30+
; GFX950-NEXT: s_load_dwordx2 s[62:63], s[2:3], 0xa0
31+
; GFX950-NEXT: s_load_dwordx2 s[60:61], s[2:3], 0xa8
32+
; GFX950-NEXT: s_load_dwordx2 s[58:59], s[2:3], 0xb0
33+
; GFX950-NEXT: s_load_dwordx2 s[56:57], s[2:3], 0xb8
34+
; GFX950-NEXT: s_load_dwordx2 s[54:55], s[2:3], 0xc0
35+
; GFX950-NEXT: s_load_dwordx2 s[52:53], s[2:3], 0xc8
36+
; GFX950-NEXT: s_load_dwordx2 s[50:51], s[2:3], 0xd0
37+
; GFX950-NEXT: s_load_dwordx2 s[48:49], s[2:3], 0xd8
38+
; GFX950-NEXT: s_load_dwordx2 s[46:47], s[2:3], 0xe0
39+
; GFX950-NEXT: s_load_dwordx2 s[44:45], s[2:3], 0xe8
40+
; GFX950-NEXT: s_load_dwordx2 s[42:43], s[2:3], 0xf0
41+
; GFX950-NEXT: s_load_dwordx2 s[40:41], s[2:3], 0xf8
42+
; GFX950-NEXT: s_load_dwordx2 s[38:39], s[2:3], 0x100
43+
; GFX950-NEXT: s_load_dwordx2 s[36:37], s[2:3], 0x108
44+
; GFX950-NEXT: s_load_dwordx2 s[34:35], s[2:3], 0x110
45+
; GFX950-NEXT: s_load_dwordx2 s[30:31], s[2:3], 0x118
46+
; GFX950-NEXT: s_load_dwordx2 s[28:29], s[2:3], 0x120
47+
; GFX950-NEXT: s_load_dwordx2 s[26:27], s[2:3], 0x128
48+
; GFX950-NEXT: s_load_dwordx2 s[24:25], s[2:3], 0x130
49+
; GFX950-NEXT: s_load_dwordx2 s[22:23], s[2:3], 0x138
50+
; GFX950-NEXT: s_load_dwordx2 s[20:21], s[2:3], 0x140
51+
; GFX950-NEXT: s_load_dwordx2 s[18:19], s[2:3], 0x148
52+
; GFX950-NEXT: s_load_dwordx2 s[16:17], s[2:3], 0x150
53+
; GFX950-NEXT: s_load_dwordx2 s[14:15], s[2:3], 0x158
54+
; GFX950-NEXT: s_load_dwordx2 s[12:13], s[2:3], 0x160
55+
; GFX950-NEXT: s_load_dwordx2 s[10:11], s[2:3], 0x168
56+
; GFX950-NEXT: s_load_dwordx2 s[8:9], s[2:3], 0x170
57+
; GFX950-NEXT: s_load_dwordx2 s[6:7], s[2:3], 0x178
58+
; GFX950-NEXT: s_load_dwordx2 s[4:5], s[2:3], 0x180
59+
; GFX950-NEXT: s_nop 0
60+
; GFX950-NEXT: s_load_dwordx2 s[2:3], s[2:3], 0x188
61+
; GFX950-NEXT: v_mov_b64_e32 v[0:1], 0
62+
; GFX950-NEXT: scratch_store_dwordx2 off, v[0:1], s33 offset:8
63+
; GFX950-NEXT: scratch_store_dwordx2 off, v[0:1], s33
64+
; GFX950-NEXT: v_mov_b64_e32 v[0:1], 0x384
65+
; GFX950-NEXT: scratch_store_dwordx2 off, v[0:1], s33 offset:16
66+
; GFX950-NEXT: s_mov_b32 s33, 0
67+
; GFX950-NEXT: ; implicit-def: $vgpr2 : SGPR spill to VGPR lane
68+
; GFX950-NEXT: v_writelane_b32 v2, s33, 0
69+
; GFX950-NEXT: s_waitcnt lgkmcnt(0)
70+
; GFX950-NEXT: v_mov_b64_e32 v[0:1], s[0:1]
71+
; GFX950-NEXT: v_readlane_b32 s0, v2, 0
72+
; GFX950-NEXT: s_nop 4
73+
; GFX950-NEXT: scratch_store_dwordx2 off, v[0:1], s0
74+
; GFX950-NEXT: v_mov_b64_e32 v[0:1], vcc
75+
; GFX950-NEXT: scratch_store_dwordx2 off, v[0:1], s0
76+
; GFX950-NEXT: v_mov_b64_e32 v[0:1], s[98:99]
77+
; GFX950-NEXT: scratch_store_dwordx2 off, v[0:1], s0
78+
; GFX950-NEXT: v_mov_b64_e32 v[0:1], s[96:97]
79+
; GFX950-NEXT: scratch_store_dwordx2 off, v[0:1], s0
80+
; GFX950-NEXT: v_mov_b64_e32 v[0:1], s[94:95]
81+
; GFX950-NEXT: scratch_store_dwordx2 off, v[0:1], s0
82+
; GFX950-NEXT: v_mov_b64_e32 v[0:1], s[92:93]
83+
; GFX950-NEXT: scratch_store_dwordx2 off, v[0:1], s0
84+
; GFX950-NEXT: v_mov_b64_e32 v[0:1], s[90:91]
85+
; GFX950-NEXT: scratch_store_dwordx2 off, v[0:1], s0
86+
; GFX950-NEXT: v_mov_b64_e32 v[0:1], s[88:89]
87+
; GFX950-NEXT: scratch_store_dwordx2 off, v[0:1], s0
88+
; GFX950-NEXT: v_mov_b64_e32 v[0:1], s[86:87]
89+
; GFX950-NEXT: scratch_store_dwordx2 off, v[0:1], s0
90+
; GFX950-NEXT: v_mov_b64_e32 v[0:1], s[84:85]
91+
; GFX950-NEXT: scratch_store_dwordx2 off, v[0:1], s0
92+
; GFX950-NEXT: v_mov_b64_e32 v[0:1], s[82:83]
93+
; GFX950-NEXT: scratch_store_dwordx2 off, v[0:1], s0
94+
; GFX950-NEXT: v_mov_b64_e32 v[0:1], s[80:81]
95+
; GFX950-NEXT: scratch_store_dwordx2 off, v[0:1], s0
96+
; GFX950-NEXT: v_mov_b64_e32 v[0:1], s[78:79]
97+
; GFX950-NEXT: scratch_store_dwordx2 off, v[0:1], s0
98+
; GFX950-NEXT: v_mov_b64_e32 v[0:1], s[76:77]
99+
; GFX950-NEXT: scratch_store_dwordx2 off, v[0:1], s0
100+
; GFX950-NEXT: v_mov_b64_e32 v[0:1], s[74:75]
101+
; GFX950-NEXT: scratch_store_dwordx2 off, v[0:1], s0
102+
; GFX950-NEXT: v_mov_b64_e32 v[0:1], s[72:73]
103+
; GFX950-NEXT: scratch_store_dwordx2 off, v[0:1], s0
104+
; GFX950-NEXT: v_mov_b64_e32 v[0:1], s[70:71]
105+
; GFX950-NEXT: scratch_store_dwordx2 off, v[0:1], s0
106+
; GFX950-NEXT: v_mov_b64_e32 v[0:1], s[68:69]
107+
; GFX950-NEXT: scratch_store_dwordx2 off, v[0:1], s0
108+
; GFX950-NEXT: v_mov_b64_e32 v[0:1], s[66:67]
109+
; GFX950-NEXT: scratch_store_dwordx2 off, v[0:1], s0
110+
; GFX950-NEXT: v_mov_b64_e32 v[0:1], s[64:65]
111+
; GFX950-NEXT: scratch_store_dwordx2 off, v[0:1], s0
112+
; GFX950-NEXT: v_mov_b64_e32 v[0:1], s[62:63]
113+
; GFX950-NEXT: scratch_store_dwordx2 off, v[0:1], s0
114+
; GFX950-NEXT: v_mov_b64_e32 v[0:1], s[60:61]
115+
; GFX950-NEXT: scratch_store_dwordx2 off, v[0:1], s0
116+
; GFX950-NEXT: v_mov_b64_e32 v[0:1], s[58:59]
117+
; GFX950-NEXT: scratch_store_dwordx2 off, v[0:1], s0
118+
; GFX950-NEXT: v_mov_b64_e32 v[0:1], s[56:57]
119+
; GFX950-NEXT: scratch_store_dwordx2 off, v[0:1], s0
120+
; GFX950-NEXT: v_mov_b64_e32 v[0:1], s[54:55]
121+
; GFX950-NEXT: scratch_store_dwordx2 off, v[0:1], s0
122+
; GFX950-NEXT: v_mov_b64_e32 v[0:1], s[52:53]
123+
; GFX950-NEXT: scratch_store_dwordx2 off, v[0:1], s0
124+
; GFX950-NEXT: v_mov_b64_e32 v[0:1], s[50:51]
125+
; GFX950-NEXT: scratch_store_dwordx2 off, v[0:1], s0
126+
; GFX950-NEXT: v_mov_b64_e32 v[0:1], s[48:49]
127+
; GFX950-NEXT: scratch_store_dwordx2 off, v[0:1], s0
128+
; GFX950-NEXT: v_mov_b64_e32 v[0:1], s[46:47]
129+
; GFX950-NEXT: scratch_store_dwordx2 off, v[0:1], s0
130+
; GFX950-NEXT: v_mov_b64_e32 v[0:1], s[44:45]
131+
; GFX950-NEXT: scratch_store_dwordx2 off, v[0:1], s0
132+
; GFX950-NEXT: v_mov_b64_e32 v[0:1], s[42:43]
133+
; GFX950-NEXT: scratch_store_dwordx2 off, v[0:1], s0
134+
; GFX950-NEXT: v_mov_b64_e32 v[0:1], s[40:41]
135+
; GFX950-NEXT: scratch_store_dwordx2 off, v[0:1], s0
136+
; GFX950-NEXT: v_mov_b64_e32 v[0:1], s[38:39]
137+
; GFX950-NEXT: scratch_store_dwordx2 off, v[0:1], s0
138+
; GFX950-NEXT: v_mov_b64_e32 v[0:1], s[36:37]
139+
; GFX950-NEXT: scratch_store_dwordx2 off, v[0:1], s0
140+
; GFX950-NEXT: v_mov_b64_e32 v[0:1], s[34:35]
141+
; GFX950-NEXT: scratch_store_dwordx2 off, v[0:1], s0
142+
; GFX950-NEXT: v_mov_b64_e32 v[0:1], s[30:31]
143+
; GFX950-NEXT: scratch_store_dwordx2 off, v[0:1], s0
144+
; GFX950-NEXT: v_mov_b64_e32 v[0:1], s[28:29]
145+
; GFX950-NEXT: scratch_store_dwordx2 off, v[0:1], s0
146+
; GFX950-NEXT: v_mov_b64_e32 v[0:1], s[26:27]
147+
; GFX950-NEXT: scratch_store_dwordx2 off, v[0:1], s0
148+
; GFX950-NEXT: v_mov_b64_e32 v[0:1], s[24:25]
149+
; GFX950-NEXT: scratch_store_dwordx2 off, v[0:1], s0
150+
; GFX950-NEXT: v_mov_b64_e32 v[0:1], s[22:23]
151+
; GFX950-NEXT: scratch_store_dwordx2 off, v[0:1], s0
152+
; GFX950-NEXT: v_mov_b64_e32 v[0:1], s[20:21]
153+
; GFX950-NEXT: scratch_store_dwordx2 off, v[0:1], s0
154+
; GFX950-NEXT: v_mov_b64_e32 v[0:1], s[18:19]
155+
; GFX950-NEXT: scratch_store_dwordx2 off, v[0:1], s0
156+
; GFX950-NEXT: v_mov_b64_e32 v[0:1], s[16:17]
157+
; GFX950-NEXT: scratch_store_dwordx2 off, v[0:1], s0
158+
; GFX950-NEXT: v_mov_b64_e32 v[0:1], s[14:15]
159+
; GFX950-NEXT: scratch_store_dwordx2 off, v[0:1], s0
160+
; GFX950-NEXT: v_mov_b64_e32 v[0:1], s[12:13]
161+
; GFX950-NEXT: scratch_store_dwordx2 off, v[0:1], s0
162+
; GFX950-NEXT: v_mov_b64_e32 v[0:1], s[10:11]
163+
; GFX950-NEXT: scratch_store_dwordx2 off, v[0:1], s0
164+
; GFX950-NEXT: v_mov_b64_e32 v[0:1], s[8:9]
165+
; GFX950-NEXT: scratch_store_dwordx2 off, v[0:1], s0
166+
; GFX950-NEXT: v_mov_b64_e32 v[0:1], s[6:7]
167+
; GFX950-NEXT: scratch_store_dwordx2 off, v[0:1], s0
168+
; GFX950-NEXT: v_mov_b64_e32 v[0:1], s[4:5]
169+
; GFX950-NEXT: scratch_store_dwordx2 off, v[0:1], s0
170+
; GFX950-NEXT: v_mov_b64_e32 v[0:1], s[2:3]
171+
; GFX950-NEXT: scratch_store_dwordx2 off, v[0:1], s0
172+
; GFX950-NEXT: s_endpgm
173+
bb:
174+
%alloca.big = alloca [4096 x i32], align 4, addrspace(5)
175+
%alloca304 = alloca [2 x i64], align 8, addrspace(5)
176+
%alloca307 = alloca i64, align 8, addrspace(5)
177+
store [2 x i64] zeroinitializer, ptr addrspace(5) %alloca304, align 8
178+
store i64 900, ptr addrspace(5) %alloca307, align 8
179+
store i64 %arg, ptr addrspace(5) null, align 8
180+
store i64 %arg1, ptr addrspace(5) null, align 8
181+
store i64 %arg2, ptr addrspace(5) null, align 8
182+
store i64 %arg3, ptr addrspace(5) null, align 8
183+
store i64 %arg4, ptr addrspace(5) null, align 8
184+
store i64 %arg5, ptr addrspace(5) null, align 8
185+
store i64 %arg6, ptr addrspace(5) null, align 8
186+
store i64 %arg7, ptr addrspace(5) null, align 8
187+
store i64 %arg8, ptr addrspace(5) null, align 8
188+
store i64 %arg9, ptr addrspace(5) null, align 8
189+
store i64 %arg10, ptr addrspace(5) null, align 8
190+
store i64 %arg11, ptr addrspace(5) null, align 8
191+
store i64 %arg12, ptr addrspace(5) null, align 8
192+
store i64 %arg13, ptr addrspace(5) null, align 8
193+
store i64 %arg14, ptr addrspace(5) null, align 8
194+
store i64 %arg15, ptr addrspace(5) null, align 8
195+
store i64 %arg16, ptr addrspace(5) null, align 8
196+
store i64 %arg17, ptr addrspace(5) null, align 8
197+
store i64 %arg18, ptr addrspace(5) null, align 8
198+
store i64 %arg19, ptr addrspace(5) null, align 8
199+
store i64 %arg20, ptr addrspace(5) null, align 8
200+
store i64 %arg21, ptr addrspace(5) null, align 8
201+
store i64 %arg22, ptr addrspace(5) null, align 8
202+
store i64 %arg23, ptr addrspace(5) null, align 8
203+
store i64 %arg24, ptr addrspace(5) null, align 8
204+
store i64 %arg25, ptr addrspace(5) null, align 8
205+
store i64 %arg26, ptr addrspace(5) null, align 8
206+
store i64 %arg27, ptr addrspace(5) null, align 8
207+
store i64 %arg28, ptr addrspace(5) null, align 8
208+
store i64 %arg29, ptr addrspace(5) null, align 8
209+
store i64 %arg30, ptr addrspace(5) null, align 8
210+
store i64 %arg31, ptr addrspace(5) null, align 8
211+
store i64 %arg32, ptr addrspace(5) null, align 8
212+
store i64 %arg33, ptr addrspace(5) null, align 8
213+
store i64 %arg34, ptr addrspace(5) null, align 8
214+
store i64 %arg35, ptr addrspace(5) null, align 8
215+
store i64 %arg36, ptr addrspace(5) null, align 8
216+
store i64 %arg37, ptr addrspace(5) null, align 8
217+
store i64 %arg38, ptr addrspace(5) null, align 8
218+
store i64 %arg39, ptr addrspace(5) null, align 8
219+
store i64 %arg40, ptr addrspace(5) null, align 8
220+
store i64 %arg41, ptr addrspace(5) null, align 8
221+
store i64 %arg42, ptr addrspace(5) null, align 8
222+
store i64 %arg43, ptr addrspace(5) null, align 8
223+
store i64 %arg44, ptr addrspace(5) null, align 8
224+
store i64 %arg45, ptr addrspace(5) null, align 8
225+
store i64 %arg46, ptr addrspace(5) null, align 8
226+
store i64 %arg47, ptr addrspace(5) null, align 8
227+
store i64 %arg48, ptr addrspace(5) null, align 8
228+
store i64 %arg49, ptr addrspace(5) null, align 8
229+
ret void
230+
}

‎llvm/test/CodeGen/AMDGPU/local-stack-alloc-add-references.gfx10.mir‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -49,15 +49,15 @@ machineFunctionInfo:
4949
body: |
5050
bb.0:
5151
; GFX10-LABEL: name: local_stack_alloc__v_add_u32_e64__literal_offsets_commute
52-
; GFX10: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 256
52+
; GFX10: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 100
5353
; GFX10-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
5454
; GFX10-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 killed [[S_MOV_B32_]], [[V_MOV_B32_e32_]], 0, implicit $exec
55-
; GFX10-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[V_ADD_U32_e64_]]
56-
; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[COPY]]
57-
; GFX10-NEXT: [[V_ADD_U32_e64_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 256, [[V_ADD_U32_e64_]], 0, implicit $exec
55+
; GFX10-NEXT: [[V_ADD_U32_e64_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 156, [[V_ADD_U32_e64_]], 0, implicit $exec
5856
; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_1]]
59-
; GFX10-NEXT: [[V_ADD_U32_e64_2:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[V_ADD_U32_e64_]], -156, 0, implicit $exec
57+
; GFX10-NEXT: [[V_ADD_U32_e64_2:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 412, [[V_ADD_U32_e64_]], 0, implicit $exec
6058
; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[V_ADD_U32_e64_2]]
59+
; GFX10-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[V_ADD_U32_e64_]]
60+
; GFX10-NEXT: INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 1245193 /* reguse:VGPR_32 */, [[COPY]]
6161
; GFX10-NEXT: SI_RETURN
6262
;
6363
; GFX12-LABEL: name: local_stack_alloc__v_add_u32_e64__literal_offsets_commute

‎llvm/test/CodeGen/AMDGPU/local-stack-alloc-block-sp-reference.ll‎

Lines changed: 6 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -294,25 +294,26 @@ define amdgpu_kernel void @local_stack_offset_uses_sp_flat(ptr addrspace(1) %out
294294
; FLATSCR-NEXT: s_add_u32 flat_scratch_lo, s8, s13
295295
; FLATSCR-NEXT: s_addc_u32 flat_scratch_hi, s9, 0
296296
; FLATSCR-NEXT: v_mov_b32_e32 v0, 0
297-
; FLATSCR-NEXT: s_mov_b32 s0, 0
298-
; FLATSCR-NEXT: scratch_store_dword off, v0, s0 offset:1024
297+
; FLATSCR-NEXT: s_movk_i32 s0, 0x2000
298+
; FLATSCR-NEXT: scratch_store_dword off, v0, s0
299299
; FLATSCR-NEXT: s_waitcnt vmcnt(0)
300+
; FLATSCR-NEXT: s_mov_b32 s0, 0
300301
; FLATSCR-NEXT: .LBB2_1: ; %loadstoreloop
301302
; FLATSCR-NEXT: ; =>This Inner Loop Header: Depth=1
302-
; FLATSCR-NEXT: s_add_i32 s1, s0, 0x2000
303+
; FLATSCR-NEXT: s_add_i32 s1, s0, 0x4000
303304
; FLATSCR-NEXT: s_add_i32 s0, s0, 1
304305
; FLATSCR-NEXT: s_cmpk_lt_u32 s0, 0x2120
305306
; FLATSCR-NEXT: scratch_store_byte off, v0, s1
306307
; FLATSCR-NEXT: s_waitcnt vmcnt(0)
307308
; FLATSCR-NEXT: s_cbranch_scc1 .LBB2_1
308309
; FLATSCR-NEXT: ; %bb.2: ; %split
309310
; FLATSCR-NEXT: s_movk_i32 s0, 0x1000
310-
; FLATSCR-NEXT: s_addk_i32 s0, 0x2000
311+
; FLATSCR-NEXT: s_addk_i32 s0, 0x4000
311312
; FLATSCR-NEXT: scratch_load_dwordx2 v[8:9], off, s0 offset:720 glc
312313
; FLATSCR-NEXT: s_waitcnt vmcnt(0)
313314
; FLATSCR-NEXT: scratch_load_dwordx4 v[0:3], off, s0 offset:704 glc
314315
; FLATSCR-NEXT: s_waitcnt vmcnt(0)
315-
; FLATSCR-NEXT: s_movk_i32 s0, 0x2000
316+
; FLATSCR-NEXT: s_movk_i32 s0, 0x4000
316317
; FLATSCR-NEXT: scratch_load_dwordx2 v[10:11], off, s0 offset:16 glc
317318
; FLATSCR-NEXT: s_waitcnt vmcnt(0)
318319
; FLATSCR-NEXT: scratch_load_dwordx4 v[4:7], off, s0 glc

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