@@ -1442,16 +1442,16 @@ const char *g_invalidate_q13[] { "q13", "d26", "d27", NULL };
14421442const char *g_invalidate_q14[] { " q14" , " d28" , " d29" , NULL };
14431443const char *g_invalidate_q15[] { " q15" , " d30" , " d31" , NULL };
14441444
1445- #define VFP_S_OFFSET_IDX (idx ) (offsetof (DNBArchMachARM::FPU, __r[ (idx)]) + offsetof (DNBArchMachARM::Context, vfp))
1446- #define VFP_D_OFFSET_IDX (idx ) (VFP_S_OFFSET_IDX ((idx) * 2 ))
1445+ #define VFP_S_OFFSET_IDX (idx ) (( (idx) % 4 ) * 4 ) // offset into q reg: 0, 4, 8, 12
1446+ #define VFP_D_OFFSET_IDX (idx ) (((idx) % 2 ) * 8 ) // offset into q reg: 0, 8
14471447#define VFP_Q_OFFSET_IDX (idx ) (VFP_S_OFFSET_IDX ((idx) * 4 ))
14481448
14491449#define VFP_OFFSET_NAME (reg ) (offsetof (DNBArchMachARM::FPU, __##reg) + offsetof (DNBArchMachARM::Context, vfp))
14501450
14511451#define FLOAT_FORMAT Float
14521452
1453- #define DEFINE_VFP_S_IDX (idx ) e_regSetVFP, vfp_s##idx, " s" #idx, NULL , IEEE754, FLOAT_FORMAT, 4 , 0 , INVALID_NUB_REGNUM, dwarf_s##idx, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM
1454- #define DEFINE_VFP_D_IDX (idx ) e_regSetVFP, vfp_d##idx, " d" #idx, NULL , IEEE754, FLOAT_FORMAT, 8 , 0 , INVALID_NUB_REGNUM, dwarf_d##idx, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM
1453+ #define DEFINE_VFP_S_IDX (idx ) e_regSetVFP, vfp_s##idx, " s" #idx, NULL , IEEE754, FLOAT_FORMAT, 4 , VFP_S_OFFSET_IDX(idx) , INVALID_NUB_REGNUM, dwarf_s##idx, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM
1454+ #define DEFINE_VFP_D_IDX (idx ) e_regSetVFP, vfp_d##idx, " d" #idx, NULL , IEEE754, FLOAT_FORMAT, 8 , VFP_D_OFFSET_IDX(idx) , INVALID_NUB_REGNUM, dwarf_d##idx, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM
14551455#define DEFINE_VFP_Q_IDX (idx ) e_regSetVFP, vfp_q##idx, " q" #idx, NULL , Vector, VectorOfUInt8, 16 , VFP_Q_OFFSET_IDX(idx), INVALID_NUB_REGNUM, dwarf_q##idx, INVALID_NUB_REGNUM, INVALID_NUB_REGNUM
14561456
14571457// Floating point registers
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