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ukalappa-mipsukalappa-mips
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Made the following changes like
 a)Refactored the code for proper indent with clang format. b)Emit ADDI for 11 bits unsigned immediate offset . c)Removed the DecodeSImm definition (not used). d)Updated the testcase.
1 parent 96d7bde commit fd02230

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8 files changed

+40
-72
lines changed

8 files changed

+40
-72
lines changed

‎llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp

Lines changed: 0 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -535,19 +535,6 @@ static DecodeStatus decodeRTZArg(MCInst &Inst, uint32_t Imm, int64_t Address,
535535
Inst.addOperand(MCOperand::createImm(Imm));
536536
return MCDisassembler::Success;
537537
}
538-
template <int Bits>
539-
static DecodeStatus DecodeSImm(MCInst &Inst, uint64_t Imm, uint64_t Address,
540-
const MCDisassembler *Decoder) {
541-
if (Imm & ~((1LL << Bits) - 1))
542-
return MCDisassembler::Fail;
543-
544-
// Imm is a signed immediate, so sign extend it.
545-
if (Imm & (1 << (Bits - 1)))
546-
Imm |= ~((1LL << Bits) - 1);
547-
548-
Inst.addOperand(MCOperand::createImm(Imm));
549-
return MCDisassembler::Success;
550-
}
551538

552539
static DecodeStatus decodeRVCInstrRdRs1ImmZero(MCInst &Inst, uint32_t Insn,
553540
uint64_t Address,
@@ -589,9 +576,6 @@ static DecodeStatus decodeXqccmpRlistS0(MCInst &Inst, uint32_t Imm,
589576
static DecodeStatus decodeCSSPushPopchk(MCInst &Inst, uint32_t Insn,
590577
uint64_t Address,
591578
const MCDisassembler *Decoder);
592-
template <int Bits>
593-
static DecodeStatus DecodeSImm(MCInst &Inst, uint64_t Imm, uint64_t Address,
594-
const MCDisassembler *Decoder);
595579

596580
#include "RISCVGenDisassemblerTables.inc"
597581

‎llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

Lines changed: 4 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -2926,7 +2926,7 @@ bool RISCVDAGToDAGISel::SelectAddrRegImm(SDValue Addr, SDValue &Base,
29262926
}
29272927

29282928
/// Similar to SelectAddrRegImm, except that the offset restricted for
2929-
/// nine bits.
2929+
/// unsinged nine bits.
29302930
bool RISCVDAGToDAGISel::SelectAddrRegImm9(SDValue Addr, SDValue &Base,
29312931
SDValue &Offset) {
29322932
if (SelectAddrFrameIndex(Addr, Base, Offset))
@@ -2936,7 +2936,6 @@ bool RISCVDAGToDAGISel::SelectAddrRegImm9(SDValue Addr, SDValue &Base,
29362936
MVT VT = Addr.getSimpleValueType();
29372937

29382938
if (CurDAG->isBaseWithConstantOffset(Addr)) {
2939-
29402939
int64_t CVal = cast<ConstantSDNode>(Addr.getOperand(1))->getSExtValue();
29412940
if (isUInt<9>(CVal)) {
29422941
Base = Addr.getOperand(0);
@@ -2947,13 +2946,13 @@ bool RISCVDAGToDAGISel::SelectAddrRegImm9(SDValue Addr, SDValue &Base,
29472946
return true;
29482947
}
29492948

2950-
// Handle with 12 bit ofset immediates with ADDI.
2949+
// Handle with 12 bit offset with sign bit off with ADDI.
2950+
// For Immediate Range [0, 2047]
29512951
else if (Addr.getOpcode() == ISD::ADD &&
29522952
isa<ConstantSDNode>(Addr.getOperand(1))) {
2953-
int64_t CVal = cast<ConstantSDNode>(Addr.getOperand(1))->getSExtValue();
29542953
assert(!isUInt<9>(CVal) && "uimm9 not already handled?");
29552954

2956-
if (isUInt<12>(CVal)) {
2955+
if (isUInt<11>(CVal)) {
29572956
Base = SDValue(CurDAG->getMachineNode(
29582957
RISCV::ADDI, DL, VT, Addr.getOperand(0),
29592958
CurDAG->getSignedTargetConstant(CVal, DL, VT)),
@@ -2963,10 +2962,6 @@ bool RISCVDAGToDAGISel::SelectAddrRegImm9(SDValue Addr, SDValue &Base,
29632962
}
29642963
}
29652964
}
2966-
// Immediates more than 12 bits i.e LUI,ADDI,ADD
2967-
if (selectConstantAddr(CurDAG, DL, VT, Subtarget, Addr, Base, Offset,
2968-
/*IsPrefetch=*/true))
2969-
return true;
29702965

29712966
Base = Addr;
29722967
Offset = CurDAG->getTargetConstant(0, DL, VT);

‎llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -45,9 +45,6 @@ class RISCVDAGToDAGISel : public SelectionDAGISel {
4545
InlineAsm::ConstraintCode ConstraintID,
4646
std::vector<SDValue> &OutOps) override;
4747

48-
bool SelectAddrFrameIndexOffset(SDValue Addr, SDValue &Base, SDValue &Offset,
49-
unsigned OffsetBits,
50-
unsigned ShiftAmount);
5148
bool SelectAddrFrameIndex(SDValue Addr, SDValue &Base, SDValue &Offset);
5249
bool SelectAddrRegImm(SDValue Addr, SDValue &Base, SDValue &Offset);
5350
bool SelectAddrRegImm9(SDValue Addr, SDValue &Base, SDValue &Offset);

‎llvm/lib/Target/RISCV/RISCVInstrInfoXMips.td

Lines changed: 13 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -110,39 +110,39 @@ class SWPFormat<dag outs, dag ins, string opcodestr, string argstr>
110110
}
111111

112112
// Prefetch format.
113-
let hasSideEffects = 0, mayLoad = 1,mayStore = 1 in
113+
let hasSideEffects = 0, mayLoad = 1, mayStore = 1 in
114114
class Mips_prefetch_ri<dag outs, dag ins, string opcodestr, string argstr>
115115
: RVInst<outs, ins, opcodestr, argstr, [], InstFormatI> {
116116
bits<9> imm9;
117117
bits<5> rs1;
118118
bits<5> hint;
119119

120-
let Inst{31 - 29} = 0b000;
121-
let Inst{28 - 20} = imm9{8 - 0};
122-
let Inst{19 - 15} = rs1;
123-
let Inst{14 - 12} = 0b000;
124-
let Inst{11 - 7} = hint;
125-
let Inst{6 - 0} = OPC_CUSTOM_0.Value;
120+
let Inst{31-29} = 0b000;
121+
let Inst{28-20} = imm9;
122+
let Inst{19-15} = rs1;
123+
let Inst{14-12} = 0b000;
124+
let Inst{11-7} = hint;
125+
let Inst{6-0} = OPC_CUSTOM_0.Value;
126126
}
127127

128128
//===----------------------------------------------------------------------===//
129129
// MIPS extensions
130130
//===----------------------------------------------------------------------===//
131131
let Predicates = [HasVendorXMIPSCBOP] ,DecoderNamespace = "Xmipscbop" in {
132-
def MIPSPREFETCH : Mips_prefetch_ri<(outs),(ins GPR:$rs1, uimm9:$imm9, uimm5:$hint),
133-
"mips.perf", "$hint, ${imm9}(${rs1})">,
132+
def MIPS_PREFETCH : Mips_prefetch_ri<(outs), (ins GPR:$rs1, uimm9:$imm9, uimm5:$hint),
133+
"mips.pref", "$hint, ${imm9}(${rs1})">,
134134
Sched<[]>;
135135
}
136136

137137
let Predicates = [HasVendorXMIPSCBOP] in {
138138
// Prefetch Data Write.
139-
def : Pat<(prefetch(AddrRegImm9(XLenVT GPR:$rs1),uimm9:$imm9),
139+
def : Pat<(prefetch (AddrRegImm9 (XLenVT GPR:$rs1), uimm9:$imm9),
140140
(i32 1), timm, (i32 1)),
141-
(MIPSPREFETCH GPR:$rs1, uimm9:$imm9, 9)>;
141+
(MIPS_PREFETCH GPR:$rs1, uimm9:$imm9, 9)>;
142142
// Prefetch Data Read.
143-
def : Pat<(prefetch(AddrRegImm9(XLenVT GPR:$rs1),uimm9:$imm9),
143+
def : Pat<(prefetch (AddrRegImm9 (XLenVT GPR:$rs1), uimm9:$imm9),
144144
(i32 0), timm, (i32 1)),
145-
(MIPSPREFETCH GPR:$rs1, uimm9:$imm9, 8)>;
145+
(MIPS_PREFETCH GPR:$rs1, uimm9:$imm9, 8)>;
146146
}
147147

148148
let Predicates = [HasVendorXMIPSCMov], hasSideEffects = 0, mayLoad = 0, mayStore = 0,

‎llvm/test/CodeGen/RISCV/xmips-cbop.ll

Lines changed: 15 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -1,40 +1,32 @@
1-
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
21
; RUN: llc -mtriple=riscv32 -mattr=+xmipscbop -mattr=+m -verify-machineinstrs < %s \
32
; RUN: | FileCheck %s -check-prefix=RV32XMIPSPREFETCH
43
; RUN: llc -mtriple=riscv64 -mattr=+xmipscbop -mattr=+m -verify-machineinstrs < %s \
54
; RUN: | FileCheck %s -check-prefix=RV64XMIPSPREFETCH
65

7-
define dso_local void @prefetch_read(ptr noundef %a) {
6+
define void @prefetch_read(ptr noundef %ptr) nounwind {
87
; RV32XMIPSPREFETCH-LABEL: prefetch_read:
9-
; RV32XMIPSPREFETCH: mips.perf 8, 511(a0)
8+
; RV32XMIPSPREFETCH: mips.pref 8, 1(a0)
109
;
1110
; RV64XMIPSPREFETCH-LABEL: prefetch_read:
12-
; RV64XMIPSPREFETCH: mips.perf 8, 511(a0)
11+
; RV64XMIPSPREFETCH: mips.pref 8, 1(a0)
1312
entry:
14-
%a.addr = alloca ptr, align 8
15-
store ptr %a, ptr %a.addr, align 8
16-
%0 = load ptr, ptr %a.addr, align 8
17-
%arrayidx = getelementptr inbounds i8, ptr %0, i64 511
18-
call void @llvm.prefetch.p0(ptr %arrayidx, i32 0, i32 0, i32 1)
13+
%arrayidx = getelementptr inbounds nuw i8, ptr %ptr, i64 1
14+
tail call void @llvm.prefetch.p0(ptr nonnull %arrayidx, i32 0, i32 0, i32 1)
15+
ret void
1916
ret void
2017
}
21-
22-
declare void @llvm.prefetch.p0(ptr readonly captures(none), i32 immarg, i32 immarg, i32 immarg)
23-
24-
define dso_local void @prefetch_write(ptr noundef %a) {
25-
entry:
18+
19+
define void @prefetch_write(ptr noundef %ptr) nounwind {
2620
; RV32XMIPSPREFETCH-LABEL: prefetch_write:
27-
; RV32XMIPSPREFETCH: addi a1, a0, 512
28-
; RV32XMIPSPREFETCH-NEXT: mips.perf 9, 0(a1)
21+
; RV32XMIPSPREFETCH: addi a0, a0, 512
22+
; RV32XMIPSPREFETCH-NEXT: mips.pref 9, 0(a0)
2923
;
3024
; RV64XMIPSPREFETCH-LABEL: prefetch_write:
31-
; RV64XMIPSPREFETCH: addi a1, a0, 512
32-
; RV64XMIPSPREFETCH-NEXT: mips.perf 9, 0(a1)
33-
%a.addr = alloca ptr, align 8
34-
store ptr %a, ptr %a.addr, align 8
35-
%0 = load ptr, ptr %a.addr, align 8
36-
%arrayidx = getelementptr inbounds i8, ptr %0, i64 512
37-
call void @llvm.prefetch.p0(ptr %arrayidx, i32 1, i32 0, i32 1)
25+
; RV64XMIPSPREFETCH: addi a0, a0, 512
26+
; RV64XMIPSPREFETCH-NEXT: mips.pref 9, 0(a0)
27+
entry:
28+
%arrayidx = getelementptr inbounds nuw i8, ptr %ptr, i64 512
29+
tail call void @llvm.prefetch.p0(ptr nonnull %arrayidx, i32 1, i32 0, i32 1)
3830
ret void
3931
}
4032

‎llvm/test/MC/RISCV/xmips-invalid.s

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,13 +1,13 @@
11
# RUN: not llvm-mc -triple=riscv64 < %s 2>&1 | FileCheck %s -check-prefixes=CHECK-FEATURE
22
# RUN: not llvm-mc -triple=riscv64 -mattr=+xmipslsp,+xmipscmov,+xmipsbcop < %s 2>&1 | FileCheck %s
33

4-
mips.perf 8, 512(a0)
4+
mips.pref 8, 512(a0)
55
# CHECK: error: invalid operand for instruction
66

7-
mips.perf 8
7+
mips.pref 8
88
# CHECK: error: too few operands for instruction
99

10-
mips.perf 8, 511(a0)
10+
mips.pref 8, 511(a0)
1111
# CHECK-FEATURE: error: instruction requires the following: 'Xmipscbop' (MIPS hardware prefetch)
1212

1313
mips.ccmov x0, x1, 0x10

‎llvm/test/MC/RISCV/xmips-valid.s

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -4,15 +4,15 @@
44
# RUN: | llvm-objdump --mattr=+xmipslsp,+xmipscmov,+xmipscbop -M no-aliases -d - \
55
# RUN: | FileCheck -check-prefix=CHECK-DIS %s
66

7-
# CHECK-INST: mips.perf 8, 511(a0)
7+
# CHECK-INST: mips.pref 8, 511(a0)
88
# CHECK-ENC: encoding: [0x0b,0x04,0xf5,0x1f]
9-
mips.perf 8, 511(a0)
9+
mips.pref 8, 511(a0)
1010

1111
# CHECK-DIS: mips.perf 0x8, 0x1ff(a0)
1212

13-
# CHECK-INST: mips.perf 9, 0(a0)
13+
# CHECK-INST: mips.pref 9, 0(a0)
1414
# CHECK-ENC: encoding: [0x8b,0x04,0x05,0x00]
15-
mips.perf 9, 0(a0)
15+
mips.pref 9, 0(a0)
1616

1717
# CHECK-DIS: mips.perf 0x9, 0x0(a0)
1818

‎llvm/unittests/TargetParser/RISCVISAInfoTest.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1140,9 +1140,9 @@ R"(All available -march extensions for RISC-V
11401140
xcvmac 1.0
11411141
xcvmem 1.0
11421142
xcvsimd 1.0
1143+
xmipscbop 1.0
11431144
xmipscmov 1.0
11441145
xmipslsp 1.0
1145-
xmipscbop 1.0
11461146
xsfcease 1.0
11471147
xsfmm128t 0.6
11481148
xsfmm16t 0.6

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