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mir-gen.c
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/* This file is a part of MIR project.
Copyright (C) 2018-2020 Vladimir Makarov <vmakarov.gcc@gmail.com>.
*/
/* Optimization pipeline:
---------------- ----------- ------------------ -------------
MIR --->| Simplify |--->| Build CFG |--->| Common Sub-Expr |--->| Dead Code |
---------------- ----------- | Elimination | | Elimination |
------------------ -------------
|
V
---------------- ------------ --------- ----------- ------------
| Loop Invariant | | Reaching | | Finding | | Variable | | Reaching |
| Code Motion |<--| Definitons |<--| Loops |<--| Renaming |<--| Definitons |
---------------- | Analysis | --------- ----------- | Analysis |
| ------------ ------------
V
---------------------- ----------- --------- ------------ -------------
| Sparse Conditional |-->| Machinize |-->| Finding |-->| Build Live |-->| Build Live |
| Constant Propagation | ----------- | Loops | | Info | | Ranges |
---------------------- --------- ------------ -------------
|
V
--------------- ------------- --------- --------- ---------
Machine <--| Generate |<--| Dead Code |<--| Combine |<--| Rewrite |<--| Assign |
Insns | machine insns | | Elimination | --------- --------- ---------
--------------- ------------
Simplify: Lowering MIR (in mir.c).
Build CGF: Building Control Flow Graph (basic blocks and CFG edges).
Common Sub-Expression Elimination: Reusing calculated values (it is before SCCP because
we need the right value numbering after simplification)
Dead code elimination: Removing insns with unused outputs.
Reaching definition Analysis: Analysis required for subsequent variable renaming
Variable renaming: Rename disjoint live ranges of variables which is beneficial for
register allocation and loop invariant code motion.
Finding Loops: Building loop tree which is used in subsequent loop invariant code motion.
Reaching definition Analysis: Analysis required for subsequent loop invariant code motion
Loop Invariant Code Motion (LICM): Register pressure sensitive moves loop invariant insns out
of the loop.
Sparse Conditional Constant Propagation: constant propagation and removing death paths of CFG
Machinize: Machine-dependent code (e.g. in mir-gen-x86_64.c)
transforming MIR for calls ABI, 2-op insns, etc.
Finding Loops: Building loop tree which is used in subsequent register allocation.
Building Live Info: Calculating live in and live out for the basic blocks.
Build Live Ranges: Calculating program point ranges for registers.
Assign: Priority-based assigning hard regs and stack slots to registers.
Rewrite: Transform MIR according to the assign using reserved hard regs.
Combine (code selection): Merging data-depended insns into one.
Dead code elimination: Removing insns with unused outputs.
Generate machine insns: Machine-dependent code (e.g. in
mir-gen-x86_64.c) creating machine insns.
Terminology:
reg - MIR (pseudo-)register (their numbers are in MIR_OP_REG and MIR_OP_MEM)
hard reg - MIR hard register (their numbers are in MIR_OP_HARD_REG and MIR_OP_HARD_REG_MEM)
breg (based reg) - function pseudo registers whose numbers start with zero
var - pseudo and hard register (var numbers for psedo-registers
are based reg numbers + MAX_HARD_REG + 1)
loc - hard register and stack locations (stack slot numbers start with MAX_HARD_REG + 1).
We don't use SSA because the optimization pipeline could use SSA is
short (2 passes) and going into / out of SSA is expensive.
*/
#include <stdlib.h>
#include <string.h>
#include <inttypes.h>
#include <assert.h>
#ifdef NDEBUG
static inline int gen_assert (int cond) { return 0 && cond; }
#else
#define gen_assert(cond) assert (cond)
#endif
struct MIR_context;
static void util_error (struct MIR_context *ctx, const char *message);
static void varr_error (const char *message) { util_error (NULL, message); }
#define MIR_VARR_ERROR varr_error
#include "mir.h"
#include "mir-dlist.h"
#include "mir-bitmap.h"
#include "mir-htab.h"
#include "mir-hash.h"
#include "mir-gen.h"
static void MIR_NO_RETURN util_error (MIR_context_t ctx, const char *message) {
(*MIR_get_error_func (ctx)) (MIR_alloc_error, message);
}
static void *gen_malloc (MIR_context_t ctx, size_t size) {
void *res = malloc (size);
if (res == NULL) util_error (ctx, "no memory");
return res;
}
static MIR_reg_t gen_new_temp_reg (MIR_context_t ctx, MIR_type_t type, MIR_func_t func);
static void set_label_disp (MIR_insn_t insn, size_t disp);
static size_t get_label_disp (MIR_insn_t insn);
static void create_new_bb_insns (MIR_context_t ctx, MIR_insn_t before, MIR_insn_t after,
MIR_insn_t insn_for_bb);
static void gen_delete_insn (MIR_context_t ctx, MIR_insn_t insn);
static void gen_add_insn_before (MIR_context_t ctx, MIR_insn_t before, MIR_insn_t insn);
static void gen_add_insn_after (MIR_context_t ctx, MIR_insn_t after, MIR_insn_t insn);
static void setup_call_hard_reg_args (MIR_insn_t call_insn, MIR_reg_t hard_reg);
#ifndef MIR_GEN_CALL_TRACE
#define MIR_GEN_CALL_TRACE 0
#endif
typedef struct func_cfg *func_cfg_t;
struct target_ctx;
struct data_flow_ctx;
struct cse_ctx;
struct rdef_ctx;
struct rename_ctx;
struct licm_ctx;
struct ccp_ctx;
struct lr_ctx;
struct ra_ctx;
struct selection_ctx;
typedef struct loop_node *loop_node_t;
DEF_VARR (loop_node_t);
struct gen_ctx {
unsigned int optimize_level; /* 0:only RA; 1:+combiner; 2: +CSE/CCP (default); >=3: everything */
MIR_item_t curr_func_item;
#if !MIR_NO_GEN_DEBUG
FILE *debug_file;
#endif
bitmap_t insn_to_consider, temp_bitmap, temp_bitmap2, all_vars;
bitmap_t call_used_hard_regs;
func_cfg_t curr_cfg;
size_t curr_bb_index, curr_loop_node_index;
struct target_ctx *target_ctx;
struct data_flow_ctx *data_flow_ctx;
struct cse_ctx *cse_ctx;
struct rename_ctx *rename_ctx;
struct licm_ctx *licm_ctx;
struct rdef_ctx *rdef_ctx;
struct ccp_ctx *ccp_ctx;
struct lr_ctx *lr_ctx;
struct ra_ctx *ra_ctx;
struct selection_ctx *selection_ctx;
VARR (loop_node_t) * loop_nodes, *queue_nodes, *loop_entries; /* used in building loop tree */
int max_int_hard_regs, max_fp_hard_regs;
};
static inline struct gen_ctx **gen_ctx_loc (MIR_context_t ctx) { return (struct gen_ctx **) ctx; }
#define optimize_level gen_ctx->optimize_level
#define curr_func_item gen_ctx->curr_func_item
#define debug_file gen_ctx->debug_file
#define insn_to_consider gen_ctx->insn_to_consider
#define temp_bitmap gen_ctx->temp_bitmap
#define temp_bitmap2 gen_ctx->temp_bitmap2
#define all_vars gen_ctx->all_vars
#define call_used_hard_regs gen_ctx->call_used_hard_regs
#define curr_cfg gen_ctx->curr_cfg
#define curr_bb_index gen_ctx->curr_bb_index
#define curr_loop_node_index gen_ctx->curr_loop_node_index
#define loop_nodes gen_ctx->loop_nodes
#define queue_nodes gen_ctx->queue_nodes
#define loop_entries gen_ctx->loop_entries
#define max_int_hard_regs gen_ctx->max_int_hard_regs
#define max_fp_hard_regs gen_ctx->max_fp_hard_regs
#ifdef __x86_64__
#include "mir-gen-x86_64.c"
#elif defined(__aarch64__)
#include "mir-gen-aarch64.c"
#else
#error "undefined or unsupported generation target"
#endif
#define DEFAULT_INIT_BITMAP_BITS_NUM 256
static void make_io_dup_op_insns (MIR_context_t ctx) {
struct gen_ctx *gen_ctx = *gen_ctx_loc (ctx);
MIR_func_t func;
MIR_insn_t insn, next_insn;
MIR_insn_code_t code;
MIR_op_t input, output, temp_op;
MIR_op_mode_t mode;
MIR_type_t type;
size_t i;
int out_p;
gen_assert (curr_func_item->item_type == MIR_func_item);
func = curr_func_item->u.func;
for (i = 0; target_io_dup_op_insn_codes[i] != MIR_INSN_BOUND; i++)
bitmap_set_bit_p (insn_to_consider, target_io_dup_op_insn_codes[i]);
if (bitmap_empty_p (insn_to_consider)) return;
for (insn = DLIST_HEAD (MIR_insn_t, func->insns); insn != NULL; insn = next_insn) {
next_insn = DLIST_NEXT (MIR_insn_t, insn);
code = insn->code;
if (!bitmap_bit_p (insn_to_consider, code)) continue;
gen_assert (MIR_insn_nops (ctx, insn) >= 2 && !MIR_call_code_p (code) && code != MIR_RET);
mode = MIR_insn_op_mode (ctx, insn, 0, &out_p);
gen_assert (out_p && mode == MIR_insn_op_mode (ctx, insn, 1, &out_p) && !out_p);
output = insn->ops[0];
input = insn->ops[1];
gen_assert (input.mode == MIR_OP_REG || input.mode == MIR_OP_HARD_REG
|| output.mode == MIR_OP_REG || output.mode == MIR_OP_HARD_REG);
if (input.mode == output.mode
&& ((input.mode == MIR_OP_HARD_REG && input.u.hard_reg == output.u.hard_reg)
|| (input.mode == MIR_OP_REG && input.u.reg == output.u.reg)))
continue;
if (mode == MIR_OP_FLOAT) {
code = MIR_FMOV;
type = MIR_T_F;
} else if (mode == MIR_OP_DOUBLE) {
code = MIR_DMOV;
type = MIR_T_D;
} else if (mode == MIR_OP_LDOUBLE) {
code = MIR_LDMOV;
type = MIR_T_LD;
} else {
code = MIR_MOV;
type = MIR_T_I64;
}
temp_op = MIR_new_reg_op (ctx, gen_new_temp_reg (ctx, type, func));
gen_add_insn_before (ctx, insn, MIR_new_insn (ctx, code, temp_op, insn->ops[1]));
gen_add_insn_after (ctx, insn, MIR_new_insn (ctx, code, insn->ops[0], temp_op));
insn->ops[0] = insn->ops[1] = temp_op;
}
}
typedef struct dead_var *dead_var_t;
DEF_DLIST_LINK (dead_var_t);
typedef struct bb *bb_t;
DEF_DLIST_LINK (bb_t);
typedef struct bb_insn *bb_insn_t;
DEF_DLIST_LINK (bb_insn_t);
typedef struct edge *edge_t;
typedef edge_t in_edge_t;
typedef edge_t out_edge_t;
DEF_DLIST_LINK (in_edge_t);
DEF_DLIST_LINK (out_edge_t);
struct edge {
bb_t src, dst;
DLIST_LINK (in_edge_t) in_link;
DLIST_LINK (out_edge_t) out_link;
unsigned char back_edge_p;
unsigned char skipped_p; /* used for CCP */
};
DEF_DLIST (in_edge_t, in_link);
DEF_DLIST (out_edge_t, out_link);
struct dead_var {
MIR_reg_t var;
DLIST_LINK (dead_var_t) dead_var_link;
};
DEF_DLIST (dead_var_t, dead_var_link);
struct bb_insn {
MIR_insn_t insn;
unsigned char flag, flag2; /* used for CCP and LICM */
size_t index; /* used for LICM */
DLIST_LINK (bb_insn_t) bb_insn_link;
bb_t bb;
DLIST (dead_var_t) dead_vars;
bitmap_t call_hard_reg_args; /* non-null for calls */
size_t label_disp; /* for label */
};
DEF_DLIST (bb_insn_t, bb_insn_link);
struct bb {
size_t index, pre, rpost, bfs; /* preorder, reverse post order, breadth first order */
unsigned int flag; /* used for CCP */
DLIST_LINK (bb_t) bb_link;
DLIST (in_edge_t) in_edges;
/* The out edges order: optional fall through bb, optional label bb,
optional exit bb. There is always at least one edge. */
DLIST (out_edge_t) out_edges;
DLIST (bb_insn_t) bb_insns;
size_t freq;
bitmap_t in, out, gen, kill; /* var bitmaps for different data flow problems */
bitmap_t dom_in, dom_out; /* additional var bitmaps LICM */
loop_node_t loop_node;
int max_int_pressure, max_fp_pressure;
};
DEF_DLIST (bb_t, bb_link);
DEF_DLIST_LINK (loop_node_t);
DEF_DLIST_TYPE (loop_node_t);
struct loop_node {
size_t index; /* if BB != NULL, it is index of BB */
bb_t bb; /* NULL for internal tree node */
loop_node_t entry;
loop_node_t parent;
bb_t preheader; /* used in LICM */
unsigned int call_p; /* used in LICM: call is present in the loop */
DLIST (loop_node_t) children;
DLIST_LINK (loop_node_t) children_link;
int max_int_pressure, max_fp_pressure;
};
DEF_DLIST_CODE (loop_node_t, children_link);
DEF_DLIST_LINK (func_cfg_t);
typedef struct mv *mv_t;
typedef mv_t dst_mv_t;
typedef mv_t src_mv_t;
DEF_DLIST_LINK (mv_t);
DEF_DLIST_LINK (dst_mv_t);
DEF_DLIST_LINK (src_mv_t);
struct mv {
bb_insn_t bb_insn;
size_t freq;
DLIST_LINK (mv_t) mv_link;
DLIST_LINK (dst_mv_t) dst_link;
DLIST_LINK (src_mv_t) src_link;
};
DEF_DLIST (mv_t, mv_link);
DEF_DLIST (dst_mv_t, dst_link);
DEF_DLIST (src_mv_t, src_link);
struct reg_info {
long freq;
size_t calls_num;
/* The followd members are defined and used only in RA */
long thread_freq; /* thread accumulated freq, defined for first thread breg */
/* first/next breg of the same thread, MIR_MAX_REG_NUM is end mark */
MIR_reg_t thread_first, thread_next;
size_t live_length; /* # of program points where breg lives */
DLIST (dst_mv_t) dst_moves;
DLIST (src_mv_t) src_moves;
};
typedef struct reg_info reg_info_t;
DEF_VARR (reg_info_t);
typedef struct {
int uns_p;
union {
int64_t i;
uint64_t u;
} u;
} const_t;
#if !MIR_NO_GEN_DEBUG
static void print_const (FILE *f, const_t c) {
if (c.uns_p)
fprintf (f, "%" PRIu64, c.u.u);
else
fprintf (f, "%" PRId64, c.u.i);
}
#endif
struct func_cfg {
MIR_reg_t min_reg, max_reg;
size_t non_conflicting_moves; /* # of moves with non-conflicting regs */
VARR (reg_info_t) * breg_info; /* bregs */
DLIST (bb_t) bbs;
DLIST (mv_t) used_moves, free_moves;
loop_node_t root_loop_node;
};
static DLIST (dead_var_t) free_dead_vars;
static void init_dead_vars (void) { DLIST_INIT (dead_var_t, free_dead_vars); }
static void free_dead_var (dead_var_t dv) { DLIST_APPEND (dead_var_t, free_dead_vars, dv); }
static dead_var_t get_dead_var (MIR_context_t ctx) {
dead_var_t dv;
if ((dv = DLIST_HEAD (dead_var_t, free_dead_vars)) == NULL)
return gen_malloc (ctx, sizeof (struct dead_var));
DLIST_REMOVE (dead_var_t, free_dead_vars, dv);
return dv;
}
static void finish_dead_vars (void) {
dead_var_t dv;
while ((dv = DLIST_HEAD (dead_var_t, free_dead_vars)) != NULL) {
DLIST_REMOVE (dead_var_t, free_dead_vars, dv);
free (dv);
}
}
static void add_bb_insn_dead_var (MIR_context_t ctx, bb_insn_t bb_insn, MIR_reg_t var) {
dead_var_t dv;
for (dv = DLIST_HEAD (dead_var_t, bb_insn->dead_vars); dv != NULL;
dv = DLIST_NEXT (dead_var_t, dv))
if (dv->var == var) return;
dv = get_dead_var (ctx);
dv->var = var;
DLIST_APPEND (dead_var_t, bb_insn->dead_vars, dv);
}
static dead_var_t find_bb_insn_dead_var (bb_insn_t bb_insn, MIR_reg_t var) {
dead_var_t dv;
for (dv = DLIST_HEAD (dead_var_t, bb_insn->dead_vars); dv != NULL;
dv = DLIST_NEXT (dead_var_t, dv))
if (dv->var == var) return dv;
return NULL;
}
static void clear_bb_insn_dead_vars (bb_insn_t bb_insn) {
dead_var_t dv;
while ((dv = DLIST_HEAD (dead_var_t, bb_insn->dead_vars)) != NULL) {
DLIST_REMOVE (dead_var_t, bb_insn->dead_vars, dv);
free_dead_var (dv);
}
}
static void remove_bb_insn_dead_var (bb_insn_t bb_insn, MIR_reg_t hr) {
dead_var_t dv, next_dv;
gen_assert (hr <= MAX_HARD_REG);
for (dv = DLIST_HEAD (dead_var_t, bb_insn->dead_vars); dv != NULL; dv = next_dv) {
next_dv = DLIST_NEXT (dead_var_t, dv);
if (dv->var != hr) continue;
DLIST_REMOVE (dead_var_t, bb_insn->dead_vars, dv);
free_dead_var (dv);
}
}
static void move_bb_insn_dead_vars (bb_insn_t bb_insn, bb_insn_t from_bb_insn) {
dead_var_t dv;
while ((dv = DLIST_HEAD (dead_var_t, from_bb_insn->dead_vars)) != NULL) {
DLIST_REMOVE (dead_var_t, from_bb_insn->dead_vars, dv);
DLIST_APPEND (dead_var_t, bb_insn->dead_vars, dv);
}
}
static bb_insn_t create_bb_insn (MIR_context_t ctx, MIR_insn_t insn, bb_t bb) {
bb_insn_t bb_insn = gen_malloc (ctx, sizeof (struct bb_insn));
insn->data = bb_insn;
bb_insn->bb = bb;
bb_insn->insn = insn;
bb_insn->flag = FALSE;
bb_insn->call_hard_reg_args = NULL;
DLIST_INIT (dead_var_t, bb_insn->dead_vars);
if (MIR_call_code_p (insn->code)) bb_insn->call_hard_reg_args = bitmap_create2 (MAX_HARD_REG + 1);
return bb_insn;
}
static bb_insn_t add_new_bb_insn (MIR_context_t ctx, MIR_insn_t insn, bb_t bb) {
bb_insn_t bb_insn = create_bb_insn (ctx, insn, bb);
DLIST_APPEND (bb_insn_t, bb->bb_insns, bb_insn);
return bb_insn;
}
static void delete_bb_insn (bb_insn_t bb_insn) {
DLIST_REMOVE (bb_insn_t, bb_insn->bb->bb_insns, bb_insn);
bb_insn->insn->data = NULL;
clear_bb_insn_dead_vars (bb_insn);
if (bb_insn->call_hard_reg_args != NULL) bitmap_destroy (bb_insn->call_hard_reg_args);
free (bb_insn);
}
static void create_new_bb_insns (MIR_context_t ctx, MIR_insn_t before, MIR_insn_t after,
MIR_insn_t insn_for_bb) {
struct gen_ctx *gen_ctx = *gen_ctx_loc (ctx);
MIR_insn_t insn;
bb_insn_t bb_insn, new_bb_insn;
bb_t bb;
if (insn_for_bb == NULL) /* It should be in the 1st block */
bb = DLIST_EL (bb_t, curr_cfg->bbs, 2); /* Skip entry and exit blocks */
else
bb = ((bb_insn_t) insn_for_bb->data)->bb;
if (before != NULL && (bb_insn = before->data)->bb == bb) {
for (insn = DLIST_NEXT (MIR_insn_t, before); insn != after;
insn = DLIST_NEXT (MIR_insn_t, insn), bb_insn = new_bb_insn) {
new_bb_insn = create_bb_insn (ctx, insn, bb);
DLIST_INSERT_AFTER (bb_insn_t, bb->bb_insns, bb_insn, new_bb_insn);
}
} else {
gen_assert (after != NULL);
bb_insn = after->data;
insn = (before == NULL ? DLIST_HEAD (MIR_insn_t, curr_func_item->u.func->insns)
: DLIST_NEXT (MIR_insn_t, before));
for (; insn != after; insn = DLIST_NEXT (MIR_insn_t, insn)) {
new_bb_insn = create_bb_insn (ctx, insn, bb);
if (bb == bb_insn->bb)
DLIST_INSERT_BEFORE (bb_insn_t, bb->bb_insns, bb_insn, new_bb_insn);
else
DLIST_APPEND (bb_insn_t, bb->bb_insns, new_bb_insn);
}
}
}
static void gen_delete_insn (MIR_context_t ctx, MIR_insn_t insn) {
struct gen_ctx *gen_ctx = *gen_ctx_loc (ctx);
delete_bb_insn (insn->data);
MIR_remove_insn (ctx, curr_func_item, insn);
}
static void gen_add_insn_before (MIR_context_t ctx, MIR_insn_t before, MIR_insn_t insn) {
MIR_insn_t insn_for_bb = before;
struct gen_ctx *gen_ctx = *gen_ctx_loc (ctx);
gen_assert (!MIR_branch_code_p (insn->code) && insn->code != MIR_LABEL);
if (before->code == MIR_LABEL) {
insn_for_bb = DLIST_PREV (MIR_insn_t, before);
gen_assert (insn_for_bb == NULL || !MIR_branch_code_p (insn_for_bb->code));
}
MIR_insert_insn_before (ctx, curr_func_item, before, insn);
create_new_bb_insns (ctx, DLIST_PREV (MIR_insn_t, insn), before, insn_for_bb);
}
static void gen_add_insn_after (MIR_context_t ctx, MIR_insn_t after, MIR_insn_t insn) {
struct gen_ctx *gen_ctx = *gen_ctx_loc (ctx);
gen_assert (insn->code != MIR_LABEL);
gen_assert (!MIR_branch_code_p (after->code));
MIR_insert_insn_after (ctx, curr_func_item, after, insn);
create_new_bb_insns (ctx, after, DLIST_NEXT (MIR_insn_t, insn), after);
}
static void setup_call_hard_reg_args (MIR_insn_t call_insn, MIR_reg_t hard_reg) {
bb_insn_t bb_insn = call_insn->data;
gen_assert (MIR_call_code_p (call_insn->code) && hard_reg <= MAX_HARD_REG);
bitmap_set_bit_p (bb_insn->call_hard_reg_args, hard_reg);
}
static void set_label_disp (MIR_insn_t insn, size_t disp) {
gen_assert (insn->code == MIR_LABEL);
((bb_insn_t) insn->data)->label_disp = disp;
}
static size_t get_label_disp (MIR_insn_t insn) {
gen_assert (insn->code == MIR_LABEL);
return ((bb_insn_t) insn->data)->label_disp;
}
static bb_t create_bb (MIR_context_t ctx, MIR_insn_t insn) {
bb_t bb = gen_malloc (ctx, sizeof (struct bb));
bb->pre = bb->rpost = bb->bfs = 0;
bb->flag = FALSE;
bb->loop_node = NULL;
DLIST_INIT (bb_insn_t, bb->bb_insns);
DLIST_INIT (in_edge_t, bb->in_edges);
DLIST_INIT (out_edge_t, bb->out_edges);
bb->in = bitmap_create2 (DEFAULT_INIT_BITMAP_BITS_NUM);
bb->out = bitmap_create2 (DEFAULT_INIT_BITMAP_BITS_NUM);
bb->gen = bitmap_create2 (DEFAULT_INIT_BITMAP_BITS_NUM);
bb->kill = bitmap_create2 (DEFAULT_INIT_BITMAP_BITS_NUM);
bb->dom_in = bitmap_create2 (DEFAULT_INIT_BITMAP_BITS_NUM);
bb->dom_out = bitmap_create2 (DEFAULT_INIT_BITMAP_BITS_NUM);
bb->max_int_pressure = bb->max_fp_pressure = 0;
if (insn != NULL) add_new_bb_insn (ctx, insn, bb);
return bb;
}
static void add_bb (MIR_context_t ctx, bb_t bb) {
struct gen_ctx *gen_ctx = *gen_ctx_loc (ctx);
DLIST_APPEND (bb_t, curr_cfg->bbs, bb);
bb->index = curr_bb_index++;
}
static edge_t create_edge (MIR_context_t ctx, bb_t src, bb_t dst, int append_p) {
edge_t e = gen_malloc (ctx, sizeof (struct edge));
e->src = src;
e->dst = dst;
if (append_p) {
DLIST_APPEND (in_edge_t, dst->in_edges, e);
DLIST_APPEND (out_edge_t, src->out_edges, e);
} else {
DLIST_PREPEND (in_edge_t, dst->in_edges, e);
DLIST_PREPEND (out_edge_t, src->out_edges, e);
}
e->back_edge_p = e->skipped_p = FALSE;
return e;
}
static void delete_edge (edge_t e) {
DLIST_REMOVE (out_edge_t, e->src->out_edges, e);
DLIST_REMOVE (in_edge_t, e->dst->in_edges, e);
free (e);
}
static void delete_bb (MIR_context_t ctx, bb_t bb) {
struct gen_ctx *gen_ctx = *gen_ctx_loc (ctx);
edge_t e, next_e;
for (e = DLIST_HEAD (out_edge_t, bb->out_edges); e != NULL; e = next_e) {
next_e = DLIST_NEXT (out_edge_t, e);
delete_edge (e);
}
for (e = DLIST_HEAD (in_edge_t, bb->in_edges); e != NULL; e = next_e) {
next_e = DLIST_NEXT (in_edge_t, e);
delete_edge (e);
}
DLIST_REMOVE (bb_t, curr_cfg->bbs, bb);
bitmap_destroy (bb->in);
bitmap_destroy (bb->out);
bitmap_destroy (bb->gen);
bitmap_destroy (bb->kill);
bitmap_destroy (bb->dom_in);
bitmap_destroy (bb->dom_out);
free (bb);
}
static void DFS (bb_t bb, size_t *pre, size_t *rpost) {
edge_t e;
bb->pre = (*pre)++;
for (e = DLIST_HEAD (out_edge_t, bb->out_edges); e != NULL; e = DLIST_NEXT (out_edge_t, e))
if (e->dst->pre == 0)
DFS (e->dst, pre, rpost);
else if (e->dst->rpost == 0)
e->back_edge_p = TRUE;
bb->rpost = (*rpost)--;
}
static void enumerate_bbs (MIR_context_t ctx) {
struct gen_ctx *gen_ctx = *gen_ctx_loc (ctx);
size_t pre, rpost;
pre = 1;
rpost = DLIST_LENGTH (bb_t, curr_cfg->bbs);
DFS (DLIST_HEAD (bb_t, curr_cfg->bbs), &pre, &rpost);
}
static loop_node_t top_loop_node (bb_t bb) {
for (loop_node_t loop_node = bb->loop_node;; loop_node = loop_node->parent)
if (loop_node->parent == NULL) return loop_node;
}
static int in_loop_p (loop_node_t node, loop_node_t loop) {
for (loop_node_t curr_node = node; curr_node != NULL; curr_node = curr_node->parent)
if (curr_node == loop) return TRUE;
return FALSE;
}
static int bb_loop_exit_p (MIR_context_t ctx, bb_t bb, loop_node_t loop) {
for (edge_t e = DLIST_HEAD (out_edge_t, bb->out_edges); e != NULL; e = DLIST_PREV (out_edge_t, e))
if (!in_loop_p (e->dst->loop_node, loop)) return TRUE;
return FALSE;
}
static loop_node_t create_loop_node (MIR_context_t ctx, bb_t bb) {
struct gen_ctx *gen_ctx = *gen_ctx_loc (ctx);
loop_node_t loop_node = gen_malloc (ctx, sizeof (struct loop_node));
loop_node->index = curr_loop_node_index++;
loop_node->bb = bb;
if (bb != NULL) bb->loop_node = loop_node;
loop_node->parent = NULL;
loop_node->entry = NULL;
loop_node->preheader = NULL;
loop_node->max_int_pressure = loop_node->max_fp_pressure = 0;
DLIST_INIT (loop_node_t, loop_node->children);
return loop_node;
}
static int process_loop (MIR_context_t ctx, bb_t entry_bb) {
struct gen_ctx *gen_ctx = *gen_ctx_loc (ctx);
edge_t e;
loop_node_t loop_node, new_loop_node, queue_node;
bb_t queue_bb;
VARR_TRUNC (loop_node_t, loop_nodes, 0);
VARR_TRUNC (loop_node_t, queue_nodes, 0);
bitmap_clear (temp_bitmap);
for (e = DLIST_HEAD (in_edge_t, entry_bb->in_edges); e != NULL; e = DLIST_NEXT (in_edge_t, e))
if (e->back_edge_p && e->src != entry_bb) {
loop_node = top_loop_node (e->src);
if (!bitmap_set_bit_p (temp_bitmap, loop_node->index)) continue;
VARR_PUSH (loop_node_t, loop_nodes, loop_node);
VARR_PUSH (loop_node_t, queue_nodes, loop_node);
}
while (VARR_LENGTH (loop_node_t, queue_nodes) != 0) {
queue_node = VARR_POP (loop_node_t, queue_nodes);
if ((queue_bb = queue_node->bb) == NULL) queue_bb = queue_node->entry->bb; /* subloop */
/* entry block is achieved which means multiple entry loop -- just ignore */
if (queue_bb == DLIST_HEAD (bb_t, curr_cfg->bbs)) return FALSE;
for (e = DLIST_HEAD (in_edge_t, queue_bb->in_edges); e != NULL; e = DLIST_NEXT (in_edge_t, e))
if (e->src != entry_bb) {
loop_node = top_loop_node (e->src);
if (!bitmap_set_bit_p (temp_bitmap, loop_node->index)) continue;
VARR_PUSH (loop_node_t, loop_nodes, loop_node);
VARR_PUSH (loop_node_t, queue_nodes, loop_node);
}
}
loop_node = entry_bb->loop_node;
VARR_PUSH (loop_node_t, loop_nodes, loop_node);
new_loop_node = create_loop_node (ctx, NULL);
new_loop_node->entry = loop_node;
while (VARR_LENGTH (loop_node_t, loop_nodes) != 0) {
loop_node = VARR_POP (loop_node_t, loop_nodes);
DLIST_APPEND (loop_node_t, new_loop_node->children, loop_node);
loop_node->parent = new_loop_node;
}
return TRUE;
}
static void setup_loop_pressure (MIR_context_t ctx, loop_node_t loop_node) {
for (loop_node_t curr = DLIST_HEAD (loop_node_t, loop_node->children); curr != NULL;
curr = DLIST_NEXT (loop_node_t, curr)) {
if (curr->bb == NULL) {
setup_loop_pressure (ctx, curr);
} else {
curr->max_int_pressure = curr->bb->max_int_pressure;
curr->max_fp_pressure = curr->bb->max_fp_pressure;
}
if (loop_node->max_int_pressure < curr->max_int_pressure)
loop_node->max_int_pressure = curr->max_int_pressure;
if (loop_node->max_fp_pressure < curr->max_fp_pressure)
loop_node->max_fp_pressure = curr->max_fp_pressure;
}
}
static int compare_bb_loop_nodes (const void *p1, const void *p2) {
bb_t bb1 = (*(const loop_node_t *) p1)->bb, bb2 = (*(const loop_node_t *) p2)->bb;
return bb1->rpost > bb2->rpost ? -1 : bb1->rpost < bb2->rpost ? 1 : 0;
}
static int build_loop_tree (MIR_context_t ctx) {
struct gen_ctx *gen_ctx = *gen_ctx_loc (ctx);
loop_node_t loop_node;
edge_t e;
int loops_p = FALSE;
curr_loop_node_index = 0;
enumerate_bbs (ctx);
VARR_TRUNC (loop_node_t, loop_entries, 0);
for (bb_t bb = DLIST_HEAD (bb_t, curr_cfg->bbs); bb != NULL; bb = DLIST_NEXT (bb_t, bb)) {
loop_node = create_loop_node (ctx, bb);
loop_node->entry = loop_node;
for (e = DLIST_HEAD (in_edge_t, bb->in_edges); e != NULL; e = DLIST_NEXT (in_edge_t, e))
if (e->back_edge_p) {
VARR_PUSH (loop_node_t, loop_entries, loop_node);
break;
}
}
qsort (VARR_ADDR (loop_node_t, loop_entries), VARR_LENGTH (loop_node_t, loop_entries),
sizeof (loop_node_t), compare_bb_loop_nodes);
for (size_t i = 0; i < VARR_LENGTH (loop_node_t, loop_entries); i++)
if (process_loop (ctx, VARR_GET (loop_node_t, loop_entries, i)->bb)) loops_p = TRUE;
curr_cfg->root_loop_node = create_loop_node (ctx, NULL);
for (bb_t bb = DLIST_HEAD (bb_t, curr_cfg->bbs); bb != NULL; bb = DLIST_NEXT (bb_t, bb))
if ((loop_node = top_loop_node (bb)) != curr_cfg->root_loop_node) {
DLIST_APPEND (loop_node_t, curr_cfg->root_loop_node->children, loop_node);
loop_node->parent = curr_cfg->root_loop_node;
}
setup_loop_pressure (ctx, curr_cfg->root_loop_node);
return loops_p;
}
static void destroy_loop_tree (MIR_context_t ctx, loop_node_t root) {
struct gen_ctx *gen_ctx = *gen_ctx_loc (ctx);
loop_node_t node, next;
if (root->bb != NULL) {
root->bb->loop_node = NULL;
} else {
for (node = DLIST_HEAD (loop_node_t, root->children); node != NULL; node = next) {
next = DLIST_NEXT (loop_node_t, node);
destroy_loop_tree (ctx, node);
}
}
free (root);
}
static void update_min_max_reg (MIR_context_t ctx, MIR_reg_t reg) {
struct gen_ctx *gen_ctx = *gen_ctx_loc (ctx);
if (reg == 0) return;
if (curr_cfg->max_reg == 0 || curr_cfg->min_reg > reg) curr_cfg->min_reg = reg;
if (curr_cfg->max_reg < reg) curr_cfg->max_reg = reg;
}
static MIR_reg_t gen_new_temp_reg (MIR_context_t ctx, MIR_type_t type, MIR_func_t func) {
MIR_reg_t reg = _MIR_new_temp_reg (ctx, type, func);
update_min_max_reg (ctx, reg);
return reg;
}
static MIR_reg_t reg2breg (struct gen_ctx *gen_ctx, MIR_reg_t reg) {
return reg - curr_cfg->min_reg;
}
static MIR_reg_t breg2reg (struct gen_ctx *gen_ctx, MIR_reg_t breg) {
return breg + curr_cfg->min_reg;
}
static MIR_reg_t reg2var (struct gen_ctx *gen_ctx, MIR_reg_t reg) {
return reg2breg (gen_ctx, reg) + MAX_HARD_REG + 1;
}
static MIR_reg_t var_is_reg_p (MIR_reg_t var) { return var > MAX_HARD_REG; }
static MIR_reg_t var2reg (struct gen_ctx *gen_ctx, MIR_reg_t var) {
gen_assert (var > MAX_HARD_REG);
return breg2reg (gen_ctx, var - MAX_HARD_REG - 1);
}
static MIR_reg_t var2breg (struct gen_ctx *gen_ctx, MIR_reg_t var) {
gen_assert (var > MAX_HARD_REG);
return var - MAX_HARD_REG - 1;
}
static MIR_reg_t get_nregs (MIR_context_t ctx) {
struct gen_ctx *gen_ctx = *gen_ctx_loc (ctx);
return curr_cfg->max_reg == 0 ? 0 : curr_cfg->max_reg - curr_cfg->min_reg + 1;
}
static MIR_reg_t get_nvars (MIR_context_t ctx) { return get_nregs (ctx) + MAX_HARD_REG + 1; }
static int move_p (MIR_insn_t insn) {
return ((insn->code == MIR_MOV || insn->code == MIR_FMOV || insn->code == MIR_DMOV
|| insn->code == MIR_LDMOV)
&& (insn->ops[0].mode == MIR_OP_REG || insn->ops[0].mode == MIR_OP_HARD_REG)
&& (insn->ops[1].mode == MIR_OP_REG || insn->ops[1].mode == MIR_OP_HARD_REG));
}
static int imm_move_p (MIR_insn_t insn) {
return ((insn->code == MIR_MOV || insn->code == MIR_FMOV || insn->code == MIR_DMOV
|| insn->code == MIR_LDMOV)
&& (insn->ops[0].mode == MIR_OP_REG || insn->ops[0].mode == MIR_OP_HARD_REG)
&& (insn->ops[1].mode == MIR_OP_INT || insn->ops[1].mode == MIR_OP_UINT
|| insn->ops[1].mode == MIR_OP_FLOAT || insn->ops[1].mode == MIR_OP_DOUBLE
|| insn->ops[1].mode == MIR_OP_LDOUBLE || insn->ops[1].mode == MIR_OP_REF));
}
typedef struct {
MIR_insn_t insn;
size_t nops, op_num, op_part_num, passed_mem_num;
} insn_var_iterator_t;
static inline void insn_var_iterator_init (MIR_context_t ctx, insn_var_iterator_t *iter,
MIR_insn_t insn) {
iter->insn = insn;
iter->nops = MIR_insn_nops (ctx, insn);
iter->op_num = 0;
iter->op_part_num = 0;
iter->passed_mem_num = 0;
}
static inline int insn_var_iterator_next (MIR_context_t ctx, insn_var_iterator_t *iter,
MIR_reg_t *var, int *out_p, int *mem_p,
size_t *passed_mem_num) {
struct gen_ctx *gen_ctx = *gen_ctx_loc (ctx);
MIR_op_t op;
while (iter->op_num < iter->nops) {
MIR_insn_op_mode (ctx, iter->insn, iter->op_num, out_p);
op = iter->insn->ops[iter->op_num];
*mem_p = FALSE;
*passed_mem_num = iter->passed_mem_num;
while (iter->op_part_num < 2) {
if (op.mode == MIR_OP_MEM || op.mode == MIR_OP_HARD_REG_MEM) {
*mem_p = TRUE;
*passed_mem_num = ++iter->passed_mem_num;
*out_p = FALSE;
if (op.mode == MIR_OP_MEM) {
*var = iter->op_part_num == 0 ? op.u.mem.base : op.u.mem.index;
if (*var == 0) {
iter->op_part_num++;
continue;
}
*var = reg2var (gen_ctx, *var);
} else {
*var = iter->op_part_num == 0 ? op.u.hard_reg_mem.base : op.u.hard_reg_mem.index;
if (*var == MIR_NON_HARD_REG) {
iter->op_part_num++;
continue;
}
}
} else if (iter->op_part_num > 0) {
break;
} else if (op.mode == MIR_OP_REG) {
*var = reg2var (gen_ctx, op.u.reg);
} else if (op.mode == MIR_OP_HARD_REG) {
*var = op.u.hard_reg;
} else
break;
iter->op_part_num++;
return TRUE;
}
iter->op_num++;
iter->op_part_num = 0;
}
return FALSE;
}
#define FOREACH_INSN_VAR(ctx, iterator, insn, var, out_p, mem_p, passed_mem_num) \
for (insn_var_iterator_init (ctx, &iterator, insn); \
insn_var_iterator_next (ctx, &iterator, &var, &out_p, &mem_p, &passed_mem_num);)
#if !MIR_NO_GEN_DEBUG
static void output_in_edges (MIR_context_t ctx, bb_t bb) {
struct gen_ctx *gen_ctx = *gen_ctx_loc (ctx);
edge_t e;
fprintf (debug_file, " in edges:");
for (e = DLIST_HEAD (in_edge_t, bb->in_edges); e != NULL; e = DLIST_NEXT (in_edge_t, e)) {
fprintf (debug_file, " %3lu", (unsigned long) e->src->index);
if (e->skipped_p) fprintf (debug_file, "(CCP skip)");
}
fprintf (debug_file, "\n");
}
static void output_out_edges (MIR_context_t ctx, bb_t bb) {
struct gen_ctx *gen_ctx = *gen_ctx_loc (ctx);
edge_t e;
fprintf (debug_file, " out edges:");
for (e = DLIST_HEAD (out_edge_t, bb->out_edges); e != NULL; e = DLIST_NEXT (out_edge_t, e)) {
fprintf (debug_file, " %3lu", (unsigned long) e->dst->index);
if (e->skipped_p) fprintf (debug_file, "(CCP skip)");
}
fprintf (debug_file, "\n");
}
static void output_bitmap (MIR_context_t ctx, const char *head, bitmap_t bm, int var_p) {
struct gen_ctx *gen_ctx = *gen_ctx_loc (ctx);
size_t nel;
bitmap_iterator_t bi;
if (bm == NULL || bitmap_empty_p (bm)) return;
fprintf (debug_file, "%s", head);
FOREACH_BITMAP_BIT (bi, bm, nel) {
fprintf (debug_file, " %3lu", (unsigned long) nel);
if (var_p && var_is_reg_p (nel))
fprintf (debug_file, "(%s:%s)",
MIR_type_str (ctx,
MIR_reg_type (ctx, var2reg (gen_ctx, nel), curr_func_item->u.func)),
MIR_reg_name (ctx, var2reg (gen_ctx, nel), curr_func_item->u.func));
}
fprintf (debug_file, "\n");
}
static void print_bb_insn (MIR_context_t ctx, bb_insn_t bb_insn, int with_notes_p) {
struct gen_ctx *gen_ctx = *gen_ctx_loc (ctx);
MIR_op_t op;
MIR_output_insn (ctx, debug_file, bb_insn->insn, curr_func_item->u.func, FALSE);
if (with_notes_p) {
for (dead_var_t dv = DLIST_HEAD (dead_var_t, bb_insn->dead_vars); dv != NULL;
dv = DLIST_NEXT (dead_var_t, dv)) {
if (var_is_reg_p (dv->var)) {
op.mode = MIR_OP_REG;
op.u.reg = var2reg (gen_ctx, dv->var);
} else {
op.mode = MIR_OP_HARD_REG;
op.u.hard_reg = dv->var;
}
fprintf (debug_file, dv == DLIST_HEAD (dead_var_t, bb_insn->dead_vars) ? " # dead: " : " ");
MIR_output_op (ctx, debug_file, op, curr_func_item->u.func);
}
}
fprintf (debug_file, "\n");
}
static void print_CFG (MIR_context_t ctx, int bb_p, int pressure_p, int insns_p, int insn_index_p,
void (*bb_info_print_func) (MIR_context_t, bb_t)) {
struct gen_ctx *gen_ctx = *gen_ctx_loc (ctx);
for (bb_t bb = DLIST_HEAD (bb_t, curr_cfg->bbs); bb != NULL; bb = DLIST_NEXT (bb_t, bb)) {
if (bb_p) {
fprintf (debug_file, "BB %3lu", (unsigned long) bb->index);
if (pressure_p)
fprintf (debug_file, " (pressure: int=%d, fp=%d)", bb->max_int_pressure,
bb->max_fp_pressure);
if (bb->loop_node == NULL)
fprintf (debug_file, "\n");
else