[test-triage] pendingReqPerSrc_M fails in tlul_assert.sv during rom_e2e_shutdown_output chip-level test

[elliotb-lowrisc]

Hierarchy of regression failure

Chip Level

Failure Description

UVM_INFO @ 20792.572969 us: (chip_sw_rom_e2e_base_vseq.sv:19) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_shutdown_output_vseq] Disconnecting UART agent from UART 0 ...
UVM_INFO @ 20792.572969 us: (chip_sw_rom_e2e_shutdown_output_vseq.sv:14) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_shutdown_output_vseq] Backdoor overwriting the lifecycle state and applying POR ...
UVM_INFO @ 20792.572969 us: (chip_base_vseq.sv:49) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_shutdown_output_vseq] Asserting POR_N
UVM_INFO @ 20802.572969 us: (chip_base_vseq.sv:53) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_rom_e2e_shutdown_output_vseq] POR_N complete
"../src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 268: tb.dut.top_earlgrey.u_rstmgr_aon.tlul_assert_device.gen_device.pendingReqPerSrc_M: started at 22712150664ps failed at 22712150664ps
	Offending '(pend_req[h2d.a_source].pend == 0)'
UVM_ERROR @ 22712.150664 us: (tlul_assert.sv:268) [ASSERT FAILED] pendingReqPerSrc_M

Steps to Reproduce

• GitHub Revision: af2d170
• dvsim invocation command to reproduce the failure, inclusive of build and run seeds:
  util/dvsim/dvsim.py hw/top_earlgrey/dv/chip_sim_cfg.hjson -i rom_e2e_shutdown_output --build-seed 13980492992314588037778262839223440914483141513139750793389284041724730149540 --seed 24635030167594819145773685420472791935838066513677808134159163261625674501968

Tests with similar or related failures

Same assert, different chip-level test: chip_sw_pwrmgr_random_sleep_all_reset_reqs #24349