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0047-RISCV-Initial-support-for-emitting-call-frame-inform.patch
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0047-RISCV-Initial-support-for-emitting-call-frame-inform.patch
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From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Alex Bradbury <asb@lowrisc.org>
Subject: [RISCV] Initial support for emitting call frame information (needs
testing)
This patch tests that appropriate directives are emitted, but I haven't done
an end-to-end test using gdb.
---
lib/Target/RISCV/MCTargetDesc/RISCVMCAsmInfo.cpp | 2 ++
.../RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp | 6 +++++-
lib/Target/RISCV/RISCVFrameLowering.cpp | 21 +++++++++++++++++++
test/CodeGen/RISCV/cfi-info.ll | 24 ++++++++++++++++++++++
4 files changed, 52 insertions(+), 1 deletion(-)
create mode 100644 test/CodeGen/RISCV/cfi-info.ll
diff --git a/lib/Target/RISCV/MCTargetDesc/RISCVMCAsmInfo.cpp b/lib/Target/RISCV/MCTargetDesc/RISCVMCAsmInfo.cpp
index d622911e92c..9f806dc1a49 100644
--- a/lib/Target/RISCV/MCTargetDesc/RISCVMCAsmInfo.cpp
+++ b/lib/Target/RISCV/MCTargetDesc/RISCVMCAsmInfo.cpp
@@ -22,4 +22,6 @@ RISCVMCAsmInfo::RISCVMCAsmInfo(const Triple &TT) {
CommentString = "#";
AlignmentIsInBytes = false;
SupportsDebugInformation = true;
+ ExceptionsType = ExceptionHandling::DwarfCFI;
+ DwarfRegNumForCFI = true;
}
diff --git a/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp b/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
index 45de976ec6c..f9a69826e10 100644
--- a/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
+++ b/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp
@@ -48,7 +48,11 @@ static MCRegisterInfo *createRISCVMCRegisterInfo(const Triple &TT) {
static MCAsmInfo *createRISCVMCAsmInfo(const MCRegisterInfo &MRI,
const Triple &TT) {
- return new RISCVMCAsmInfo(TT);
+ MCAsmInfo *MAI = new RISCVMCAsmInfo(TT);
+ // Initial state of the frame pointer is SP.
+ unsigned Reg = MRI.getDwarfRegNum(RISCV::X2, true);
+ MAI->addInitialFrameState(MCCFIInstruction::createDefCfa(nullptr, Reg, 0));
+ return MAI;
}
static MCSubtargetInfo *createRISCVMCSubtargetInfo(const Triple &TT,
diff --git a/lib/Target/RISCV/RISCVFrameLowering.cpp b/lib/Target/RISCV/RISCVFrameLowering.cpp
index 33703f5ec20..324ae8f2f3b 100644
--- a/lib/Target/RISCV/RISCVFrameLowering.cpp
+++ b/lib/Target/RISCV/RISCVFrameLowering.cpp
@@ -17,6 +17,7 @@
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/CodeGen/MachineModuleInfo.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/RegisterScavenging.h"
@@ -113,6 +114,7 @@ void RISCVFrameLowering::emitPrologue(MachineFunction &MF,
MachineFrameInfo &MFI = MF.getFrameInfo();
auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();
MachineBasicBlock::iterator MBBI = MBB.begin();
+ const RISCVInstrInfo *TII = STI.getInstrInfo();
unsigned FPReg = getFPReg(STI);
unsigned SPReg = getSPReg(STI);
@@ -148,6 +150,25 @@ void RISCVFrameLowering::emitPrologue(MachineFunction &MF,
if (hasFP(MF))
adjustReg(MBB, MBBI, DL, FPReg, SPReg,
StackSize - RVFI->getVarArgsSaveSize(), MachineInstr::FrameSetup);
+
+ // Emit CFI records:
+ const MCRegisterInfo *MRI = MF.getMMI().getContext().getRegisterInfo();
+ // .cfi_def_cfa_offset -StackSize
+ unsigned CFIIndex = MF.addFrameInst(
+ MCCFIInstruction::createDefCfaOffset(nullptr, -StackSize));
+ BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
+ .addCFIIndex(CFIIndex)
+ .setMIFlags(MachineInstr::FrameSetup);
+ // .cfi_def_cfa_register DwarfRegNum
+ for (const auto &Entry : CSI) {
+ unsigned Reg = Entry.getReg();
+ int FI = Entry.getFrameIdx();
+ CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
+ nullptr, MRI->getDwarfRegNum(Reg, true), MFI.getObjectOffset(FI)));
+ BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
+ .addCFIIndex(CFIIndex)
+ .setMIFlags(MachineInstr::FrameSetup);
+ }
}
void RISCVFrameLowering::emitEpilogue(MachineFunction &MF,
diff --git a/test/CodeGen/RISCV/cfi-info.ll b/test/CodeGen/RISCV/cfi-info.ll
new file mode 100644
index 00000000000..32d246380ac
--- /dev/null
+++ b/test/CodeGen/RISCV/cfi-info.ll
@@ -0,0 +1,24 @@
+; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s | FileCheck %s
+
+define i32 @callee(i32 %a, i64 %b, i32 %c, i32 %d, double %e) {
+; CHECK-LABEL: callee:
+; CHECK: addi sp, sp, -32
+; CHECK: sw ra, 28(sp)
+; CHECK: sw s1, 24(sp)
+; CHECK: sw s2, 20(sp)
+; CHECK: sw s3, 16(sp)
+; CHECK: sw s4, 12(sp)
+; CHECK: .cfi_def_cfa_offset 32
+; CHECK: .cfi_offset 1, -4
+; CHECK: .cfi_offset 9, -8
+; CHECK: .cfi_offset 18, -12
+; CHECK: .cfi_offset 19, -16
+; CHECK: .cfi_offset 20, -20
+ %b_trunc = trunc i64 %b to i32
+ %e_fptosi = fptosi double %e to i32
+ %1 = add i32 %a, %b_trunc
+ %2 = add i32 %1, %c
+ %3 = add i32 %2, %d
+ %4 = add i32 %3, %e_fptosi
+ ret i32 %4
+}
--
2.16.2