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0067-RISCV-Enable-emission-of-aliased-instructions-by-def.patch
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0067-RISCV-Enable-emission-of-aliased-instructions-by-def.patch
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From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
From: Alex Bradbury <asb@lowrisc.org>
Subject: [RISCV] Enable emission of aliased instructions by default
This patch switches the default for -riscv-no-aliases to false
and updates all affected MC and CodeGen tests. As recommended in
D41071, MC tests use the canonical instructions and the CodeGen
tests use the aliases.
Additionally, for the f and d instructions with rounding mode,
the tests for the aliased versions are moved and tightened such
that they can actually detect if alias emission is enabled.
(see D40902 for context).
Differential Revision: https://reviews.llvm.org/D41225
Patch by Mario Werner.
(Note: the changes to test/CodeGen/* were regenerated when merging this patch
in to github.com/lowrisc/riscv-llvm).
---
lib/Target/RISCV/InstPrinter/RISCVInstPrinter.cpp | 4 +-
test/CodeGen/RISCV/addc-adde-sube-subc.ll | 22 +-
test/CodeGen/RISCV/alloca.ll | 16 +-
test/CodeGen/RISCV/alu32.ll | 96 ++++-----
test/CodeGen/RISCV/alu64.ll | 162 +++++++--------
test/CodeGen/RISCV/analyze-branch.ll | 12 +-
test/CodeGen/RISCV/bare-select.ll | 16 +-
test/CodeGen/RISCV/blockaddress.ll | 4 +-
test/CodeGen/RISCV/branch-relaxation.ll | 12 +-
test/CodeGen/RISCV/branch.ll | 4 +-
test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll | 128 ++++++------
test/CodeGen/RISCV/byval.ll | 6 +-
test/CodeGen/RISCV/calling-conv-sext-zext.ll | 90 ++++-----
test/CodeGen/RISCV/calling-conv.ll | 233 +++++++++++-----------
test/CodeGen/RISCV/calls.ll | 74 +++----
test/CodeGen/RISCV/cfi-info.ll | 46 +++--
test/CodeGen/RISCV/div.ll | 72 +++----
test/CodeGen/RISCV/double-arith.ll | 170 +++++++++++++++-
test/CodeGen/RISCV/double-br-fcmp.ll | 112 +++++------
test/CodeGen/RISCV/double-convert.ll | 12 +-
test/CodeGen/RISCV/double-fcmp.ll | 44 ++--
test/CodeGen/RISCV/double-imm.ll | 4 +-
test/CodeGen/RISCV/double-mem.ll | 18 +-
test/CodeGen/RISCV/double-select-fcmp.ll | 110 +++++-----
test/CodeGen/RISCV/double-stack-spill-restore.ll | 8 +-
test/CodeGen/RISCV/float-arith.ll | 32 +--
test/CodeGen/RISCV/float-br-fcmp.ll | 112 +++++------
test/CodeGen/RISCV/float-convert.ll | 12 +-
test/CodeGen/RISCV/float-fcmp.ll | 44 ++--
test/CodeGen/RISCV/float-fma.ll | 8 +-
test/CodeGen/RISCV/float-imm.ll | 4 +-
test/CodeGen/RISCV/float-mem.ll | 18 +-
test/CodeGen/RISCV/float-select-fcmp.ll | 108 +++++-----
test/CodeGen/RISCV/fp128.ll | 12 +-
test/CodeGen/RISCV/frame.ll | 12 +-
test/CodeGen/RISCV/frameaddr-returnaddr.ll | 16 +-
test/CodeGen/RISCV/i32-icmp.ll | 24 +--
test/CodeGen/RISCV/imm.ll | 32 +--
test/CodeGen/RISCV/indirectbr.ll | 10 +-
test/CodeGen/RISCV/inline-asm.ll | 8 +-
test/CodeGen/RISCV/jumptable.ll | 8 +-
test/CodeGen/RISCV/large-stack.ll | 10 +-
test/CodeGen/RISCV/mem.ll | 28 +--
test/CodeGen/RISCV/mem64.ll | 30 +--
test/CodeGen/RISCV/mul.ll | 62 +++---
test/CodeGen/RISCV/rem.ll | 12 +-
test/CodeGen/RISCV/rotl-rotr.ll | 4 +-
test/CodeGen/RISCV/select-cc.ll | 22 +-
test/CodeGen/RISCV/sext-zext-trunc.ll | 78 ++++----
test/CodeGen/RISCV/shifts.ll | 12 +-
test/CodeGen/RISCV/vararg.ll | 153 +++++++-------
test/CodeGen/RISCV/wide-mem.ll | 6 +-
test/MC/RISCV/fixups.s | 5 +-
test/MC/RISCV/priv-valid.s | 10 +-
test/MC/RISCV/relocations.s | 2 +-
test/MC/RISCV/rv32a-valid.s | 10 +-
test/MC/RISCV/rv32c-only-valid.s | 4 +-
test/MC/RISCV/rv32c-valid.s | 10 +-
test/MC/RISCV/rv32d-valid.s | 56 +++---
test/MC/RISCV/rv32dc-valid.s | 12 +-
test/MC/RISCV/rv32f-valid.s | 62 +++---
test/MC/RISCV/rv32fc-valid.s | 10 +-
test/MC/RISCV/rv32i-aliases-invalid.s | 2 +-
test/MC/RISCV/rv32i-aliases-valid.s | 6 +-
test/MC/RISCV/rv32i-valid.s | 10 +-
test/MC/RISCV/rv32m-valid.s | 10 +-
test/MC/RISCV/rv64a-valid.s | 5 +-
test/MC/RISCV/rv64c-valid.s | 8 +-
test/MC/RISCV/rv64d-aliases-valid.s | 27 +++
test/MC/RISCV/rv64d-valid.s | 21 +-
test/MC/RISCV/rv64f-aliases-valid.s | 27 +++
test/MC/RISCV/rv64f-valid.s | 21 +-
test/MC/RISCV/rv64i-aliases-invalid.s | 2 +-
test/MC/RISCV/rv64i-aliases-valid.s | 6 +-
test/MC/RISCV/rv64i-valid.s | 5 +-
test/MC/RISCV/rv64m-valid.s | 5 +-
test/MC/RISCV/rvd-aliases-valid.s | 53 ++++-
test/MC/RISCV/rvf-aliases-valid.s | 56 +++++-
test/MC/RISCV/rvi-aliases-valid.s | 8 +-
79 files changed, 1580 insertions(+), 1225 deletions(-)
create mode 100644 test/MC/RISCV/rv64d-aliases-valid.s
create mode 100644 test/MC/RISCV/rv64f-aliases-valid.s
diff --git a/lib/Target/RISCV/InstPrinter/RISCVInstPrinter.cpp b/lib/Target/RISCV/InstPrinter/RISCVInstPrinter.cpp
index d21c48ec65a..ff56fc5d90f 100644
--- a/lib/Target/RISCV/InstPrinter/RISCVInstPrinter.cpp
+++ b/lib/Target/RISCV/InstPrinter/RISCVInstPrinter.cpp
@@ -29,12 +29,10 @@ using namespace llvm;
#define PRINT_ALIAS_INSTR
#include "RISCVGenAsmWriter.inc"
-// Alias instruction emission is disabled by default. A subsequent patch will
-// change this default and fix all affected tests.
static cl::opt<bool>
NoAliases("riscv-no-aliases",
cl::desc("Disable the emission of assembler pseudo instructions"),
- cl::init(true),
+ cl::init(false),
cl::Hidden);
void RISCVInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
diff --git a/test/CodeGen/RISCV/addc-adde-sube-subc.ll b/test/CodeGen/RISCV/addc-adde-sube-subc.ll
index 0fd223534aa..1925a140e4f 100644
--- a/test/CodeGen/RISCV/addc-adde-sube-subc.ll
+++ b/test/CodeGen/RISCV/addc-adde-sube-subc.ll
@@ -13,13 +13,13 @@ define i64 @addc_adde(i64 %a, i64 %b) {
; RV32I-NEXT: add a2, a0, a2
; RV32I-NEXT: sltu a0, a2, a0
; RV32I-NEXT: add a1, a1, a0
-; RV32I-NEXT: addi a0, a2, 0
-; RV32I-NEXT: jalr zero, ra, 0
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
;
; RV64I-LABEL: addc_adde:
; RV64I: # %bb.0:
; RV64I-NEXT: add a0, a0, a1
-; RV64I-NEXT: jalr zero, ra, 0
+; RV64I-NEXT: ret
%1 = add i64 %a, %b
ret i64 %1
}
@@ -31,12 +31,12 @@ define i64 @subc_sube(i64 %a, i64 %b) {
; RV32I-NEXT: sltu a3, a0, a2
; RV32I-NEXT: sub a1, a1, a3
; RV32I-NEXT: sub a0, a0, a2
-; RV32I-NEXT: jalr zero, ra, 0
+; RV32I-NEXT: ret
;
; RV64I-LABEL: subc_sube:
; RV64I: # %bb.0:
; RV64I-NEXT: sub a0, a0, a1
-; RV64I-NEXT: jalr zero, ra, 0
+; RV64I-NEXT: ret
%1 = sub i64 %a, %b
ret i64 %1
}
@@ -71,7 +71,7 @@ define i128 @addc_adde128(i128 %a, i128 %b) {
; RV32I-NEXT: add a1, a4, a1
; RV32I-NEXT: add a1, a1, a3
; RV32I-NEXT: sw a1, 12(a0)
-; RV32I-NEXT: jalr zero, ra, 0
+; RV32I-NEXT: ret
;
; RV64I-LABEL: addc_adde128:
; RV64I: # %bb.0:
@@ -79,8 +79,8 @@ define i128 @addc_adde128(i128 %a, i128 %b) {
; RV64I-NEXT: add a2, a0, a2
; RV64I-NEXT: sltu a0, a2, a0
; RV64I-NEXT: add a1, a1, a0
-; RV64I-NEXT: addi a0, a2, 0
-; RV64I-NEXT: jalr zero, ra, 0
+; RV64I-NEXT: mv a0, a2
+; RV64I-NEXT: ret
%1 = add i128 %a, %b
ret i128 %1
}
@@ -93,7 +93,7 @@ define i128 @subc_sube128(i128 %a, i128 %b) {
; RV32I-NEXT: lw a5, 0(a2)
; RV32I-NEXT: lw a7, 0(a1)
; RV32I-NEXT: sltu t0, a7, a5
-; RV32I-NEXT: addi a3, t0, 0
+; RV32I-NEXT: mv a3, t0
; RV32I-NEXT: beq a6, a4, .LBB3_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: sltu a3, a6, a4
@@ -116,7 +116,7 @@ define i128 @subc_sube128(i128 %a, i128 %b) {
; RV32I-NEXT: sltu a2, a6, a3
; RV32I-NEXT: sub a1, a1, a2
; RV32I-NEXT: sw a1, 12(a0)
-; RV32I-NEXT: jalr zero, ra, 0
+; RV32I-NEXT: ret
;
; RV64I-LABEL: subc_sube128:
; RV64I: # %bb.0:
@@ -124,7 +124,7 @@ define i128 @subc_sube128(i128 %a, i128 %b) {
; RV64I-NEXT: sltu a3, a0, a2
; RV64I-NEXT: sub a1, a1, a3
; RV64I-NEXT: sub a0, a0, a2
-; RV64I-NEXT: jalr zero, ra, 0
+; RV64I-NEXT: ret
%1 = sub i128 %a, %b
ret i128 %1
}
diff --git a/test/CodeGen/RISCV/alloca.ll b/test/CodeGen/RISCV/alloca.ll
index 7815866f5c4..1472e8a302c 100644
--- a/test/CodeGen/RISCV/alloca.ll
+++ b/test/CodeGen/RISCV/alloca.ll
@@ -17,15 +17,15 @@ define void @simple_alloca(i32 %n) nounwind {
; RV32I-NEXT: addi a0, a0, 15
; RV32I-NEXT: andi a0, a0, -16
; RV32I-NEXT: sub a0, sp, a0
-; RV32I-NEXT: addi sp, a0, 0
+; RV32I-NEXT: mv sp, a0
; RV32I-NEXT: lui a1, %hi(notdead)
; RV32I-NEXT: addi a1, a1, %lo(notdead)
-; RV32I-NEXT: jalr ra, a1, 0
+; RV32I-NEXT: jalr a1
; RV32I-NEXT: addi sp, s0, -16
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
-; RV32I-NEXT: jalr zero, ra, 0
+; RV32I-NEXT: ret
%1 = alloca i8, i32 %n
call void @notdead(i8* %1)
ret void
@@ -42,21 +42,21 @@ define void @scoped_alloca(i32 %n) nounwind {
; RV32I-NEXT: sw s0, 8(sp)
; RV32I-NEXT: sw s1, 4(sp)
; RV32I-NEXT: addi s0, sp, 16
-; RV32I-NEXT: addi s1, sp, 0
+; RV32I-NEXT: mv s1, sp
; RV32I-NEXT: addi a0, a0, 15
; RV32I-NEXT: andi a0, a0, -16
; RV32I-NEXT: sub a0, sp, a0
-; RV32I-NEXT: addi sp, a0, 0
+; RV32I-NEXT: mv sp, a0
; RV32I-NEXT: lui a1, %hi(notdead)
; RV32I-NEXT: addi a1, a1, %lo(notdead)
-; RV32I-NEXT: jalr ra, a1, 0
-; RV32I-NEXT: addi sp, s1, 0
+; RV32I-NEXT: jalr a1
+; RV32I-NEXT: mv sp, s1
; RV32I-NEXT: addi sp, s0, -16
; RV32I-NEXT: lw s1, 4(sp)
; RV32I-NEXT: lw s0, 8(sp)
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
-; RV32I-NEXT: jalr zero, ra, 0
+; RV32I-NEXT: ret
%sp = call i8* @llvm.stacksave()
%addr = alloca i8, i32 %n
call void @notdead(i8* %addr)
diff --git a/test/CodeGen/RISCV/alu32.ll b/test/CodeGen/RISCV/alu32.ll
index 106626f07f4..3b194089f91 100644
--- a/test/CodeGen/RISCV/alu32.ll
+++ b/test/CodeGen/RISCV/alu32.ll
@@ -14,12 +14,12 @@ define i32 @addi(i32 %a) nounwind {
; RV32I-LABEL: addi:
; RV32I: # %bb.0:
; RV32I-NEXT: addi a0, a0, 1
-; RV32I-NEXT: jalr zero, ra, 0
+; RV32I-NEXT: ret
;
; RV64I-LABEL: addi:
; RV64I: # %bb.0:
; RV64I-NEXT: addi a0, a0, 1
-; RV64I-NEXT: jalr zero, ra, 0
+; RV64I-NEXT: ret
%1 = add i32 %a, 1
ret i32 %1
}
@@ -28,13 +28,13 @@ define i32 @slti(i32 %a) nounwind {
; RV32I-LABEL: slti:
; RV32I: # %bb.0:
; RV32I-NEXT: slti a0, a0, 2
-; RV32I-NEXT: jalr zero, ra, 0
+; RV32I-NEXT: ret
;
; RV64I-LABEL: slti:
; RV64I: # %bb.0:
-; RV64I-NEXT: addiw a0, a0, 0
+; RV64I-NEXT: sext.w a0, a0
; RV64I-NEXT: slti a0, a0, 2
-; RV64I-NEXT: jalr zero, ra, 0
+; RV64I-NEXT: ret
%1 = icmp slt i32 %a, 2
%2 = zext i1 %1 to i32
ret i32 %2
@@ -44,12 +44,12 @@ define i32 @sltiu(i32 %a) nounwind {
; RV32I-LABEL: sltiu:
; RV32I: # %bb.0:
; RV32I-NEXT: sltiu a0, a0, 3
-; RV32I-NEXT: jalr zero, ra, 0
+; RV32I-NEXT: ret
;
; RV64I-LABEL: sltiu:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 0
-; RV64I-NEXT: addiw a2, a1, 0
+; RV64I-NEXT: sext.w a2, a1
; RV64I-NEXT: slli a2, a2, 32
; RV64I-NEXT: addiw a1, a1, -1
; RV64I-NEXT: slli a1, a1, 32
@@ -57,7 +57,7 @@ define i32 @sltiu(i32 %a) nounwind {
; RV64I-NEXT: or a1, a2, a1
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: sltiu a0, a0, 3
-; RV64I-NEXT: jalr zero, ra, 0
+; RV64I-NEXT: ret
%1 = icmp ult i32 %a, 3
%2 = zext i1 %1 to i32
ret i32 %2
@@ -67,12 +67,12 @@ define i32 @xori(i32 %a) nounwind {
; RV32I-LABEL: xori:
; RV32I: # %bb.0:
; RV32I-NEXT: xori a0, a0, 4
-; RV32I-NEXT: jalr zero, ra, 0
+; RV32I-NEXT: ret
;
; RV64I-LABEL: xori:
; RV64I: # %bb.0:
; RV64I-NEXT: xori a0, a0, 4
-; RV64I-NEXT: jalr zero, ra, 0
+; RV64I-NEXT: ret
%1 = xor i32 %a, 4
ret i32 %1
}
@@ -81,12 +81,12 @@ define i32 @ori(i32 %a) nounwind {
; RV32I-LABEL: ori:
; RV32I: # %bb.0:
; RV32I-NEXT: ori a0, a0, 5
-; RV32I-NEXT: jalr zero, ra, 0
+; RV32I-NEXT: ret
;
; RV64I-LABEL: ori:
; RV64I: # %bb.0:
; RV64I-NEXT: ori a0, a0, 5
-; RV64I-NEXT: jalr zero, ra, 0
+; RV64I-NEXT: ret
%1 = or i32 %a, 5
ret i32 %1
}
@@ -95,12 +95,12 @@ define i32 @andi(i32 %a) nounwind {
; RV32I-LABEL: andi:
; RV32I: # %bb.0:
; RV32I-NEXT: andi a0, a0, 6
-; RV32I-NEXT: jalr zero, ra, 0
+; RV32I-NEXT: ret
;
; RV64I-LABEL: andi:
; RV64I: # %bb.0:
; RV64I-NEXT: andi a0, a0, 6
-; RV64I-NEXT: jalr zero, ra, 0
+; RV64I-NEXT: ret
%1 = and i32 %a, 6
ret i32 %1
}
@@ -109,12 +109,12 @@ define i32 @slli(i32 %a) nounwind {
; RV32I-LABEL: slli:
; RV32I: # %bb.0:
; RV32I-NEXT: slli a0, a0, 7
-; RV32I-NEXT: jalr zero, ra, 0
+; RV32I-NEXT: ret
;
; RV64I-LABEL: slli:
; RV64I: # %bb.0:
; RV64I-NEXT: slli a0, a0, 7
-; RV64I-NEXT: jalr zero, ra, 0
+; RV64I-NEXT: ret
%1 = shl i32 %a, 7
ret i32 %1
}
@@ -123,12 +123,12 @@ define i32 @srli(i32 %a) nounwind {
; RV32I-LABEL: srli:
; RV32I: # %bb.0:
; RV32I-NEXT: srli a0, a0, 8
-; RV32I-NEXT: jalr zero, ra, 0
+; RV32I-NEXT: ret
;
; RV64I-LABEL: srli:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a1, 0
-; RV64I-NEXT: addiw a2, a1, 0
+; RV64I-NEXT: sext.w a2, a1
; RV64I-NEXT: slli a2, a2, 32
; RV64I-NEXT: addiw a1, a1, -256
; RV64I-NEXT: slli a1, a1, 32
@@ -136,7 +136,7 @@ define i32 @srli(i32 %a) nounwind {
; RV64I-NEXT: or a1, a2, a1
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: srli a0, a0, 8
-; RV64I-NEXT: jalr zero, ra, 0
+; RV64I-NEXT: ret
%1 = lshr i32 %a, 8
ret i32 %1
}
@@ -145,13 +145,13 @@ define i32 @srai(i32 %a) nounwind {
; RV32I-LABEL: srai:
; RV32I: # %bb.0:
; RV32I-NEXT: srai a0, a0, 9
-; RV32I-NEXT: jalr zero, ra, 0
+; RV32I-NEXT: ret
;
; RV64I-LABEL: srai:
; RV64I: # %bb.0:
-; RV64I-NEXT: addiw a0, a0, 0
+; RV64I-NEXT: sext.w a0, a0
; RV64I-NEXT: srai a0, a0, 9
-; RV64I-NEXT: jalr zero, ra, 0
+; RV64I-NEXT: ret
%1 = ashr i32 %a, 9
ret i32 %1
}
@@ -162,12 +162,12 @@ define i32 @add(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: add:
; RV32I: # %bb.0:
; RV32I-NEXT: add a0, a0, a1
-; RV32I-NEXT: jalr zero, ra, 0
+; RV32I-NEXT: ret
;
; RV64I-LABEL: add:
; RV64I: # %bb.0:
; RV64I-NEXT: add a0, a0, a1
-; RV64I-NEXT: jalr zero, ra, 0
+; RV64I-NEXT: ret
%1 = add i32 %a, %b
ret i32 %1
}
@@ -176,12 +176,12 @@ define i32 @sub(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: sub:
; RV32I: # %bb.0:
; RV32I-NEXT: sub a0, a0, a1
-; RV32I-NEXT: jalr zero, ra, 0
+; RV32I-NEXT: ret
;
; RV64I-LABEL: sub:
; RV64I: # %bb.0:
; RV64I-NEXT: sub a0, a0, a1
-; RV64I-NEXT: jalr zero, ra, 0
+; RV64I-NEXT: ret
%1 = sub i32 %a, %b
ret i32 %1
}
@@ -190,12 +190,12 @@ define i32 @sll(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: sll:
; RV32I: # %bb.0:
; RV32I-NEXT: sll a0, a0, a1
-; RV32I-NEXT: jalr zero, ra, 0
+; RV32I-NEXT: ret
;
; RV64I-LABEL: sll:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a2, 0
-; RV64I-NEXT: addiw a3, a2, 0
+; RV64I-NEXT: sext.w a3, a2
; RV64I-NEXT: slli a3, a3, 32
; RV64I-NEXT: addiw a2, a2, -1
; RV64I-NEXT: slli a2, a2, 32
@@ -203,7 +203,7 @@ define i32 @sll(i32 %a, i32 %b) nounwind {
; RV64I-NEXT: or a2, a3, a2
; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: sll a0, a0, a1
-; RV64I-NEXT: jalr zero, ra, 0
+; RV64I-NEXT: ret
%1 = shl i32 %a, %b
ret i32 %1
}
@@ -212,14 +212,14 @@ define i32 @slt(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: slt:
; RV32I: # %bb.0:
; RV32I-NEXT: slt a0, a0, a1
-; RV32I-NEXT: jalr zero, ra, 0
+; RV32I-NEXT: ret
;
; RV64I-LABEL: slt:
; RV64I: # %bb.0:
-; RV64I-NEXT: addiw a1, a1, 0
-; RV64I-NEXT: addiw a0, a0, 0
+; RV64I-NEXT: sext.w a1, a1
+; RV64I-NEXT: sext.w a0, a0
; RV64I-NEXT: slt a0, a0, a1
-; RV64I-NEXT: jalr zero, ra, 0
+; RV64I-NEXT: ret
%1 = icmp slt i32 %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -229,12 +229,12 @@ define i32 @sltu(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: sltu:
; RV32I: # %bb.0:
; RV32I-NEXT: sltu a0, a0, a1
-; RV32I-NEXT: jalr zero, ra, 0
+; RV32I-NEXT: ret
;
; RV64I-LABEL: sltu:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a2, 0
-; RV64I-NEXT: addiw a3, a2, 0
+; RV64I-NEXT: sext.w a3, a2
; RV64I-NEXT: slli a3, a3, 32
; RV64I-NEXT: addiw a2, a2, -1
; RV64I-NEXT: slli a2, a2, 32
@@ -243,7 +243,7 @@ define i32 @sltu(i32 %a, i32 %b) nounwind {
; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: sltu a0, a0, a1
-; RV64I-NEXT: jalr zero, ra, 0
+; RV64I-NEXT: ret
%1 = icmp ult i32 %a, %b
%2 = zext i1 %1 to i32
ret i32 %2
@@ -253,12 +253,12 @@ define i32 @xor(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: xor:
; RV32I: # %bb.0:
; RV32I-NEXT: xor a0, a0, a1
-; RV32I-NEXT: jalr zero, ra, 0
+; RV32I-NEXT: ret
;
; RV64I-LABEL: xor:
; RV64I: # %bb.0:
; RV64I-NEXT: xor a0, a0, a1
-; RV64I-NEXT: jalr zero, ra, 0
+; RV64I-NEXT: ret
%1 = xor i32 %a, %b
ret i32 %1
}
@@ -267,12 +267,12 @@ define i32 @srl(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: srl:
; RV32I: # %bb.0:
; RV32I-NEXT: srl a0, a0, a1
-; RV32I-NEXT: jalr zero, ra, 0
+; RV32I-NEXT: ret
;
; RV64I-LABEL: srl:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a2, 0
-; RV64I-NEXT: addiw a3, a2, 0
+; RV64I-NEXT: sext.w a3, a2
; RV64I-NEXT: slli a3, a3, 32
; RV64I-NEXT: addiw a2, a2, -1
; RV64I-NEXT: slli a2, a2, 32
@@ -280,7 +280,7 @@ define i32 @srl(i32 %a, i32 %b) nounwind {
; RV64I-NEXT: or a2, a3, a2
; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: srlw a0, a0, a1
-; RV64I-NEXT: jalr zero, ra, 0
+; RV64I-NEXT: ret
%1 = lshr i32 %a, %b
ret i32 %1
}
@@ -289,12 +289,12 @@ define i32 @sra(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: sra:
; RV32I: # %bb.0:
; RV32I-NEXT: sra a0, a0, a1
-; RV32I-NEXT: jalr zero, ra, 0
+; RV32I-NEXT: ret
;
; RV64I-LABEL: sra:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a2, 0
-; RV64I-NEXT: addiw a3, a2, 0
+; RV64I-NEXT: sext.w a3, a2
; RV64I-NEXT: slli a3, a3, 32
; RV64I-NEXT: addiw a2, a2, -1
; RV64I-NEXT: slli a2, a2, 32
@@ -302,7 +302,7 @@ define i32 @sra(i32 %a, i32 %b) nounwind {
; RV64I-NEXT: or a2, a3, a2
; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: sraw a0, a0, a1
-; RV64I-NEXT: jalr zero, ra, 0
+; RV64I-NEXT: ret
%1 = ashr i32 %a, %b
ret i32 %1
}
@@ -311,12 +311,12 @@ define i32 @or(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: or:
; RV32I: # %bb.0:
; RV32I-NEXT: or a0, a0, a1
-; RV32I-NEXT: jalr zero, ra, 0
+; RV32I-NEXT: ret
;
; RV64I-LABEL: or:
; RV64I: # %bb.0:
; RV64I-NEXT: or a0, a0, a1
-; RV64I-NEXT: jalr zero, ra, 0
+; RV64I-NEXT: ret
%1 = or i32 %a, %b
ret i32 %1
}
@@ -325,12 +325,12 @@ define i32 @and(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: and:
; RV32I: # %bb.0:
; RV32I-NEXT: and a0, a0, a1
-; RV32I-NEXT: jalr zero, ra, 0
+; RV32I-NEXT: ret
;
; RV64I-LABEL: and:
; RV64I: # %bb.0:
; RV64I-NEXT: and a0, a0, a1
-; RV64I-NEXT: jalr zero, ra, 0
+; RV64I-NEXT: ret
%1 = and i32 %a, %b
ret i32 %1
}
diff --git a/test/CodeGen/RISCV/alu64.ll b/test/CodeGen/RISCV/alu64.ll
index 2a289387fb3..75b3c5f2e14 100644
--- a/test/CodeGen/RISCV/alu64.ll
+++ b/test/CodeGen/RISCV/alu64.ll
@@ -10,15 +10,15 @@ define i64 @addi(i64 %a) nounwind {
; RV64I-LABEL: addi:
; RV64I: # %bb.0:
; RV64I-NEXT: addi a0, a0, 1
-; RV64I-NEXT: jalr zero, ra, 0
+; RV64I-NEXT: ret
;
; RV32I-LABEL: addi:
; RV32I: # %bb.0:
; RV32I-NEXT: addi a2, a0, 1
; RV32I-NEXT: sltu a0, a2, a0
; RV32I-NEXT: add a1, a1, a0
-; RV32I-NEXT: addi a0, a2, 0
-; RV32I-NEXT: jalr zero, ra, 0
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
%1 = add i64 %a, 1
ret i64 %1
}
@@ -27,19 +27,19 @@ define i64 @slti(i64 %a) nounwind {
; RV64I-LABEL: slti:
; RV64I: # %bb.0:
; RV64I-NEXT: slti a0, a0, 2
-; RV64I-NEXT: jalr zero, ra, 0
+; RV64I-NEXT: ret
;
; RV32I-LABEL: slti:
; RV32I: # %bb.0:
-; RV32I-NEXT: beq a1, zero, .LBB1_2
+; RV32I-NEXT: beqz a1, .LBB1_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: slti a0, a1, 0
-; RV32I-NEXT: addi a1, zero, 0
-; RV32I-NEXT: jalr zero, ra, 0
+; RV32I-NEXT: mv a1, zero
+; RV32I-NEXT: ret
; RV32I-NEXT: .LBB1_2:
; RV32I-NEXT: sltiu a0, a0, 2
-; RV32I-NEXT: addi a1, zero, 0
-; RV32I-NEXT: jalr zero, ra, 0
+; RV32I-NEXT: mv a1, zero
+; RV32I-NEXT: ret
%1 = icmp slt i64 %a, 2
%2 = zext i1 %1 to i64
ret i64 %2
@@ -49,19 +49,19 @@ define i64 @sltiu(i64 %a) nounwind {
; RV64I-LABEL: sltiu:
; RV64I: # %bb.0:
; RV64I-NEXT: sltiu a0, a0, 3
-; RV64I-NEXT: jalr zero, ra, 0
+; RV64I-NEXT: ret
;
; RV32I-LABEL: sltiu:
; RV32I: # %bb.0:
-; RV32I-NEXT: beq a1, zero, .LBB2_2
+; RV32I-NEXT: beqz a1, .LBB2_2
; RV32I-NEXT: # %bb.1:
-; RV32I-NEXT: addi a0, zero, 0
-; RV32I-NEXT: addi a1, zero, 0
-; RV32I-NEXT: jalr zero, ra, 0
+; RV32I-NEXT: mv a0, zero
+; RV32I-NEXT: mv a1, zero
+; RV32I-NEXT: ret
; RV32I-NEXT: .LBB2_2:
; RV32I-NEXT: sltiu a0, a0, 3
-; RV32I-NEXT: addi a1, zero, 0
-; RV32I-NEXT: jalr zero, ra, 0
+; RV32I-NEXT: mv a1, zero
+; RV32I-NEXT: ret
%1 = icmp ult i64 %a, 3
%2 = zext i1 %1 to i64
ret i64 %2
@@ -71,12 +71,12 @@ define i64 @xori(i64 %a) nounwind {
; RV64I-LABEL: xori:
; RV64I: # %bb.0:
; RV64I-NEXT: xori a0, a0, 4
-; RV64I-NEXT: jalr zero, ra, 0
+; RV64I-NEXT: ret
;
; RV32I-LABEL: xori:
; RV32I: # %bb.0:
; RV32I-NEXT: xori a0, a0, 4
-; RV32I-NEXT: jalr zero, ra, 0
+; RV32I-NEXT: ret
%1 = xor i64 %a, 4
ret i64 %1
}
@@ -85,12 +85,12 @@ define i64 @ori(i64 %a) nounwind {
; RV64I-LABEL: ori:
; RV64I: # %bb.0:
; RV64I-NEXT: ori a0, a0, 5
-; RV64I-NEXT: jalr zero, ra, 0
+; RV64I-NEXT: ret
;
; RV32I-LABEL: ori:
; RV32I: # %bb.0:
; RV32I-NEXT: ori a0, a0, 5
-; RV32I-NEXT: jalr zero, ra, 0
+; RV32I-NEXT: ret
%1 = or i64 %a, 5
ret i64 %1
}
@@ -99,13 +99,13 @@ define i64 @andi(i64 %a) nounwind {
; RV64I-LABEL: andi:
; RV64I: # %bb.0:
; RV64I-NEXT: andi a0, a0, 6
-; RV64I-NEXT: jalr zero, ra, 0
+; RV64I-NEXT: ret
;
; RV32I-LABEL: andi:
; RV32I: # %bb.0:
; RV32I-NEXT: andi a0, a0, 6
-; RV32I-NEXT: addi a1, zero, 0
-; RV32I-NEXT: jalr zero, ra, 0
+; RV32I-NEXT: mv a1, zero
+; RV32I-NEXT: ret
%1 = and i64 %a, 6
ret i64 %1
}
@@ -114,7 +114,7 @@ define i64 @slli(i64 %a) nounwind {
; RV64I-LABEL: slli:
; RV64I: # %bb.0:
; RV64I-NEXT: slli a0, a0, 7
-; RV64I-NEXT: jalr zero, ra, 0
+; RV64I-NEXT: ret
;
; RV32I-LABEL: slli:
; RV32I: # %bb.0:
@@ -122,7 +122,7 @@ define i64 @slli(i64 %a) nounwind {
; RV32I-NEXT: srli a2, a0, 25
; RV32I-NEXT: or a1, a1, a2
; RV32I-NEXT: slli a0, a0, 7
-; RV32I-NEXT: jalr zero, ra, 0
+; RV32I-NEXT: ret
%1 = shl i64 %a, 7
ret i64 %1
}
@@ -131,7 +131,7 @@ define i64 @srli(i64 %a) nounwind {
; RV64I-LABEL: srli:
; RV64I: # %bb.0:
; RV64I-NEXT: srli a0, a0, 8
-; RV64I-NEXT: jalr zero, ra, 0
+; RV64I-NEXT: ret
;
; RV32I-LABEL: srli:
; RV32I: # %bb.0:
@@ -139,7 +139,7 @@ define i64 @srli(i64 %a) nounwind {
; RV32I-NEXT: slli a2, a1, 24
; RV32I-NEXT: or a0, a0, a2
; RV32I-NEXT: srli a1, a1, 8
-; RV32I-NEXT: jalr zero, ra, 0
+; RV32I-NEXT: ret
%1 = lshr i64 %a, 8
ret i64 %1
}
@@ -148,7 +148,7 @@ define i64 @srai(i64 %a) nounwind {
; RV64I-LABEL: srai:
; RV64I: # %bb.0:
; RV64I-NEXT: srai a0, a0, 9
-; RV64I-NEXT: jalr zero, ra, 0
+; RV64I-NEXT: ret
;
; RV32I-LABEL: srai:
; RV32I: # %bb.0:
@@ -156,7 +156,7 @@ define i64 @srai(i64 %a) nounwind {
; RV32I-NEXT: slli a2, a1, 23
; RV32I-NEXT: or a0, a0, a2
; RV32I-NEXT: srai a1, a1, 9
-; RV32I-NEXT: jalr zero, ra, 0
+; RV32I-NEXT: ret
%1 = ashr i64 %a, 9
ret i64 %1
}
@@ -167,7 +167,7 @@ define i64 @add(i64 %a, i64 %b) nounwind {
; RV64I-LABEL: add:
; RV64I: # %bb.0:
; RV64I-NEXT: add a0, a0, a1
-; RV64I-NEXT: jalr zero, ra, 0
+; RV64I-NEXT: ret
;
; RV32I-LABEL: add:
; RV32I: # %bb.0:
@@ -175,8 +175,8 @@ define i64 @add(i64 %a, i64 %b) nounwind {
; RV32I-NEXT: add a2, a0, a2
; RV32I-NEXT: sltu a0, a2, a0
; RV32I-NEXT: add a1, a1, a0
-; RV32I-NEXT: addi a0, a2, 0
-; RV32I-NEXT: jalr zero, ra, 0
+; RV32I-NEXT: mv a0, a2
+; RV32I-NEXT: ret
%1 = add i64 %a, %b
ret i64 %1
}
@@ -185,7 +185,7 @@ define i64 @sub(i64 %a, i64 %b) nounwind {
; RV64I-LABEL: sub:
; RV64I: # %bb.0:
; RV64I-NEXT: sub a0, a0, a1
-; RV64I-NEXT: jalr zero, ra, 0
+; RV64I-NEXT: ret
;
; RV32I-LABEL: sub:
; RV32I: # %bb.0:
@@ -193,7 +193,7 @@ define i64 @sub(i64 %a, i64 %b) nounwind {
; RV32I-NEXT: sltu a3, a0, a2
; RV32I-NEXT: sub a1, a1, a3
; RV32I-NEXT: sub a0, a0, a2
-; RV32I-NEXT: jalr zero, ra, 0
+; RV32I-NEXT: ret
%1 = sub i64 %a, %b
ret i64 %1
}
@@ -202,7 +202,7 @@ define i64 @sll(i64 %a, i64 %b) nounwind {
; RV64I-LABEL: sll:
; RV64I: # %bb.0:
; RV64I-NEXT: sll a0, a0, a1
-; RV64I-NEXT: jalr zero, ra, 0
+; RV64I-NEXT: ret
;
; RV32I-LABEL: sll:
; RV32I: # %bb.0:
@@ -210,10 +210,10 @@ define i64 @sll(i64 %a, i64 %b) nounwind {
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: lui a3, %hi(__ashldi3)
; RV32I-NEXT: addi a3, a3, %lo(__ashldi3)
-; RV32I-NEXT: jalr ra, a3, 0
+; RV32I-NEXT: jalr a3
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
-; RV32I-NEXT: jalr zero, ra, 0
+; RV32I-NEXT: ret
%1 = shl i64 %a, %b
ret i64 %1
}
@@ -222,19 +222,19 @@ define i64 @slt(i64 %a, i64 %b) nounwind {
; RV64I-LABEL: slt:
; RV64I: # %bb.0:
; RV64I-NEXT: slt a0, a0, a1
-; RV64I-NEXT: jalr zero, ra, 0
+; RV64I-NEXT: ret
;
; RV32I-LABEL: slt:
; RV32I: # %bb.0:
; RV32I-NEXT: beq a1, a3, .LBB12_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: slt a0, a1, a3
-; RV32I-NEXT: addi a1, zero, 0
-; RV32I-NEXT: jalr zero, ra, 0
+; RV32I-NEXT: mv a1, zero
+; RV32I-NEXT: ret
; RV32I-NEXT: .LBB12_2:
; RV32I-NEXT: sltu a0, a0, a2
-; RV32I-NEXT: addi a1, zero, 0
-; RV32I-NEXT: jalr zero, ra, 0
+; RV32I-NEXT: mv a1, zero
+; RV32I-NEXT: ret
%1 = icmp slt i64 %a, %b
%2 = zext i1 %1 to i64
ret i64 %2
@@ -244,19 +244,19 @@ define i64 @sltu(i64 %a, i64 %b) nounwind {
; RV64I-LABEL: sltu:
; RV64I: # %bb.0:
; RV64I-NEXT: sltu a0, a0, a1
-; RV64I-NEXT: jalr zero, ra, 0
+; RV64I-NEXT: ret
;
; RV32I-LABEL: sltu:
; RV32I: # %bb.0:
; RV32I-NEXT: beq a1, a3, .LBB13_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: sltu a0, a1, a3
-; RV32I-NEXT: addi a1, zero, 0
-; RV32I-NEXT: jalr zero, ra, 0
+; RV32I-NEXT: mv a1, zero
+; RV32I-NEXT: ret
; RV32I-NEXT: .LBB13_2:
; RV32I-NEXT: sltu a0, a0, a2
-; RV32I-NEXT: addi a1, zero, 0
-; RV32I-NEXT: jalr zero, ra, 0
+; RV32I-NEXT: mv a1, zero
+; RV32I-NEXT: ret
%1 = icmp ult i64 %a, %b
%2 = zext i1 %1 to i64
ret i64 %2
@@ -266,13 +266,13 @@ define i64 @xor(i64 %a, i64 %b) nounwind {
; RV64I-LABEL: xor:
; RV64I: # %bb.0:
; RV64I-NEXT: xor a0, a0, a1
-; RV64I-NEXT: jalr zero, ra, 0
+; RV64I-NEXT: ret
;
; RV32I-LABEL: xor:
; RV32I: # %bb.0:
; RV32I-NEXT: xor a0, a0, a2
; RV32I-NEXT: xor a1, a1, a3
-; RV32I-NEXT: jalr zero, ra, 0
+; RV32I-NEXT: ret
%1 = xor i64 %a, %b
ret i64 %1
}
@@ -281,7 +281,7 @@ define i64 @srl(i64 %a, i64 %b) nounwind {
; RV64I-LABEL: srl:
; RV64I: # %bb.0:
; RV64I-NEXT: srl a0, a0, a1
-; RV64I-NEXT: jalr zero, ra, 0
+; RV64I-NEXT: ret
;
; RV32I-LABEL: srl:
; RV32I: # %bb.0:
@@ -289,10 +289,10 @@ define i64 @srl(i64 %a, i64 %b) nounwind {
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: lui a3, %hi(__lshrdi3)
; RV32I-NEXT: addi a3, a3, %lo(__lshrdi3)
-; RV32I-NEXT: jalr ra, a3, 0
+; RV32I-NEXT: jalr a3
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
-; RV32I-NEXT: jalr zero, ra, 0
+; RV32I-NEXT: ret
%1 = lshr i64 %a, %b
ret i64 %1
}
@@ -301,7 +301,7 @@ define i64 @sra(i64 %a, i64 %b) nounwind {
; RV64I-LABEL: sra:
; RV64I: # %bb.0:
; RV64I-NEXT: sra a0, a0, a1
-; RV64I-NEXT: jalr zero, ra, 0
+; RV64I-NEXT: ret
;
; RV32I-LABEL: sra:
; RV32I: # %bb.0:
@@ -309,10 +309,10 @@ define i64 @sra(i64 %a, i64 %b) nounwind {
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: lui a3, %hi(__ashrdi3)
; RV32I-NEXT: addi a3, a3, %lo(__ashrdi3)
-; RV32I-NEXT: jalr ra, a3, 0
+; RV32I-NEXT: jalr a3
; RV32I-NEXT: lw ra, 12(sp)
; RV32I-NEXT: addi sp, sp, 16
-; RV32I-NEXT: jalr zero, ra, 0
+; RV32I-NEXT: ret
%1 = ashr i64 %a, %b
ret i64 %1
}
@@ -321,13 +321,13 @@ define i64 @or(i64 %a, i64 %b) nounwind {
; RV64I-LABEL: or:
; RV64I: # %bb.0:
; RV64I-NEXT: or a0, a0, a1
-; RV64I-NEXT: jalr zero, ra, 0
+; RV64I-NEXT: ret
;
; RV32I-LABEL: or:
; RV32I: # %bb.0:
; RV32I-NEXT: or a0, a0, a2
; RV32I-NEXT: or a1, a1, a3
-; RV32I-NEXT: jalr zero, ra, 0
+; RV32I-NEXT: ret
%1 = or i64 %a, %b
ret i64 %1
}
@@ -336,13 +336,13 @@ define i64 @and(i64 %a, i64 %b) nounwind {
; RV64I-LABEL: and:
; RV64I: # %bb.0:
; RV64I-NEXT: and a0, a0, a1
-; RV64I-NEXT: jalr zero, ra, 0
+; RV64I-NEXT: ret
;
; RV32I-LABEL: and:
; RV32I: # %bb.0:
; RV32I-NEXT: and a0, a0, a2
; RV32I-NEXT: and a1, a1, a3
-; RV32I-NEXT: jalr zero, ra, 0
+; RV32I-NEXT: ret
%1 = and i64 %a, %b
ret i64 %1
}
@@ -351,12 +351,12 @@ define signext i32 @addiw(i32 signext %a) {
; RV64I-LABEL: addiw:
; RV64I: # %bb.0:
; RV64I-NEXT: addiw a0, a0, 123
-; RV64I-NEXT: jalr zero, ra, 0
+; RV64I-NEXT: ret
;
; RV32I-LABEL: addiw:
; RV32I: # %bb.0:
; RV32I-NEXT: addi a0, a0, 123
-; RV32I-NEXT: jalr zero, ra, 0
+; RV32I-NEXT: ret
%1 = add i32 %a, 123
ret i32 %1
}