state of atomic support

[dvc94ch]

There are some patches for atomic support in the backend, but there are still some parts missing to build a rust memory allocator or rust's libstd.

LLVM ERROR: Cannot select: t32: i32,ch = AtomicCmpSwap<Volatile LDST1[%70]> t12, t4, t39, t26
  t4: i32,ch = load<LD4[%15](dereferenceable)> t0, FrameIndex:i32<9>, undef:i32
    t1: i32 = FrameIndex<9>
    t3: i32 = undef
  t39: i32,ch = load<LD1[%14](dereferenceable), zext from i8> t0, FrameIndex:i32<8>, undef:i32
    t5: i32 = FrameIndex<8>
    t3: i32 = undef
  t26: i32,ch = load<LD1[%13](dereferenceable), anyext from i8> t0, FrameIndex:i32<7>, undef:i32
    t7: i32 = FrameIndex<7>
    t3: i32 = undef
In function: _ZN4core4sync6atomic23atomic_compare_exchange17h1807facac1d33089E

LLVM ERROR: Cannot select: t22: i32,ch = AtomicCmpSwap<Volatile LDST4[%9]> t11, t8, Constant:i32<2>, Constant:i32<0>
  t8: i32 = add nuw t2, Constant:i32<24>
    t2: i32,ch = CopyFromReg t0, Register:i32 %0
      t1: i32 = Register %0
    t7: i32 = Constant<24>
  t12: i32 = Constant<2>
  t4: i32 = Constant<0>
In function: _ZN3std6thread4park17h5b16deb9482d0a5bE

[asb]

Yes, there are certainly gaps I was going to hold off finalising atomics codegen until the memory model working group finalise the C++ mappings (as then I can get the whole thing reviewed by the RISC-V memory model people), but this seems to be taking longer than expected. Once I've caught up on code reviews and made more progress in merging F+D codegen upstream I should be able to take another look at this.

[luismarques]

D's runtime library also needs more complete atomic support.