0001-Revert-upstreamed-RISC-V-changes.patch
0002-RISCV-Add-the-RISCV-target-and-compiler-driver.patch
0003-RISCV-Implement-clang-driver-for-the-baremetal-RISCV.patch
0004-RISCV-Implement-RISCV-ABI-lowering.patch
0001-Revert-upstreamed-RISC-V-changes.patch
0002-RISCV-Recognise-riscv32-and-riscv64-in-triple-parsin.patch
0003-RISCV-Add-RISC-V-ELF-defines.patch
0004-RISCV-Add-stub-backend.patch
0005-RISCV-Add-basic-RISCV-InstrFormats-InstrInfo-Registe.patch
0006-RISCV-Add-bare-bones-RISC-V-MCTargetDesc.patch
0007-RISCV-Add-basic-RISCVAsmParser.patch
0008-RISCV-Add-RISCVInstPrinter-and-basic-MC-assembler-te.patch
0009-RISCV-Add-support-for-all-RV32I-instructions.patch
0010-RISCV-Add-support-for-disassembly.patch
0011-RISCV-Add-common-fixups-and-relocations.patch
0012-Add-RISC-V-support-to-update_llc_test_checks.py.patch
0013-RISCV-Initial-codegen-support-for-ALU-operations.patch
0014-RISCV-Codegen-support-for-materializing-constants.patch
0015-RISCV-Codegen-support-for-memory-operations.patch
0016-RISCV-Codegen-support-for-memory-operations-on-globa.patch
0017-RISCV-Codegen-for-conditional-branches.patch
0018-RISCV-Support-for-function-calls.patch
0019-RISCV-Implement-lowering-of-ISD-SELECT.patch
0020-RISCV-Support-and-tests-for-a-variety-of-additional-.patch
0021-RISCV-Use-register-X0-ZERO-for-constant-0.patch
0022-RISCV-Support-lowering-FrameIndex.patch
0023-RISCV-Implement-prolog-and-epilog-insertion.patch
0024-RISCV-Allow-lowering-of-dynamic_stackalloc-stacksave.patch
0025-RISCV-Add-custom-CC_RISCV-calling-convention-and-imp.patch
0026-RISCV-Support-for-varargs.patch
0027-RISCV-Support-stack-frames-and-offsets-up-to-32-bits.patch
0028-RISCV-Add-basic-support-for-inline-asm-constraints.patch
0029-RISCV-Add-support-for-llvm.-frameaddress-returnaddre.patch
0030-RISCV-Implement-branch-analysis.patch
0031-RISCV-Implement-support-for-the-BranchRelaxation-pas.patch
0032-RISCV-Reserve-an-emergency-spill-slot-for-the-regist.patch
0033-RISCV-MC-layer-support-for-the-standard-RV32M-instru.patch
0034-RISCV-MC-layer-support-for-the-standard-RV32A-instru.patch
0035-RISCV-MC-layer-support-for-the-standard-RV32F-instru.patch
0036-RISCV-MC-layer-support-for-the-standard-RV32D-instru.patch
0037-RISCV-MC-layer-support-for-the-standard-RV64I-instru.patch
0038-RISCV-MC-layer-support-for-the-standard-RV64M-instru.patch
0039-RISCV-MC-layer-support-for-the-standard-RV64A-instru.patch
0040-RISCV-MC-layer-support-for-the-standard-RV64F-instru.patch
0041-RISCV-MC-layer-support-for-the-standard-RV64D-instru.patch
0042-RISCV-Implement-frame-pointer-elimination.patch
0043-RISCV-Codegen-support-for-the-standard-RV32M-instruc.patch
0044-RISCV-Add-initial-RV64I-codegen-support.patch
0045-LegalizeDAG-promote-frameaddr-returnaddr-arguments-t.patch
0046-LegalizeDAG-promote-PREFETCH-operands-to-native-inte.patch
0047-RISCV-Initial-support-for-emitting-call-frame-inform.patch
0048-RISCV-Peephole-optimisation-for-load-store-of-global.patch
0049-RISCV-Add-codegen-for-RV32F-arithmetic-and-conversio.patch
0050-RISCV-Add-codegen-for-RV32F-floating-point-load-stor.patch
0051-RISCV-Codegen-support-for-FPR32-stack-loads-stores.patch
0052-RISCV-Codegen-support-for-floating-point-comparison-.patch
0053-RISCV-WIP-Codegen-support-for-RV32F-fused-multiply-a.patch
0054-RISCV-Add-minimum-necessary-for-RV32D-codegen-for-fa.patch
0055-RISCV-Add-codegen-support-for-RV32D-floating-point-a.patch
0056-RISCV-Codegen-support-for-RV32D-floating-point-conve.patch
0057-RISCV-Codegen-support-for-RV32D-floating-point-compa.patch
0058-RISCV-Codegen-support-for-RV32D-floating-point-load-.patch
0059-RISCV-Add-xfailed-test-case-for-type-legalisation-fa.patch
0060-Add-xfailed-RV32D-test-case-failing-with-multiple-vr.patch
0061-RISCV-MC-layer-support-for-load-store-instructions-o.patch
0062-RISCV-MC-layer-support-for-the-jump-branch-instructi.patch
0063-RISCV-MC-layer-support-for-the-remaining-RVC-instruc.patch
0064-RISCV-MC-layer-support-for-the-instructions-added-in.patch
0065-RISCV-Implement-assembler-pseudo-instructions-for-RV.patch
0066-RISCV-Implement-RISCVRegisterInfo-enableMultipleCopy.patch
0067-RISCV-Enable-emission-of-aliased-instructions-by-def.patch
0068-RISCV-Pass-MCSubtargetInfo-to-print-methods.patch
0069-RISCV-Codegen-for-atomic-fences-loads-and-stores.patch
0070-RISCV-Lowering-for-AMO-operations.patch
0071-RISCV-Expose-options-to-enable-optimisation-of-compl.patch
0072-RISCV-Implement-isLegalAddressingMode-for-RISC-V.patch
0073-RISCV-Implement-isLegalAddImmediate.patch
0074-RISCV-Implement-isLegalICmpImmediate.patch
0075-RISCV-Implement-isTruncateFree.patch
0076-RISCV-Implement-isZExtFree.patch
0077-RISCV-Implement-computeKnownBitsForTargetNode-for-RI.patch
0078-RISCV-Implement-isLoadFromStackSlot-and-isStoreToSta.patch
0079-RISCV-Allow-RISCVAsmBackend-writeNopData-to-generate.patch
0080-RISCV-Encode-RISCV-specific-ELF-e_flags-to-RISCV-Bin.patch
0081-RISCV-Define-getSetCCResultType-for-setting-vector-s.patch
0082-RISCV-Add-support-for-pcrel_lo.patch
0083-RISCV-Add-ELFObjectFileBase-getRISCVFeatures-let-llv.patch
0084-RISCV-Implement-MC-relaxations-for-compressed-instru.patch
0085-RISCV-Set-AllowRegisterRenaming-1.patch
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