[RISCV] Handle undef passthrus in foldVMV_V_V

If a PseudoVMV_V_V's passthru is undef then we don't need the Src to have the same passthru, nor do we need to check its VL.

The tail policy in these tests is still tu, llvm#105788 should fix this separately.

Author: lukel97

llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp

@@ -503,30 +503,32 @@ bool RISCVVectorPeephole::foldVMV_V_V(MachineInstr &MI) {
   if (getSEWLMULRatio(MI) != getSEWLMULRatio(*Src))
     return false;
 
-  // Src needs to have the same passthru as VMV_V_V
-  MachineOperand &SrcPassthru = Src->getOperand(1);
-  if (SrcPassthru.getReg() != RISCV::NoRegister &&
-      SrcPassthru.getReg() != Passthru.getReg())
-    return false;
+  if (Passthru.getReg() != RISCV::NoRegister) {
+    // Src needs to have the same passthru as VMV_V_V
+    MachineOperand &SrcPassthru = Src->getOperand(1);
+    if (SrcPassthru.getReg() != RISCV::NoRegister &&
+	SrcPassthru.getReg() != Passthru.getReg())
+      return false;
 
-  // Src VL will have already been reduced if legal (see tryToReduceVL),
-  // so we don't need to handle a smaller source VL here.  However, the
-  // user's VL may be larger
-  MachineOperand &SrcVL = Src->getOperand(RISCVII::getVLOpNum(Src->getDesc()));
-  if (!isVLKnownLE(SrcVL, MI.getOperand(3)))
-    return false;
+    // Src VL will have already been reduced if legal (see tryToReduceVL),
+    // so we don't need to handle a smaller source VL here.  However, the
+    // user's VL may be larger
+    MachineOperand &SrcVL = Src->getOperand(RISCVII::getVLOpNum(Src->getDesc()));
+    if (!isVLKnownLE(SrcVL, MI.getOperand(3)))
+      return false;
 
-  // If the new passthru doesn't dominate Src, try to move Src so it does.
-  if (!ensureDominates(Passthru, *Src))
-    return false;
+    // If the new passthru doesn't dominate Src, try to move Src so it does.
+    if (!ensureDominates(Passthru, *Src))
+      return false;
 
-  if (SrcPassthru.getReg() != Passthru.getReg()) {
-    SrcPassthru.setReg(Passthru.getReg());
-    // If Src is masked then its passthru needs to be in VRNoV0.
-    if (Passthru.getReg() != RISCV::NoRegister)
-      MRI->constrainRegClass(Passthru.getReg(),
-                             TII->getRegClass(Src->getDesc(), 1, TRI,
-                                              *Src->getParent()->getParent()));
+    if (SrcPassthru.getReg() != Passthru.getReg()) {
+      SrcPassthru.setReg(Passthru.getReg());
+      // If Src is masked then its passthru needs to be in VRNoV0.
+      if (Passthru.getReg() != RISCV::NoRegister)
+	MRI->constrainRegClass(Passthru.getReg(),
+                               TII->getRegClass(Src->getDesc(), 1, TRI,
+						*Src->getParent()->getParent()));
+    }
   }
 
   // Use a conservative tu,mu policy, RISCVInsertVSETVLI will relax it if

llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.ll

@@ -200,8 +200,6 @@ define <vscale x 1 x i64> @undef_passthru(<vscale x 1 x i64> %passthru, <vscale
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vsetvli zero, a0, e64, m1, tu, ma
 ; CHECK-NEXT:    vadd.vv v8, v9, v10
-; CHECK-NEXT:    vsetvli zero, zero, e64, m1, ta, ma
-; CHECK-NEXT:    vmv.v.v v8, v8
 ; CHECK-NEXT:    ret
   %a = call <vscale x 1 x i64> @llvm.riscv.vadd.nxv1i64.nxv1i64(<vscale x 1 x i64> %passthru, <vscale x 1 x i64> %x, <vscale x 1 x i64> %y, iXLen %avl)
   %b = call <vscale x 1 x i64> @llvm.riscv.vmv.v.v.nxv1i64(<vscale x 1 x i64> undef, <vscale x 1 x i64> %a, iXLen %avl)

llvm/test/CodeGen/RISCV/rvv/vmv.v.v-peephole.mir

@@ -28,7 +28,6 @@ body: |
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: %passthru:vr = COPY $v8
     ; CHECK-NEXT: %x:vr = PseudoVADD_VV_M1 %passthru, $noreg, $noreg, 4, 5 /* e32 */, 0 /* tu, mu */
-    ; CHECK-NEXT: %y:vr = PseudoVMV_V_V_M1 $noreg, %x, 4, 5 /* e32 */, 1 /* ta, mu */
     %passthru:vr = COPY $v8
     %x:vr = PseudoVADD_VV_M1 %passthru, $noreg, $noreg, 4, 5 /* e32 */, 0 /* tu, mu */
     %y:vr = PseudoVMV_V_V_M1 $noreg, %x, 4, 5 /* e32 */, 1 /* ta, mu */