-
Notifications
You must be signed in to change notification settings - Fork 191
/
rtw8814a.c
2224 lines (1835 loc) · 62.9 KB
/
rtw8814a.c
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
/* Copyright(c) 2025 Realtek Corporation
*/
#include <linux/usb.h>
#include "main.h"
#include "coex.h"
#include "tx.h"
#include "phy.h"
#include "rtw8814a.h"
#include "rtw8814a_table.h"
#include "rtw88xxa.h"
#include "reg.h"
#include "debug.h"
#include "efuse.h"
#include "regd.h"
#include "usb.h"
static void rtw8814a_efuse_grant(struct rtw_dev *rtwdev, bool on)
{
if (on) {
rtw_write8(rtwdev, REG_EFUSE_ACCESS, EFUSE_ACCESS_ON);
rtw_write16_set(rtwdev, REG_SYS_FUNC_EN, BIT_FEN_ELDR);
rtw_write16_set(rtwdev, REG_SYS_CLKR,
BIT_LOADER_CLK_EN | BIT_ANA8M);
} else {
rtw_write8(rtwdev, REG_EFUSE_ACCESS, EFUSE_ACCESS_OFF);
}
}
static void rtw8814a_read_rfe_type(struct rtw_dev *rtwdev)
{
struct rtw_efuse *efuse = &rtwdev->efuse;
if (!(efuse->rfe_option & BIT(7)))
return;
if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_PCIE)
efuse->rfe_option = 0;
else if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_USB)
efuse->rfe_option = 1;
}
static void rtw8814a_read_amplifier_type(struct rtw_dev *rtwdev)
{
struct rtw_efuse *efuse = &rtwdev->efuse;
switch (efuse->rfe_option) {
case 1:
/* Internal 2G */
efuse->pa_type_2g = 0;
efuse->lna_type_2g = 0;
/* External 5G */
efuse->pa_type_5g = BIT(0);
efuse->lna_type_5g = BIT(3);
break;
case 2 ... 5:
/* External everything */
efuse->pa_type_2g = BIT(4);
efuse->lna_type_2g = BIT(3);
efuse->pa_type_5g = BIT(0);
efuse->lna_type_5g = BIT(3);
break;
case 6:
efuse->lna_type_5g = BIT(3);
break;
default:
break;
}
}
static void rtw8814a_read_rf_type(struct rtw_dev *rtwdev,
struct rtw8814a_efuse *map)
{
struct rtw_usb *rtwusb = rtw_get_usb_priv(rtwdev);
struct rtw_hal *hal = &rtwdev->hal;
switch (map->trx_antenna_option) {
case 0xff: /* 4T4R */
case 0xee: /* 3T3R */
if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_USB &&
rtwusb->udev->speed != USB_SPEED_SUPER)
hal->rf_type = RF_2T2R;
else
hal->rf_type = RF_3T3R;
break;
case 0x66: /* 2T2R */
case 0x6f: /* 2T4R */
default:
hal->rf_type = RF_2T2R;
break;
}
hal->rf_path_num = 4;
hal->rf_phy_num = 4;
if (hal->rf_type == RF_3T3R) {
hal->antenna_rx = BB_PATH_ABC;
hal->antenna_tx = BB_PATH_ABC;
} else {
hal->antenna_rx = BB_PATH_AB;
hal->antenna_tx = BB_PATH_AB;
}
}
static void rtw8814a_init_hwcap(struct rtw_dev *rtwdev)
{
struct rtw_efuse *efuse = &rtwdev->efuse;
struct rtw_hal *hal = &rtwdev->hal;
efuse->hw_cap.bw = BIT(RTW_CHANNEL_WIDTH_20) |
BIT(RTW_CHANNEL_WIDTH_40) |
BIT(RTW_CHANNEL_WIDTH_80);
efuse->hw_cap.ptcl = EFUSE_HW_CAP_PTCL_VHT;
if (hal->rf_type == RF_3T3R)
efuse->hw_cap.nss = 3;
else
efuse->hw_cap.nss = 2;
rtw_dbg(rtwdev, RTW_DBG_EFUSE,
"hw cap: hci=0x%02x, bw=0x%02x, ptcl=0x%02x, ant_num=%d, nss=%d\n",
efuse->hw_cap.hci, efuse->hw_cap.bw, efuse->hw_cap.ptcl,
efuse->hw_cap.ant_num, efuse->hw_cap.nss);
}
static int rtw8814a_read_efuse(struct rtw_dev *rtwdev, u8 *log_map)
{
struct rtw_efuse *efuse = &rtwdev->efuse;
struct rtw8814a_efuse *map;
int i;
if (rtw_dbg_is_enabled(rtwdev, RTW_DBG_EFUSE))
print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET, 16, 1,
log_map, rtwdev->chip->log_efuse_size, true);
map = (struct rtw8814a_efuse *)log_map;
efuse->usb_mode_switch = u8_get_bits(map->usb_mode, BIT(4));
efuse->rfe_option = map->rfe_option;
efuse->rf_board_option = map->rf_board_option;
efuse->crystal_cap = map->xtal_k;
efuse->channel_plan = map->channel_plan;
efuse->country_code[0] = map->country_code[0];
efuse->country_code[1] = map->country_code[1];
efuse->bt_setting = map->rf_bt_setting;
efuse->regd = map->rf_board_option & 0x7;
efuse->thermal_meter[RF_PATH_A] = map->thermal_meter;
efuse->thermal_meter_k = map->thermal_meter;
efuse->tx_bb_swing_setting_2g = map->tx_bb_swing_setting_2g;
efuse->tx_bb_swing_setting_5g = map->tx_bb_swing_setting_5g;
rtw8814a_read_rfe_type(rtwdev);
rtw8814a_read_amplifier_type(rtwdev);
/* Override rtw_chip_parameter_setup() */
rtw8814a_read_rf_type(rtwdev, map);
rtw8814a_init_hwcap(rtwdev);
for (i = 0; i < 4; i++)
efuse->txpwr_idx_table[i] = map->txpwr_idx_table[i];
switch (rtw_hci_type(rtwdev)) {
case RTW_HCI_TYPE_USB:
ether_addr_copy(efuse->addr, map->u.mac_addr);
break;
case RTW_HCI_TYPE_PCIE:
case RTW_HCI_TYPE_SDIO:
default:
/* unsupported now */
return -EOPNOTSUPP;
}
return 0;
}
static void rtw8814a_init_rfe_reg(struct rtw_dev *rtwdev)
{
u8 rfe_option = rtwdev->efuse.rfe_option;
if (rfe_option == 2 || rfe_option == 1) {
rtw_write32_mask(rtwdev, 0x1994, 0xf, 0xf);
rtw_write8_set(rtwdev, REG_GPIO_MUXCFG + 2, 0xf0);
} else if (rfe_option == 0) {
rtw_write32_mask(rtwdev, 0x1994, 0xf, 0xf);
rtw_write8_set(rtwdev, REG_GPIO_MUXCFG + 2, 0xc0);
}
}
#define RTW_TXSCALE_SIZE 37
static const u32 rtw8814a_txscale_tbl[RTW_TXSCALE_SIZE] = {
0x081, 0x088, 0x090, 0x099, 0x0a2, 0x0ac, 0x0b6, 0x0c0, 0x0cc, 0x0d8,
0x0e5, 0x0f2, 0x101, 0x110, 0x120, 0x131, 0x143, 0x156, 0x16a, 0x180,
0x197, 0x1af, 0x1c8, 0x1e3, 0x200, 0x21e, 0x23e, 0x261, 0x285, 0x2ab,
0x2d3, 0x2fe, 0x32b, 0x35c, 0x38e, 0x3c4, 0x3fe
};
static u32 rtw8814a_get_bb_swing(struct rtw_dev *rtwdev, u8 band, u8 rf_path)
{
static const u32 swing2setting[4] = {0x200, 0x16a, 0x101, 0x0b6};
struct rtw_efuse *efuse = &rtwdev->efuse;
u8 tx_bb_swing;
if (band == RTW_BAND_2G)
tx_bb_swing = efuse->tx_bb_swing_setting_2g;
else
tx_bb_swing = efuse->tx_bb_swing_setting_5g;
tx_bb_swing >>= 2 * rf_path;
tx_bb_swing &= 0x3;
return swing2setting[tx_bb_swing];
}
static u8 rtw8814a_get_swing_index(struct rtw_dev *rtwdev)
{
u32 swing, table_value;
u8 i;
swing = rtw8814a_get_bb_swing(rtwdev, rtwdev->hal.current_band_type,
RF_PATH_A);
for (i = 0; i < ARRAY_SIZE(rtw8814a_txscale_tbl); i++) {
table_value = rtw8814a_txscale_tbl[i];
if (swing == table_value)
return i;
}
return 24;
}
static void rtw8814a_pwrtrack_init(struct rtw_dev *rtwdev)
{
struct rtw_dm_info *dm_info = &rtwdev->dm_info;
u8 path;
dm_info->default_ofdm_index = rtw8814a_get_swing_index(rtwdev);
for (path = RF_PATH_A; path < rtwdev->hal.rf_path_num; path++) {
ewma_thermal_init(&dm_info->avg_thermal[path]);
dm_info->delta_power_index[path] = 0;
dm_info->delta_power_index_last[path] = 0;
}
dm_info->pwr_trk_triggered = false;
dm_info->pwr_trk_init_trigger = true;
dm_info->thermal_meter_k = rtwdev->efuse.thermal_meter_k;
}
static void rtw8814a_config_trx_path(struct rtw_dev *rtwdev)
{
/* RX CCK disable 2R CCA */
rtw_write32_clr(rtwdev, REG_CCK0_FAREPORT,
BIT_CCK0_2RX | BIT_CCK0_MRC);
/* pathB tx on, path A/C/D tx off */
rtw_write32_mask(rtwdev, REG_CCK_RX, 0xf0000000, 0x4);
/* pathB rx */
rtw_write32_mask(rtwdev, REG_CCK_RX, 0x0f000000, 0x5);
}
static void rtw8814a_config_cck_rx_antenna_init(struct rtw_dev *rtwdev)
{
/* CCK 2R CCA parameters */
/* Disable Ant diversity */
rtw_write32_mask(rtwdev, REG_RXSB, BIT(15), 0x0);
/* Concurrent CCA at LSB & USB */
rtw_write32_mask(rtwdev, 0xa70, BIT(7), 0);
/* RX path diversity enable */
rtw_write32_mask(rtwdev, 0xa74, BIT(8), 0);
/* r_en_mrc_antsel */
rtw_write32_mask(rtwdev, 0xa14, BIT(7), 0);
/* MBC weighting */
rtw_write32_mask(rtwdev, 0xa20, BIT(5) | BIT(4), 1);
/* 2R CCA only */
rtw_write32_mask(rtwdev, 0xa84, BIT(28), 1);
}
static void rtw8814a_phy_set_param(struct rtw_dev *rtwdev)
{
u32 crystal_cap, val32;
u8 val8, rf_path;
/* power on BB/RF domain */
if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_USB)
rtw_write8_set(rtwdev, REG_SYS_FUNC_EN, BIT_FEN_USBA);
else if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_PCIE)
rtw_write8_set(rtwdev, REG_SYS_FUNC_EN, BIT_FEN_PCIEA);
rtw_write8_set(rtwdev, REG_SYS_CFG3_8814A + 2,
BIT_FEN_BB_GLB_RST | BIT_FEN_BB_RSTB);
/* Power on RF paths A..D */
val8 = BIT_RF_EN | BIT_RF_RSTB | BIT_RF_SDM_RSTB;
rtw_write8(rtwdev, REG_RF_CTRL, val8);
rtw_write8(rtwdev, REG_RF_CTRL1, val8);
rtw_write8(rtwdev, REG_RF_CTRL2, val8);
rtw_write8(rtwdev, REG_RF_CTRL3, val8);
rtw_load_table(rtwdev, rtwdev->chip->bb_tbl);
rtw_load_table(rtwdev, rtwdev->chip->agc_tbl);
crystal_cap = rtwdev->efuse.crystal_cap & 0x3F;
crystal_cap |= crystal_cap << 6;
rtw_write32_mask(rtwdev, REG_AFE_CTRL3, 0x07ff8000, crystal_cap);
rtw8814a_config_trx_path(rtwdev);
for (rf_path = 0; rf_path < rtwdev->hal.rf_path_num; rf_path++)
rtw_load_table(rtwdev, rtwdev->chip->rf_tbl[rf_path]);
val32 = rtw_read_rf(rtwdev, RF_PATH_A, RF_RCK1, RFREG_MASK);
rtw_write_rf(rtwdev, RF_PATH_B, RF_RCK1, RFREG_MASK, val32);
rtw_write_rf(rtwdev, RF_PATH_C, RF_RCK1, RFREG_MASK, val32);
rtw_write_rf(rtwdev, RF_PATH_D, RF_RCK1, RFREG_MASK, val32);
rtw_write32_set(rtwdev, REG_RXPSEL, BIT_RX_PSEL_RST);
rtw_write8(rtwdev, REG_HWSEQ_CTRL, 0xFF);
rtw_write32(rtwdev, REG_BAR_MODE_CTRL, 0x0201ffff);
rtw_write8(rtwdev, REG_MISC_CTRL, BIT_DIS_SECOND_CCA);
rtw_write8(rtwdev, REG_NAV_CTRL + 2, 0);
rtw_write8_clr(rtwdev, REG_GPIO_MUXCFG, BIT(5));
rtw8814a_config_cck_rx_antenna_init(rtwdev);
rtw_phy_init(rtwdev);
rtw8814a_pwrtrack_init(rtwdev);
rtw8814a_init_rfe_reg(rtwdev);
rtw_write8_clr(rtwdev, REG_QUEUE_CTRL, BIT(3));
rtw_write8(rtwdev, REG_NAV_CTRL + 2, 235);
/* enable Tx report. */
rtw_write8(rtwdev, REG_FWHW_TXQ_CTRL + 1, 0x0F);
if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_USB) {
/* Reset USB mode switch setting */
rtw_write8(rtwdev, REG_SYS_SDIO_CTRL, 0x0);
rtw_write8(rtwdev, REG_ACLK_MON, 0x0);
}
}
static int rtw8814a_mac_init(struct rtw_dev *rtwdev)
{
struct rtw_usb *rtwusb = rtw_get_usb_priv(rtwdev);
rtw_write16(rtwdev, REG_CR,
MAC_TRX_ENABLE | BIT_MAC_SEC_EN | BIT_32K_CAL_TMR_EN);
rtw_load_table(rtwdev, rtwdev->chip->mac_tbl);
rtw_write8(rtwdev, REG_AUTO_LLT_V1 + 3,
rtwdev->chip->usb_tx_agg_desc_num << 1);
rtw_write32(rtwdev, REG_HIMR0, 0);
rtw_write32(rtwdev, REG_HIMR1, 0);
rtw_write32_mask(rtwdev, REG_RRSR, 0xfffff, 0xfffff);
rtw_write16(rtwdev, REG_RETRY_LIMIT, 0x3030);
rtw_write16(rtwdev, REG_RXFLTMAP0, 0xffff);
rtw_write16(rtwdev, REG_RXFLTMAP1, 0x0400);
rtw_write16(rtwdev, REG_RXFLTMAP2, 0xffff);
rtw_write8(rtwdev, REG_MAX_AGGR_NUM, 0x36);
rtw_write8(rtwdev, REG_MAX_AGGR_NUM + 1, 0x36);
/* Set Spec SIFS (used in NAV) */
rtw_write16(rtwdev, REG_SPEC_SIFS, 0x100a);
rtw_write16(rtwdev, REG_MAC_SPEC_SIFS, 0x100a);
/* Set SIFS for CCK */
rtw_write16(rtwdev, REG_SIFS, 0x100a);
/* Set SIFS for OFDM */
rtw_write16(rtwdev, REG_SIFS + 2, 0x100a);
/* TXOP */
rtw_write32(rtwdev, REG_EDCA_BE_PARAM, 0x005EA42B);
rtw_write32(rtwdev, REG_EDCA_BK_PARAM, 0x0000A44F);
rtw_write32(rtwdev, REG_EDCA_VI_PARAM, 0x005EA324);
rtw_write32(rtwdev, REG_EDCA_VO_PARAM, 0x002FA226);
rtw_write8_set(rtwdev, REG_FWHW_TXQ_CTRL, BIT(7));
rtw_write8(rtwdev, REG_ACKTO, 0x80);
rtw_write16(rtwdev, REG_BCN_CTRL,
BIT_DIS_TSF_UDT | (BIT_DIS_TSF_UDT << 8));
rtw_write32_mask(rtwdev, REG_TBTT_PROHIBIT, 0xfffff, WLAN_TBTT_TIME);
rtw_write8(rtwdev, REG_DRVERLYINT, 0x05);
rtw_write8(rtwdev, REG_BCNDMATIM, WLAN_BCN_DMA_TIME);
rtw_write16(rtwdev, REG_BCNTCFG, 0x4413);
rtw_write8(rtwdev, REG_BCN_MAX_ERR, 0xFF);
rtw_write32(rtwdev, REG_FAST_EDCA_VOVI_SETTING, 0x08070807);
rtw_write32(rtwdev, REG_FAST_EDCA_BEBK_SETTING, 0x08070807);
if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_USB &&
rtwusb->udev->speed == USB_SPEED_SUPER) {
/* Disable U1/U2 Mode to avoid 2.5G spur in USB3.0. */
rtw_write8_clr(rtwdev, REG_USB_MOD, BIT(4) | BIT(3));
/* To avoid usb 3.0 H2C fail. */
rtw_write16(rtwdev, 0xf002, 0);
rtw_write8_clr(rtwdev, REG_SW_AMPDU_BURST_MODE_CTRL,
BIT_PRE_TX_CMD);
}
return 0;
}
static void rtw8814a_set_rfe_reg_24g(struct rtw_dev *rtwdev)
{
switch (rtwdev->efuse.rfe_option) {
case 2:
rtw_write32(rtwdev, REG_RFE_PINMUX_A, 0x72707270);
rtw_write32(rtwdev, REG_RFE_PINMUX_B, 0x72707270);
rtw_write32(rtwdev, REG_RFE_PINMUX_C, 0x72707270);
rtw_write32(rtwdev, REG_RFE_PINMUX_D, 0x77707770);
rtw_write32_mask(rtwdev, 0x1ABC, 0x0ff00000, 0x72);
break;
case 1:
rtw_write32(rtwdev, REG_RFE_PINMUX_A, 0x77777777);
rtw_write32(rtwdev, REG_RFE_PINMUX_B, 0x77777777);
rtw_write32(rtwdev, REG_RFE_PINMUX_C, 0x77777777);
rtw_write32(rtwdev, REG_RFE_PINMUX_D, 0x77777777);
rtw_write32_mask(rtwdev, 0x1ABC, 0x0ff00000, 0x77);
break;
case 0:
default:
rtw_write32(rtwdev, REG_RFE_PINMUX_A, 0x77777777);
rtw_write32(rtwdev, REG_RFE_PINMUX_B, 0x77777777);
rtw_write32(rtwdev, REG_RFE_PINMUX_C, 0x77777777);
/* Is it not necessary to set REG_RFE_PINMUX_D ? */
rtw_write32_mask(rtwdev, 0x1ABC, 0x0ff00000, 0x77);
break;
}
}
static void rtw8814a_set_rfe_reg_5g(struct rtw_dev *rtwdev)
{
switch (rtwdev->efuse.rfe_option) {
case 2:
rtw_write32(rtwdev, REG_RFE_PINMUX_A, 0x37173717);
rtw_write32(rtwdev, REG_RFE_PINMUX_B, 0x37173717);
rtw_write32(rtwdev, REG_RFE_PINMUX_C, 0x37173717);
rtw_write32(rtwdev, REG_RFE_PINMUX_D, 0x77177717);
rtw_write32_mask(rtwdev, 0x1ABC, 0x0ff00000, 0x37);
break;
case 1:
rtw_write32(rtwdev, REG_RFE_PINMUX_A, 0x33173317);
rtw_write32(rtwdev, REG_RFE_PINMUX_B, 0x33173317);
rtw_write32(rtwdev, REG_RFE_PINMUX_C, 0x33173317);
rtw_write32(rtwdev, REG_RFE_PINMUX_D, 0x77177717);
rtw_write32_mask(rtwdev, 0x1ABC, 0x0ff00000, 0x33);
break;
case 0:
default:
rtw_write32(rtwdev, REG_RFE_PINMUX_A, 0x54775477);
rtw_write32(rtwdev, REG_RFE_PINMUX_B, 0x54775477);
rtw_write32(rtwdev, REG_RFE_PINMUX_C, 0x54775477);
rtw_write32(rtwdev, REG_RFE_PINMUX_D, 0x54775477);
rtw_write32_mask(rtwdev, 0x1ABC, 0x0ff00000, 0x54);
break;
}
}
static void rtw8814a_set_channel_bb_swing(struct rtw_dev *rtwdev, u8 band)
{
rtw_write32_mask(rtwdev, REG_TXSCALE_A, BB_SWING_MASK,
rtw8814a_get_bb_swing(rtwdev, band, RF_PATH_A));
rtw_write32_mask(rtwdev, REG_TXSCALE_B, BB_SWING_MASK,
rtw8814a_get_bb_swing(rtwdev, band, RF_PATH_B));
rtw_write32_mask(rtwdev, REG_TXSCALE_C, BB_SWING_MASK,
rtw8814a_get_bb_swing(rtwdev, band, RF_PATH_C));
rtw_write32_mask(rtwdev, REG_TXSCALE_D, BB_SWING_MASK,
rtw8814a_get_bb_swing(rtwdev, band, RF_PATH_D));
rtw8814a_pwrtrack_init(rtwdev);
}
static void rtw8814a_set_bw_reg_adc(struct rtw_dev *rtwdev, u8 bw)
{
u32 adc = 0;
if (bw == RTW_CHANNEL_WIDTH_20)
adc = 0;
else if (bw == RTW_CHANNEL_WIDTH_40)
adc = 1;
else if (bw == RTW_CHANNEL_WIDTH_80)
adc = 2;
rtw_write32_mask(rtwdev, REG_ADCCLK, BIT(1) | BIT(0), adc);
}
static void rtw8814a_set_bw_reg_agc(struct rtw_dev *rtwdev, u8 new_band, u8 bw)
{
u32 agc = 7;
if (bw == RTW_CHANNEL_WIDTH_20) {
agc = 6;
} else if (bw == RTW_CHANNEL_WIDTH_40) {
if (new_band == RTW_BAND_5G)
agc = 8;
else
agc = 7;
} else if (bw == RTW_CHANNEL_WIDTH_80) {
agc = 3;
}
rtw_write32_mask(rtwdev, REG_CCASEL, 0xf000, agc);
}
static void rtw8814a_switch_band(struct rtw_dev *rtwdev, u8 new_band, u8 bw)
{
/* Clear 0x1000[16], When this bit is set to 0, CCK and OFDM
* are disabled, and clock are gated. Otherwise, CCK and OFDM
* are enabled.
*/
rtw_write8_clr(rtwdev, REG_SYS_CFG3_8814A + 2, BIT_FEN_BB_RSTB);
if (new_band == RTW_BAND_2G) {
rtw_write32_mask(rtwdev, REG_AGC_TABLE, 0x1f, 0);
rtw8814a_set_rfe_reg_24g(rtwdev);
rtw_write32_mask(rtwdev, REG_TXPSEL, 0xf0, 0x2);
rtw_write32_mask(rtwdev, REG_CCK_RX, 0x0f000000, 0x5);
rtw_write32_mask(rtwdev, REG_RXPSEL, BIT_RX_PSEL_RST, 0x3);
rtw_write8(rtwdev, REG_CCK_CHECK, 0);
rtw_write32_mask(rtwdev, 0xa80, BIT(18), 0);
} else {
rtw_write8(rtwdev, REG_CCK_CHECK, BIT_CHECK_CCK_EN);
/* Enable CCK Tx function, even when CCK is off */
rtw_write32_mask(rtwdev, 0xa80, BIT(18), 1);
rtw8814a_set_rfe_reg_5g(rtwdev);
rtw_write32_mask(rtwdev, REG_TXPSEL, 0xf0, 0x0);
rtw_write32_mask(rtwdev, REG_CCK_RX, 0x0f000000, 0xf);
rtw_write32_mask(rtwdev, REG_RXPSEL, BIT_RX_PSEL_RST, 0x2);
}
rtw8814a_set_channel_bb_swing(rtwdev, new_band);
rtw8814a_set_bw_reg_adc(rtwdev, bw);
rtw8814a_set_bw_reg_agc(rtwdev, new_band, bw);
rtw_write8_set(rtwdev, REG_SYS_CFG3_8814A + 2, BIT_FEN_BB_RSTB);
}
static void rtw8814a_switch_channel(struct rtw_dev *rtwdev, u8 channel)
{
struct rtw_hal *hal = &rtwdev->hal;
u32 fc_area, rf_mod_ag, cfgch;
u8 path;
switch (channel) {
case 36 ... 48:
fc_area = 0x494;
break;
case 50 ... 64:
fc_area = 0x453;
break;
case 100 ... 116:
fc_area = 0x452;
break;
default:
if (channel >= 118)
fc_area = 0x412;
else
fc_area = 0x96a;
break;
}
rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, fc_area);
for (path = 0; path < hal->rf_path_num; path++) {
switch (channel) {
case 36 ... 64:
rf_mod_ag = 0x101;
break;
case 100 ... 140:
rf_mod_ag = 0x301;
break;
default:
if (channel > 140)
rf_mod_ag = 0x501;
else
rf_mod_ag = 0x000;
break;
}
cfgch = (rf_mod_ag << 8) | channel;
rtw_write_rf(rtwdev, path, RF_CFGCH,
RF18_RFSI_MASK | RF18_BAND_MASK | RF18_CHANNEL_MASK, cfgch);
}
switch (channel) {
case 36 ... 64:
rtw_write32_mask(rtwdev, REG_AGC_TABLE, 0x1f, 1);
break;
case 100 ... 144:
rtw_write32_mask(rtwdev, REG_AGC_TABLE, 0x1f, 2);
break;
default:
if (channel >= 149)
rtw_write32_mask(rtwdev, REG_AGC_TABLE, 0x1f, 3);
break;
}
}
static void rtw8814a_24g_cck_tx_dfir(struct rtw_dev *rtwdev, u8 channel)
{
if (channel >= 1 && channel <= 11) {
rtw_write32(rtwdev, REG_CCK0_TX_FILTER1, 0x1a1b0030);
rtw_write32(rtwdev, REG_CCK0_TX_FILTER2, 0x090e1317);
rtw_write32(rtwdev, REG_CCK0_DEBUG_PORT, 0x00000204);
} else if (channel >= 12 && channel <= 13) {
rtw_write32(rtwdev, REG_CCK0_TX_FILTER1, 0x1a1b0030);
rtw_write32(rtwdev, REG_CCK0_TX_FILTER2, 0x090e1217);
rtw_write32(rtwdev, REG_CCK0_DEBUG_PORT, 0x00000305);
} else if (channel == 14) {
rtw_write32(rtwdev, REG_CCK0_TX_FILTER1, 0x1a1b0030);
rtw_write32(rtwdev, REG_CCK0_TX_FILTER2, 0x00000E17);
rtw_write32(rtwdev, REG_CCK0_DEBUG_PORT, 0x00000000);
}
}
static void rtw8814a_set_bw_reg_mac(struct rtw_dev *rtwdev, u8 bw)
{
u16 val16 = rtw_read16(rtwdev, REG_WMAC_TRXPTCL_CTL);
val16 &= ~BIT_RFMOD;
if (bw == RTW_CHANNEL_WIDTH_80)
val16 |= BIT_RFMOD_80M;
else if (bw == RTW_CHANNEL_WIDTH_40)
val16 |= BIT_RFMOD_40M;
rtw_write16(rtwdev, REG_WMAC_TRXPTCL_CTL, val16);
}
static void rtw8814a_set_bw_rf(struct rtw_dev *rtwdev, u8 bw)
{
u8 path;
for (path = RF_PATH_A; path < rtwdev->hal.rf_path_num; path++) {
switch (bw) {
case RTW_CHANNEL_WIDTH_5:
case RTW_CHANNEL_WIDTH_10:
case RTW_CHANNEL_WIDTH_20:
default:
rtw_write_rf(rtwdev, path, RF_CFGCH, RF18_BW_MASK, 3);
break;
case RTW_CHANNEL_WIDTH_40:
rtw_write_rf(rtwdev, path, RF_CFGCH, RF18_BW_MASK, 1);
break;
case RTW_CHANNEL_WIDTH_80:
rtw_write_rf(rtwdev, path, RF_CFGCH, RF18_BW_MASK, 0);
break;
}
}
}
static void rtw8814a_adc_clk(struct rtw_dev *rtwdev)
{
static const u32 rxiqc_reg[2][4] = {
{ REG_RX_IQC_AB_A, REG_RX_IQC_AB_B,
REG_RX_IQC_AB_C, REG_RX_IQC_AB_D },
{ REG_RX_IQC_CD_A, REG_RX_IQC_CD_B,
REG_RX_IQC_CD_C, REG_RX_IQC_CD_D }
};
u32 bb_reg_8fc, bb_reg_808, rxiqc[4];
u32 i = 0, mac_active = 1;
u8 mac_reg_522;
if (rtwdev->hal.cut_version != RTW_CHIP_VER_CUT_A)
return;
/* 1 Step1. MAC TX pause */
mac_reg_522 = rtw_read8(rtwdev, REG_TXPAUSE);
bb_reg_8fc = rtw_read32(rtwdev, 0x8fc);
bb_reg_808 = rtw_read32(rtwdev, REG_RXPSEL);
rtw_write8(rtwdev, REG_TXPAUSE, 0x3f);
/* 1 Step 2. Backup rxiqc & rxiqc = 0 */
for (i = 0; i < 4; i++) {
rxiqc[i] = rtw_read32(rtwdev, rxiqc_reg[0][i]);
rtw_write32(rtwdev, rxiqc_reg[0][i], 0x0);
rtw_write32(rtwdev, rxiqc_reg[1][i], 0x0);
}
rtw_write32_mask(rtwdev, 0xa14, 0x00000300, 0x3);
i = 0;
/* 1 Step 3. Monitor MAC IDLE */
rtw_write32(rtwdev, 0x8fc, 0x0);
while (mac_active) {
mac_active = rtw_read32(rtwdev, 0xfa0) & 0x803e0008;
i++;
if (i > 1000)
break;
}
/* 1 Step 4. ADC clk flow */
rtw_write8(rtwdev, REG_RXPSEL, 0x11);
rtw_write32_mask(rtwdev, REG_DAC_RSTB, BIT(13), 0x1);
rtw_write8_mask(rtwdev, REG_GNT_BT, BIT(2) | BIT(1), 0x3);
rtw_write32_mask(rtwdev, REG_CCK_RPT_FORMAT, BIT(2), 0x1);
/* 0xc1c/0xe1c/0x181c/0x1a1c[4] must=1 to ensure table can be
* written when bbrstb=0
* 0xc60/0xe60/0x1860/0x1a60[15] always = 1 after this line
* 0xc60/0xe60/0x1860/0x1a60[14] always = 0 bcz its error in A-cut
*/
/* power_off/clk_off @ anapar_state=idle mode */
rtw_write32(rtwdev, REG_AFE_PWR1_A, 0x15800002);
rtw_write32(rtwdev, REG_AFE_PWR1_A, 0x01808003);
rtw_write32(rtwdev, REG_AFE_PWR1_B, 0x15800002);
rtw_write32(rtwdev, REG_AFE_PWR1_B, 0x01808003);
rtw_write32(rtwdev, REG_AFE_PWR1_C, 0x15800002);
rtw_write32(rtwdev, REG_AFE_PWR1_C, 0x01808003);
rtw_write32(rtwdev, REG_AFE_PWR1_D, 0x15800002);
rtw_write32(rtwdev, REG_AFE_PWR1_D, 0x01808003);
rtw_write8_mask(rtwdev, REG_GNT_BT, BIT(2), 0x0);
rtw_write32_mask(rtwdev, REG_CCK_RPT_FORMAT, BIT(2), 0x0);
/* [19] = 1 to turn off ADC */
rtw_write32(rtwdev, REG_CK_MONHA, 0x0D080058);
rtw_write32(rtwdev, REG_CK_MONHB, 0x0D080058);
rtw_write32(rtwdev, REG_CK_MONHC, 0x0D080058);
rtw_write32(rtwdev, REG_CK_MONHD, 0x0D080058);
/* power_on/clk_off */
/* [19] = 0 to turn on ADC */
rtw_write32(rtwdev, REG_CK_MONHA, 0x0D000058);
rtw_write32(rtwdev, REG_CK_MONHB, 0x0D000058);
rtw_write32(rtwdev, REG_CK_MONHC, 0x0D000058);
rtw_write32(rtwdev, REG_CK_MONHD, 0x0D000058);
/* power_on/clk_on @ anapar_state=BT mode */
rtw_write32(rtwdev, REG_AFE_PWR1_A, 0x05808032);
rtw_write32(rtwdev, REG_AFE_PWR1_B, 0x05808032);
rtw_write32(rtwdev, REG_AFE_PWR1_C, 0x05808032);
rtw_write32(rtwdev, REG_AFE_PWR1_D, 0x05808032);
rtw_write8_mask(rtwdev, REG_GNT_BT, BIT(2), 0x1);
rtw_write32_mask(rtwdev, REG_CCK_RPT_FORMAT, BIT(2), 0x1);
/* recover original setting @ anapar_state=BT mode */
rtw_write32(rtwdev, REG_AFE_PWR1_A, 0x05808032);
rtw_write32(rtwdev, REG_AFE_PWR1_B, 0x05808032);
rtw_write32(rtwdev, REG_AFE_PWR1_C, 0x05808032);
rtw_write32(rtwdev, REG_AFE_PWR1_D, 0x05808032);
rtw_write32(rtwdev, REG_AFE_PWR1_A, 0x05800002);
rtw_write32(rtwdev, REG_AFE_PWR1_A, 0x07808003);
rtw_write32(rtwdev, REG_AFE_PWR1_B, 0x05800002);
rtw_write32(rtwdev, REG_AFE_PWR1_B, 0x07808003);
rtw_write32(rtwdev, REG_AFE_PWR1_C, 0x05800002);
rtw_write32(rtwdev, REG_AFE_PWR1_C, 0x07808003);
rtw_write32(rtwdev, REG_AFE_PWR1_D, 0x05800002);
rtw_write32(rtwdev, REG_AFE_PWR1_D, 0x07808003);
rtw_write8_mask(rtwdev, REG_GNT_BT, BIT(2) | BIT(1), 0x0);
rtw_write32_mask(rtwdev, REG_CCK_RPT_FORMAT, BIT(2), 0x0);
rtw_write32_mask(rtwdev, REG_DAC_RSTB, BIT(13), 0x0);
/* 1 Step 5. Recover MAC TX & IQC */
rtw_write8(rtwdev, REG_TXPAUSE, mac_reg_522);
rtw_write32(rtwdev, 0x8fc, bb_reg_8fc);
rtw_write32(rtwdev, REG_RXPSEL, bb_reg_808);
for (i = 0; i < 4; i++) {
rtw_write32(rtwdev, rxiqc_reg[0][i], rxiqc[i]);
rtw_write32(rtwdev, rxiqc_reg[1][i], 0x01000000);
}
rtw_write32_mask(rtwdev, 0xa14, 0x00000300, 0x0);
}
static void rtw8814a_spur_calibration_ch140(struct rtw_dev *rtwdev, u8 channel)
{
struct rtw_hal *hal = &rtwdev->hal;
/* Add for 8814AE module ch140 MP Rx */
if (channel == 140) {
if (hal->ch_param[0] == 0)
hal->ch_param[0] = rtw_read32(rtwdev, REG_CCASEL);
if (hal->ch_param[1] == 0)
hal->ch_param[1] = rtw_read32(rtwdev, REG_PDMFTH);
rtw_write32(rtwdev, REG_CCASEL, 0x75438170);
rtw_write32(rtwdev, REG_PDMFTH, 0x79a18a0a);
} else {
if (rtw_read32(rtwdev, REG_CCASEL) == 0x75438170 &&
hal->ch_param[0] != 0)
rtw_write32(rtwdev, REG_CCASEL, hal->ch_param[0]);
if (rtw_read32(rtwdev, REG_PDMFTH) == 0x79a18a0a &&
hal->ch_param[1] != 0)
rtw_write32(rtwdev, REG_PDMFTH, hal->ch_param[1]);
hal->ch_param[0] = rtw_read32(rtwdev, REG_CCASEL);
hal->ch_param[1] = rtw_read32(rtwdev, REG_PDMFTH);
}
}
static void rtw8814a_set_nbi_reg(struct rtw_dev *rtwdev, u32 tone_idx)
{
/* tone_idx X 10 */
static const u32 nbi_128[] = {
25, 55, 85, 115, 135,
155, 185, 205, 225, 245,
265, 285, 305, 335, 355,
375, 395, 415, 435, 455,
485, 505, 525, 555, 585, 615, 635
};
u32 reg_idx = 0;
u32 i;
for (i = 0; i < ARRAY_SIZE(nbi_128); i++) {
if (tone_idx < nbi_128[i]) {
reg_idx = i + 1;
break;
}
}
rtw_write32_mask(rtwdev, REG_NBI_SETTING, 0xfc000, reg_idx);
}
static void rtw8814a_nbi_setting(struct rtw_dev *rtwdev, u32 ch, u32 f_intf)
{
u32 fc, int_distance, tone_idx;
fc = 2412 + (ch - 1) * 5;
int_distance = abs_diff(fc, f_intf);
/* 10 * (int_distance / 0.3125) */
tone_idx = int_distance << 5;
rtw8814a_set_nbi_reg(rtwdev, tone_idx);
rtw_write32_mask(rtwdev, REG_NBI_SETTING, BIT_NBI_ENABLE, 1);
}
static void rtw8814a_spur_nbi_setting(struct rtw_dev *rtwdev)
{
u8 primary_channel = rtwdev->hal.primary_channel;
u8 rfe_type = rtwdev->efuse.rfe_option;
if (rfe_type != 0 && rfe_type != 1 && rfe_type != 6 && rfe_type != 7)
return;
if (primary_channel == 14)
rtw8814a_nbi_setting(rtwdev, primary_channel, 2480);
else if (primary_channel >= 4 && primary_channel <= 8)
rtw8814a_nbi_setting(rtwdev, primary_channel, 2440);
else
rtw_write32_mask(rtwdev, REG_NBI_SETTING, BIT_NBI_ENABLE, 0);
}
/* A workaround to eliminate the 5280 MHz & 5600 MHz & 5760 MHz spur of 8814A */
static void rtw8814a_spur_calibration(struct rtw_dev *rtwdev, u8 channel, u8 bw)
{
u8 rfe_type = rtwdev->efuse.rfe_option;
bool reset_nbi_csi = true;
if (rfe_type == 0) {
switch (bw) {
case RTW_CHANNEL_WIDTH_40:
if (channel == 54 || channel == 118) {
rtw_write32_mask(rtwdev, REG_NBI_SETTING,
0x000fe000, 0x3e >> 1);
rtw_write32_mask(rtwdev, REG_CSI_MASK_SETTING1,
BIT(0), 1);
rtw_write32(rtwdev, REG_CSI_FIX_MASK0, 0);
rtw_write32_mask(rtwdev, REG_CSI_FIX_MASK1,
BIT(0), 1);
rtw_write32(rtwdev, REG_CSI_FIX_MASK6, 0);
rtw_write32(rtwdev, REG_CSI_FIX_MASK7, 0);
reset_nbi_csi = false;
} else if (channel == 151) {
rtw_write32_mask(rtwdev, REG_NBI_SETTING,
0x000fe000, 0x1e >> 1);
rtw_write32_mask(rtwdev, REG_CSI_MASK_SETTING1,
BIT(0), 1);
rtw_write32_mask(rtwdev, REG_CSI_FIX_MASK0,
BIT(16), 1);
rtw_write32(rtwdev, REG_CSI_FIX_MASK1, 0);
rtw_write32(rtwdev, REG_CSI_FIX_MASK6, 0);
rtw_write32(rtwdev, REG_CSI_FIX_MASK7, 0);
reset_nbi_csi = false;
}
break;
case RTW_CHANNEL_WIDTH_80:
if (channel == 58 || channel == 122) {
rtw_write32_mask(rtwdev, REG_NBI_SETTING,
0x000fe000, 0x3a >> 1);
rtw_write32_mask(rtwdev, REG_CSI_MASK_SETTING1,
BIT(0), 1);
rtw_write32(rtwdev, REG_CSI_FIX_MASK0, 0);
rtw_write32(rtwdev, REG_CSI_FIX_MASK1, 0);
rtw_write32(rtwdev, REG_CSI_FIX_MASK6, 0);
rtw_write32_mask(rtwdev, REG_CSI_FIX_MASK7,
BIT(0), 1);
reset_nbi_csi = false;
} else if (channel == 155) {
rtw_write32_mask(rtwdev, REG_NBI_SETTING,
0x000fe000, 0x5a >> 1);
rtw_write32_mask(rtwdev, REG_CSI_MASK_SETTING1,
BIT(0), 1);
rtw_write32(rtwdev, REG_CSI_FIX_MASK0, 0);
rtw_write32(rtwdev, REG_CSI_FIX_MASK1, 0);
rtw_write32_mask(rtwdev, REG_CSI_FIX_MASK6,
BIT(16), 1);
rtw_write32(rtwdev, REG_CSI_FIX_MASK7, 0);
reset_nbi_csi = false;
}
break;
case RTW_CHANNEL_WIDTH_20:
if (channel == 153) {
rtw_write32_mask(rtwdev, REG_NBI_SETTING,
0x000fe000, 0x1e >> 1);
rtw_write32_mask(rtwdev, REG_CSI_MASK_SETTING1,
BIT(0), 1);
rtw_write32(rtwdev, REG_CSI_FIX_MASK0, 0);
rtw_write32(rtwdev, REG_CSI_FIX_MASK1, 0);
rtw_write32(rtwdev, REG_CSI_FIX_MASK6, 0);
rtw_write32_mask(rtwdev, REG_CSI_FIX_MASK7,
BIT(16), 1);
reset_nbi_csi = false;
}
rtw8814a_spur_calibration_ch140(rtwdev, channel);
break;
default:
break;
}
} else if (rfe_type == 1 || rfe_type == 2) {
switch (bw) {
case RTW_CHANNEL_WIDTH_20:
if (channel == 153) {
rtw_write32_mask(rtwdev, REG_NBI_SETTING,
0x000fe000, 0x1E >> 1);
rtw_write32_mask(rtwdev, REG_CSI_MASK_SETTING1,
BIT(0), 1);
rtw_write32(rtwdev, REG_CSI_FIX_MASK0, 0);
rtw_write32(rtwdev, REG_CSI_FIX_MASK1, 0);
rtw_write32(rtwdev, REG_CSI_FIX_MASK6, 0);
rtw_write32_mask(rtwdev, REG_CSI_FIX_MASK7,
BIT(16), 1);
reset_nbi_csi = false;
}
break;
case RTW_CHANNEL_WIDTH_40:
if (channel == 151) {
rtw_write32_mask(rtwdev, REG_NBI_SETTING,
0x000fe000, 0x1e >> 1);
rtw_write32_mask(rtwdev, REG_CSI_MASK_SETTING1,
BIT(0), 1);
rtw_write32_mask(rtwdev, REG_CSI_FIX_MASK0,
BIT(16), 1);
rtw_write32(rtwdev, REG_CSI_FIX_MASK1, 0);
rtw_write32(rtwdev, REG_CSI_FIX_MASK6, 0);
rtw_write32(rtwdev, REG_CSI_FIX_MASK7, 0);