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rtw88xxa.c
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rtw88xxa.c
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// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
/* Copyright(c) 2024 Realtek Corporation
*/
#include <linux/usb.h>
#include "main.h"
#include "coex.h"
#include "phy.h"
#include "rtw88xxa.h"
#include "mac.h"
#include "reg.h"
#include "sec.h"
#include "debug.h"
#include "bf.h"
#include "efuse.h"
#include "usb.h"
void rtw88xxa_efuse_grant(struct rtw_dev *rtwdev, bool on)
{
if (on) {
rtw_write8(rtwdev, REG_EFUSE_ACCESS, EFUSE_ACCESS_ON);
rtw_write16_set(rtwdev, REG_SYS_FUNC_EN, BIT_FEN_ELDR);
rtw_write16_set(rtwdev, REG_SYS_CLKR,
BIT_LOADER_CLK_EN | BIT_ANA8M);
} else {
rtw_write8(rtwdev, REG_EFUSE_ACCESS, EFUSE_ACCESS_OFF);
}
}
EXPORT_SYMBOL(rtw88xxa_efuse_grant);
static void rtw8812a_read_amplifier_type(struct rtw_dev *rtwdev)
{
struct rtw_efuse *efuse = &rtwdev->efuse;
efuse->ext_pa_2g = (efuse->pa_type_2g & BIT(5)) &&
(efuse->pa_type_2g & BIT(4));
efuse->ext_lna_2g = (efuse->lna_type_2g & BIT(7)) &&
(efuse->lna_type_2g & BIT(3));
efuse->ext_pa_5g = (efuse->pa_type_5g & BIT(1)) &&
(efuse->pa_type_5g & BIT(0));
efuse->ext_lna_5g = (efuse->lna_type_5g & BIT(7)) &&
(efuse->lna_type_5g & BIT(3));
/* For rtw_phy_cond2: */
if (efuse->ext_pa_2g) {
u8 ext_type_pa_2g_a = u8_get_bits(efuse->lna_type_2g, BIT(2));
u8 ext_type_pa_2g_b = u8_get_bits(efuse->lna_type_2g, BIT(6));
efuse->gpa_type = (ext_type_pa_2g_b << 2) | ext_type_pa_2g_a;
}
if (efuse->ext_pa_5g) {
u8 ext_type_pa_5g_a = u8_get_bits(efuse->lna_type_5g, BIT(2));
u8 ext_type_pa_5g_b = u8_get_bits(efuse->lna_type_5g, BIT(6));
efuse->apa_type = (ext_type_pa_5g_b << 2) | ext_type_pa_5g_a;
}
if (efuse->ext_lna_2g) {
u8 ext_type_lna_2g_a = u8_get_bits(efuse->lna_type_2g,
BIT(1) | BIT(0));
u8 ext_type_lna_2g_b = u8_get_bits(efuse->lna_type_2g,
BIT(5) | BIT(4));
efuse->glna_type = (ext_type_lna_2g_b << 2) | ext_type_lna_2g_a;
}
if (efuse->ext_lna_5g) {
u8 ext_type_lna_5g_a = u8_get_bits(efuse->lna_type_5g,
BIT(1) | BIT(0));
u8 ext_type_lna_5g_b = u8_get_bits(efuse->lna_type_5g,
BIT(5) | BIT(4));
efuse->alna_type = (ext_type_lna_5g_b << 2) | ext_type_lna_5g_a;
}
}
static void rtw8812a_read_rfe_type(struct rtw_dev *rtwdev,
struct rtw88xxa_efuse *map)
{
struct rtw_efuse *efuse = &rtwdev->efuse;
if (map->rfe_option == 0xff) {
if (rtwdev->hci.type == RTW_HCI_TYPE_USB)
efuse->rfe_option = 0;
else if (rtwdev->hci.type == RTW_HCI_TYPE_PCIE)
efuse->rfe_option = 2;
else
efuse->rfe_option = 4;
} else if (map->rfe_option & BIT(7)) {
if (efuse->ext_lna_5g) {
if (efuse->ext_pa_5g) {
if (efuse->ext_lna_2g && efuse->ext_pa_2g)
efuse->rfe_option = 3;
else
efuse->rfe_option = 0;
} else {
efuse->rfe_option = 2;
}
} else {
efuse->rfe_option = 4;
}
} else {
efuse->rfe_option = map->rfe_option & 0x3f;
/* Due to other customer already use incorrect EFUSE map for
* their product. We need to add workaround to prevent to
* modify spec and notify all customer to revise the IC 0xca
* content.
*/
if (efuse->rfe_option == 4 &&
(efuse->ext_pa_5g || efuse->ext_pa_2g ||
efuse->ext_lna_5g || efuse->ext_lna_2g)) {
if (rtwdev->hci.type == RTW_HCI_TYPE_USB)
efuse->rfe_option = 0;
else if (rtwdev->hci.type == RTW_HCI_TYPE_PCIE)
efuse->rfe_option = 2;
}
}
}
static void rtw88xxa_read_usb_type(struct rtw_dev *rtwdev)
{
struct rtw_efuse *efuse = &rtwdev->efuse;
struct rtw_hal *hal = &rtwdev->hal;
u8 antenna = 0;
u8 wmode = 0;
u8 val8, i;
efuse->hw_cap.bw = BIT(RTW_CHANNEL_WIDTH_20) |
BIT(RTW_CHANNEL_WIDTH_40) |
BIT(RTW_CHANNEL_WIDTH_80);
efuse->hw_cap.ptcl = EFUSE_HW_CAP_PTCL_VHT;
if (rtwdev->chip->id == RTW_CHIP_TYPE_8821A)
efuse->hw_cap.nss = 1;
else
efuse->hw_cap.nss = 2;
if (rtwdev->chip->id == RTW_CHIP_TYPE_8821A)
goto print_hw_cap;
for (i = 0; i < 2; i++) {
rtw_read8_physical_efuse(rtwdev, 1019 - i, &val8);
antenna = u8_get_bits(val8, GENMASK(7, 5));
if (antenna)
break;
antenna = u8_get_bits(val8, GENMASK(3, 1));
if (antenna)
break;
}
for (i = 0; i < 2; i++) {
rtw_read8_physical_efuse(rtwdev, 1021 - i, &val8);
wmode = u8_get_bits(val8, GENMASK(3, 2));
if (wmode)
break;
}
if (antenna == 1) {
rtw_info(rtwdev, "This RTL8812AU says it is 1T1R.\n");
efuse->hw_cap.nss = 1;
hal->rf_type = RF_1T1R;
hal->rf_path_num = 1;
hal->rf_phy_num = 1;
hal->antenna_tx = BB_PATH_A;
hal->antenna_rx = BB_PATH_A;
} else {
/* Override rtw_chip_parameter_setup(). It detects 8812au as 1T1R. */
efuse->hw_cap.nss = 2;
hal->rf_type = RF_2T2R;
hal->rf_path_num = 2;
hal->rf_phy_num = 2;
hal->antenna_tx = BB_PATH_AB;
hal->antenna_rx = BB_PATH_AB;
if (antenna == 2 && wmode == 2) {
rtw_info(rtwdev, "This RTL8812AU says it can't do VHT.\n");
/* Can't be EFUSE_HW_CAP_IGNORE and can't be
* EFUSE_HW_CAP_PTCL_VHT, so make it 1.
*/
efuse->hw_cap.ptcl = 1;
efuse->hw_cap.bw &= ~BIT(RTW_CHANNEL_WIDTH_80);
}
}
print_hw_cap:
rtw_dbg(rtwdev, RTW_DBG_EFUSE,
"hw cap: hci=0x%02x, bw=0x%02x, ptcl=0x%02x, ant_num=%d, nss=%d\n",
efuse->hw_cap.hci, efuse->hw_cap.bw, efuse->hw_cap.ptcl,
efuse->hw_cap.ant_num, efuse->hw_cap.nss);
}
int rtw88xxa_read_efuse(struct rtw_dev *rtwdev, u8 *log_map)
{
const struct rtw_chip_info *chip = rtwdev->chip;
struct rtw_efuse *efuse = &rtwdev->efuse;
struct rtw88xxa_efuse *map;
int i;
if (chip->id == RTW_CHIP_TYPE_8812A)
rtwdev->hal.cut_version += 1;
if (rtw_dbg_is_enabled(rtwdev, RTW_DBG_EFUSE))
print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET, 16, 1,
log_map, chip->log_efuse_size, true);
map = (struct rtw88xxa_efuse *)log_map;
efuse->rf_board_option = map->rf_board_option;
efuse->crystal_cap = map->xtal_k;
if (efuse->crystal_cap == 0xff)
efuse->crystal_cap = 0x20;
efuse->pa_type_2g = map->pa_type;
efuse->pa_type_5g = map->pa_type;
efuse->lna_type_2g = map->lna_type_2g;
efuse->lna_type_5g = map->lna_type_5g;
if (chip->id == RTW_CHIP_TYPE_8812A) {
rtw8812a_read_amplifier_type(rtwdev);
rtw8812a_read_rfe_type(rtwdev, map);
efuse->usb_mode_switch = u8_get_bits(map->usb_mode, BIT(1));
}
efuse->channel_plan = map->channel_plan;
efuse->country_code[0] = map->country_code[0];
efuse->country_code[1] = map->country_code[1];
efuse->bt_setting = map->rf_bt_setting;
efuse->regd = map->rf_board_option & 0x7;
efuse->thermal_meter[0] = map->thermal_meter;
efuse->thermal_meter[1] = map->thermal_meter;
efuse->thermal_meter_k = map->thermal_meter;
efuse->tx_bb_swing_setting_2g = map->tx_bb_swing_setting_2g;
efuse->tx_bb_swing_setting_5g = map->tx_bb_swing_setting_5g;
rtw88xxa_read_usb_type(rtwdev);
if (chip->id == RTW_CHIP_TYPE_8821A)
efuse->btcoex = rtw_read32_mask(rtwdev, REG_WL_BT_PWR_CTRL,
BIT_BT_FUNC_EN);
else
efuse->btcoex = (map->rf_board_option & 0xe0) == 0x20;
efuse->share_ant = !!(efuse->bt_setting & BIT(0));
/* No antenna diversity because it's disabled in the vendor driver */
efuse->ant_div_cfg = 0;
efuse->ant_div_type = map->rf_antenna_option;
if (efuse->ant_div_type == 0xff)
efuse->ant_div_type = 0x3;
for (i = 0; i < 4; i++)
efuse->txpwr_idx_table[i] = map->txpwr_idx_table[i];
switch (rtw_hci_type(rtwdev)) {
case RTW_HCI_TYPE_USB:
if (chip->id == RTW_CHIP_TYPE_8821A)
ether_addr_copy(efuse->addr, map->rtw8821au.mac_addr);
else
ether_addr_copy(efuse->addr, map->rtw8812au.mac_addr);
break;
case RTW_HCI_TYPE_PCIE:
case RTW_HCI_TYPE_SDIO:
default:
/* unsupported now */
return -EOPNOTSUPP;
}
return 0;
}
EXPORT_SYMBOL(rtw88xxa_read_efuse);
static void rtw88xxa_reset_8051(struct rtw_dev *rtwdev)
{
const struct rtw_chip_info *chip = rtwdev->chip;
u8 val8;
/* Reset MCU IO Wrapper */
rtw_write8_clr(rtwdev, REG_RSV_CTRL, BIT(1));
if (chip->id == RTW_CHIP_TYPE_8812A)
rtw_write8_clr(rtwdev, REG_RSV_CTRL + 1, BIT(3));
else
rtw_write8_clr(rtwdev, REG_RSV_CTRL + 1, BIT(0));
val8 = rtw_read8(rtwdev, REG_SYS_FUNC_EN + 1);
rtw_write8(rtwdev, REG_SYS_FUNC_EN + 1, val8 & ~BIT(2));
/* Enable MCU IO Wrapper */
rtw_write8_clr(rtwdev, REG_RSV_CTRL, BIT(1));
if (chip->id == RTW_CHIP_TYPE_8812A)
rtw_write8_set(rtwdev, REG_RSV_CTRL + 1, BIT(3));
else
rtw_write8_set(rtwdev, REG_RSV_CTRL + 1, BIT(0));
rtw_write8(rtwdev, REG_SYS_FUNC_EN + 1, val8 | BIT(2));
}
/* A lightweight deinit function */
static void rtw88xxau_hw_reset(struct rtw_dev *rtwdev)
{
u8 val8;
if (!(rtw_read8(rtwdev, REG_MCUFW_CTRL) & BIT_RAM_DL_SEL))
return;
rtw88xxa_reset_8051(rtwdev);
rtw_write8(rtwdev, REG_MCUFW_CTRL, 0x00);
/* before BB reset should do clock gated */
rtw_write32_set(rtwdev, REG_FPGA0_XCD_RF_PARA, BIT(6));
/* reset BB */
rtw_write8_clr(rtwdev, REG_SYS_FUNC_EN, BIT(0) | BIT(1));
/* reset RF */
rtw_write8(rtwdev, REG_RF_CTRL, 0);
/* reset TRX path */
rtw_write16(rtwdev, REG_CR, 0);
/* reset MAC, reg0x5[1], auto FSM off */
rtw_write8_set(rtwdev, REG_APS_FSMCO + 1, APS_FSMCO_MAC_OFF >> 8);
/* check if reg0x5[1] auto cleared */
if (read_poll_timeout_atomic(rtw_read8, val8,
!(val8 & (APS_FSMCO_MAC_OFF >> 8)),
1, 5000, false,
rtwdev, REG_APS_FSMCO + 1))
rtw_err(rtwdev, "%s: timed out waiting for 0x5[1]\n", __func__);
/* reg0x5[0], auto FSM on */
val8 |= APS_FSMCO_MAC_ENABLE >> 8;
rtw_write8(rtwdev, REG_APS_FSMCO + 1, val8);
rtw_write8_clr(rtwdev, REG_SYS_FUNC_EN + 1, BIT(4) | BIT(7));
rtw_write8_set(rtwdev, REG_SYS_FUNC_EN + 1, BIT(4) | BIT(7));
}
static int rtw88xxau_init_power_on(struct rtw_dev *rtwdev)
{
const struct rtw_chip_info *chip = rtwdev->chip;
u16 val16;
int ret;
ret = rtw_pwr_seq_parser(rtwdev, chip->pwr_on_seq);
if (ret) {
rtw_err(rtwdev, "power on flow failed\n");
return ret;
}
rtw_write16(rtwdev, REG_CR, 0);
val16 = BIT_HCI_TXDMA_EN | BIT_HCI_RXDMA_EN | BIT_TXDMA_EN |
BIT_RXDMA_EN | BIT_PROTOCOL_EN | BIT_SCHEDULE_EN |
BIT_MAC_SEC_EN | BIT_32K_CAL_TMR_EN;
rtw_write16_set(rtwdev, REG_CR, val16);
if (chip->id == RTW_CHIP_TYPE_8821A) {
if (rtw_read8(rtwdev, REG_SYS_CFG1 + 3) & BIT(0))
rtw_write8_set(rtwdev, REG_LDO_SWR_CTRL, BIT(6));
}
return ret;
}
static int rtw88xxa_llt_write(struct rtw_dev *rtwdev, u32 address, u32 data)
{
u32 value = BIT_LLT_WRITE_ACCESS | (address << 8) | data;
int count = 0;
rtw_write32(rtwdev, REG_LLT_INIT, value);
do {
if (!rtw_read32_mask(rtwdev, REG_LLT_INIT, BIT(31) | BIT(30)))
break;
if (count > 20) {
rtw_err(rtwdev, "Failed to poll write LLT done at %d!\n",
address);
return -EBUSY;
}
} while (++count);
return 0;
}
static int rtw88xxa_llt_init(struct rtw_dev *rtwdev, u32 boundary)
{
u32 last_entry = 255;
int status = 0;
u32 i;
for (i = 0; i < boundary - 1; i++) {
status = rtw88xxa_llt_write(rtwdev, i, i + 1);
if (status)
return status;
}
status = rtw88xxa_llt_write(rtwdev, boundary - 1, 0xFF);
if (status)
return status;
for (i = boundary; i < last_entry; i++) {
status = rtw88xxa_llt_write(rtwdev, i, i + 1);
if (status)
return status;
}
status = rtw88xxa_llt_write(rtwdev, last_entry, boundary);
return status;
}
static void rtw88xxau_init_queue_reserved_page(struct rtw_dev *rtwdev)
{
const struct rtw_chip_info *chip = rtwdev->chip;
struct rtw_fifo_conf *fifo = &rtwdev->fifo;
const struct rtw_page_table *pg_tbl = NULL;
u16 pubq_num;
u32 val32;
switch (rtw_hci_type(rtwdev)) {
case RTW_HCI_TYPE_PCIE:
pg_tbl = &chip->page_table[1];
break;
case RTW_HCI_TYPE_USB:
if (rtwdev->hci.bulkout_num == 2)
pg_tbl = &chip->page_table[2];
else if (rtwdev->hci.bulkout_num == 3)
pg_tbl = &chip->page_table[3];
else if (rtwdev->hci.bulkout_num == 4)
pg_tbl = &chip->page_table[4];
break;
case RTW_HCI_TYPE_SDIO:
pg_tbl = &chip->page_table[0];
break;
default:
break;
}
pubq_num = fifo->acq_pg_num - pg_tbl->hq_num - pg_tbl->lq_num -
pg_tbl->nq_num - pg_tbl->exq_num - pg_tbl->gapq_num;
val32 = BIT_RQPN_NE(pg_tbl->nq_num, pg_tbl->exq_num);
rtw_write32(rtwdev, REG_RQPN_NPQ, val32);
val32 = BIT_RQPN_HLP(pg_tbl->hq_num, pg_tbl->lq_num, pubq_num);
rtw_write32(rtwdev, REG_RQPN, val32);
}
static void rtw88xxau_init_tx_buffer_boundary(struct rtw_dev *rtwdev)
{
struct rtw_fifo_conf *fifo = &rtwdev->fifo;
rtw_write8(rtwdev, REG_BCNQ_BDNY, fifo->rsvd_boundary);
rtw_write8(rtwdev, REG_MGQ_BDNY, fifo->rsvd_boundary);
rtw_write8(rtwdev, REG_WMAC_LBK_BF_HD, fifo->rsvd_boundary);
rtw_write8(rtwdev, REG_TRXFF_BNDY, fifo->rsvd_boundary);
rtw_write8(rtwdev, REG_DWBCN0_CTRL + 1, fifo->rsvd_boundary);
}
static int rtw88xxau_init_queue_priority(struct rtw_dev *rtwdev)
{
const struct rtw_chip_info *chip = rtwdev->chip;
u8 bulkout_num = rtwdev->hci.bulkout_num;
const struct rtw_rqpn *rqpn = NULL;
u16 txdma_pq_map;
switch (rtw_hci_type(rtwdev)) {
case RTW_HCI_TYPE_PCIE:
rqpn = &chip->rqpn_table[1];
break;
case RTW_HCI_TYPE_USB:
if (bulkout_num == 2)
rqpn = &chip->rqpn_table[2];
else if (bulkout_num == 3)
rqpn = &chip->rqpn_table[3];
else if (bulkout_num == 4)
rqpn = &chip->rqpn_table[4];
else
return -EINVAL;
break;
case RTW_HCI_TYPE_SDIO:
rqpn = &chip->rqpn_table[0];
break;
default:
return -EINVAL;
}
rtwdev->fifo.rqpn = rqpn;
txdma_pq_map = rtw_read16(rtwdev, REG_TXDMA_PQ_MAP) & 0x7;
txdma_pq_map |= BIT_TXDMA_HIQ_MAP(rqpn->dma_map_hi);
txdma_pq_map |= BIT_TXDMA_MGQ_MAP(rqpn->dma_map_mg);
txdma_pq_map |= BIT_TXDMA_BKQ_MAP(rqpn->dma_map_bk);
txdma_pq_map |= BIT_TXDMA_BEQ_MAP(rqpn->dma_map_be);
txdma_pq_map |= BIT_TXDMA_VIQ_MAP(rqpn->dma_map_vi);
txdma_pq_map |= BIT_TXDMA_VOQ_MAP(rqpn->dma_map_vo);
rtw_write16(rtwdev, REG_TXDMA_PQ_MAP, txdma_pq_map);
/* Packet in Hi Queue Tx immediately (No constraint for ATIM Period). */
if (rtw_hci_type(rtwdev) == RTW_HCI_TYPE_USB && bulkout_num == 4)
rtw_write8(rtwdev, REG_HIQ_NO_LMT_EN, 0xff);
return 0;
}
static void rtw88xxa_init_wmac_setting(struct rtw_dev *rtwdev)
{
rtw_write16(rtwdev, REG_RXFLTMAP0, 0xffff);
rtw_write16(rtwdev, REG_RXFLTMAP1, 0x0400);
rtw_write16(rtwdev, REG_RXFLTMAP2, 0xffff);
rtw_write32(rtwdev, REG_MAR, 0xffffffff);
rtw_write32(rtwdev, REG_MAR + 4, 0xffffffff);
}
static void rtw88xxa_init_adaptive_ctrl(struct rtw_dev *rtwdev)
{
rtw_write32_mask(rtwdev, REG_RRSR, 0xfffff, 0xffff1);
rtw_write16(rtwdev, REG_RETRY_LIMIT, 0x3030);
}
static void rtw88xxa_init_edca(struct rtw_dev *rtwdev)
{
rtw_write16(rtwdev, REG_SPEC_SIFS, 0x100a);
rtw_write16(rtwdev, REG_MAC_SPEC_SIFS, 0x100a);
rtw_write16(rtwdev, REG_SIFS, 0x100a);
rtw_write16(rtwdev, REG_SIFS + 2, 0x100a);
rtw_write32(rtwdev, REG_EDCA_BE_PARAM, 0x005EA42B);
rtw_write32(rtwdev, REG_EDCA_BK_PARAM, 0x0000A44F);
rtw_write32(rtwdev, REG_EDCA_VI_PARAM, 0x005EA324);
rtw_write32(rtwdev, REG_EDCA_VO_PARAM, 0x002FA226);
rtw_write8(rtwdev, REG_USTIME_TSF, 0x50);
rtw_write8(rtwdev, REG_USTIME_EDCA, 0x50);
}
static void rtw88xxau_tx_aggregation(struct rtw_dev *rtwdev)
{
const struct rtw_chip_info *chip = rtwdev->chip;
rtw_write32_mask(rtwdev, REG_DWBCN0_CTRL, 0xf0,
chip->usb_tx_agg_desc_num);
if (chip->id == RTW_CHIP_TYPE_8821A)
rtw_write8(rtwdev, REG_DWBCN1_CTRL,
chip->usb_tx_agg_desc_num << 1);
}
static void rtw88xxa_init_beacon_parameters(struct rtw_dev *rtwdev)
{
u16 val16;
val16 = (BIT_DIS_TSF_UDT << 8) | BIT_DIS_TSF_UDT;
if (rtwdev->efuse.btcoex)
val16 |= BIT_EN_BCN_FUNCTION;
rtw_write16(rtwdev, REG_BCN_CTRL, val16);
rtw_write32_mask(rtwdev, REG_TBTT_PROHIBIT, 0xfffff, WLAN_TBTT_TIME);
rtw_write8(rtwdev, REG_DRVERLYINT, 0x05);
rtw_write8(rtwdev, REG_BCNDMATIM, WLAN_BCN_DMA_TIME);
rtw_write16(rtwdev, REG_BCNTCFG, 0x4413);
}
static void rtw88xxa_phy_bb_config(struct rtw_dev *rtwdev)
{
u8 val8, crystal_cap;
/* power on BB/RF domain */
val8 = rtw_read8(rtwdev, REG_SYS_FUNC_EN);
val8 |= BIT_FEN_USBA;
rtw_write8(rtwdev, REG_SYS_FUNC_EN, val8);
/* toggle BB reset */
val8 |= BIT_FEN_BB_RSTB | BIT_FEN_BB_GLB_RST;
rtw_write8(rtwdev, REG_SYS_FUNC_EN, val8);
rtw_write8(rtwdev, REG_RF_CTRL,
BIT_RF_EN | BIT_RF_RSTB | BIT_RF_SDM_RSTB);
rtw_write8(rtwdev, REG_RF_B_CTRL,
BIT_RF_EN | BIT_RF_RSTB | BIT_RF_SDM_RSTB);
rtw_load_table(rtwdev, rtwdev->chip->bb_tbl);
rtw_load_table(rtwdev, rtwdev->chip->agc_tbl);
crystal_cap = rtwdev->efuse.crystal_cap & 0x3F;
if (rtwdev->chip->id == RTW_CHIP_TYPE_8812A)
rtw_write32_mask(rtwdev, REG_AFE_CTRL3, 0x7FF80000,
crystal_cap | (crystal_cap << 6));
else
rtw_write32_mask(rtwdev, REG_AFE_CTRL3, 0x00FFF000,
crystal_cap | (crystal_cap << 6));
}
static void rtw88xxa_phy_rf_config(struct rtw_dev *rtwdev)
{
u8 rf_path;
for (rf_path = 0; rf_path < rtwdev->hal.rf_path_num; rf_path++)
rtw_load_table(rtwdev, rtwdev->chip->rf_tbl[rf_path]);
}
static void rtw8812a_config_1t(struct rtw_dev *rtwdev)
{
/* BB OFDM RX Path_A */
rtw_write32_mask(rtwdev, REG_RXPSEL, 0xff, 0x11);
/* BB OFDM TX Path_A */
rtw_write32_mask(rtwdev, REG_TXPSEL, MASKLWORD, 0x1111);
/* BB CCK R/Rx Path_A */
rtw_write32_mask(rtwdev, REG_CCK_RX, 0x0c000000, 0x0);
/* MCS support */
rtw_write32_mask(rtwdev, REG_RX_MCS_LIMIT, 0xc0000060, 0x4);
/* RF Path_B HSSI OFF */
rtw_write32_mask(rtwdev, REG_3WIRE_SWB, 0xf, 0x4);
/* RF Path_B Power Down */
rtw_write32_mask(rtwdev, REG_LSSI_WRITE_B, MASKDWORD, 0);
/* ADDA Path_B OFF */
rtw_write32_mask(rtwdev, REG_AFE_PWR1_B, MASKDWORD, 0);
rtw_write32_mask(rtwdev, REG_AFE_PWR2_B, MASKDWORD, 0);
}
static const u32 rtw88xxa_txscale_tbl[] = {
0x081, 0x088, 0x090, 0x099, 0x0a2, 0x0ac, 0x0b6, 0x0c0, 0x0cc, 0x0d8,
0x0e5, 0x0f2, 0x101, 0x110, 0x120, 0x131, 0x143, 0x156, 0x16a, 0x180,
0x197, 0x1af, 0x1c8, 0x1e3, 0x200, 0x21e, 0x23e, 0x261, 0x285, 0x2ab,
0x2d3, 0x2fe, 0x32b, 0x35c, 0x38e, 0x3c4, 0x3fe
};
static u32 rtw88xxa_get_bb_swing(struct rtw_dev *rtwdev, u8 band, u8 path)
{
static const u32 swing2setting[4] = {0x200, 0x16a, 0x101, 0x0b6};
struct rtw_efuse *efuse = &rtwdev->efuse;
u8 tx_bb_swing;
if (band == RTW_BAND_2G)
tx_bb_swing = efuse->tx_bb_swing_setting_2g;
else
tx_bb_swing = efuse->tx_bb_swing_setting_5g;
if (path == RF_PATH_B)
tx_bb_swing >>= 2;
tx_bb_swing &= 0x3;
return swing2setting[tx_bb_swing];
}
static u8 rtw88xxa_get_swing_index(struct rtw_dev *rtwdev)
{
u32 swing, table_value;
u8 i;
swing = rtw88xxa_get_bb_swing(rtwdev, rtwdev->hal.current_band_type,
RF_PATH_A);
for (i = 0; i < ARRAY_SIZE(rtw88xxa_txscale_tbl); i++) {
table_value = rtw88xxa_txscale_tbl[i];
if (swing == table_value)
return i;
}
return 24;
}
static void rtw88xxa_pwrtrack_init(struct rtw_dev *rtwdev)
{
struct rtw_dm_info *dm_info = &rtwdev->dm_info;
u8 path;
dm_info->default_ofdm_index = rtw88xxa_get_swing_index(rtwdev);
if (rtwdev->chip->id == RTW_CHIP_TYPE_8821A)
dm_info->default_cck_index = 0;
else
dm_info->default_cck_index = 24;
for (path = RF_PATH_A; path < rtwdev->hal.rf_path_num; path++) {
ewma_thermal_init(&dm_info->avg_thermal[path]);
dm_info->delta_power_index[path] = 0;
dm_info->delta_power_index_last[path] = 0;
}
dm_info->pwr_trk_triggered = false;
dm_info->pwr_trk_init_trigger = true;
dm_info->thermal_meter_k = rtwdev->efuse.thermal_meter_k;
}
void rtw88xxa_power_off(struct rtw_dev *rtwdev,
const struct rtw_pwr_seq_cmd *const *enter_lps_flow)
{
struct rtw_usb *rtwusb = rtw_get_usb_priv(rtwdev);
enum usb_device_speed speed = rtwusb->udev->speed;
u16 ori_fsmc0;
u8 reg_cr;
reg_cr = rtw_read8(rtwdev, REG_CR);
/* Already powered off */
if (reg_cr == 0 || reg_cr == 0xEA)
return;
rtw_hci_stop(rtwdev);
if (!rtwdev->efuse.btcoex)
rtw_write16_clr(rtwdev, REG_GPIO_MUXCFG, BIT_EN_SIC);
/* set Reg 0xf008[3:4] to 2'11 to enable U1/U2 Mode in USB3.0. */
if (speed == USB_SPEED_SUPER)
rtw_write8_set(rtwdev, REG_USB_MOD, 0x18);
rtw_write32(rtwdev, REG_HISR0, 0xffffffff);
rtw_write32(rtwdev, REG_HISR1, 0xffffffff);
rtw_write32(rtwdev, REG_HIMR0, 0);
rtw_write32(rtwdev, REG_HIMR1, 0);
if (rtwdev->efuse.btcoex)
rtw_coex_power_off_setting(rtwdev);
ori_fsmc0 = rtw_read16(rtwdev, REG_APS_FSMCO);
rtw_write16(rtwdev, REG_APS_FSMCO, ori_fsmc0 & ~APS_FSMCO_HW_POWERDOWN);
/* Stop Tx Report Timer. */
rtw_write8_clr(rtwdev, REG_TX_RPT_CTRL, BIT(1));
/* Stop Rx */
rtw_write8(rtwdev, REG_CR, 0);
rtw_pwr_seq_parser(rtwdev, enter_lps_flow);
if (rtw_read8(rtwdev, REG_MCUFW_CTRL) & BIT_RAM_DL_SEL)
rtw88xxa_reset_8051(rtwdev);
rtw_write8_clr(rtwdev, REG_SYS_FUNC_EN + 1, BIT(2));
rtw_write8(rtwdev, REG_MCUFW_CTRL, 0);
rtw_pwr_seq_parser(rtwdev, rtwdev->chip->pwr_off_seq);
if (ori_fsmc0 & APS_FSMCO_HW_POWERDOWN)
rtw_write16_set(rtwdev, REG_APS_FSMCO, APS_FSMCO_HW_POWERDOWN);
clear_bit(RTW_FLAG_POWERON, rtwdev->flags);
}
EXPORT_SYMBOL(rtw88xxa_power_off);
static void rtw88xxa_set_channel_bb_swing(struct rtw_dev *rtwdev, u8 band)
{
rtw_write32_mask(rtwdev, REG_TXSCALE_A, BB_SWING_MASK,
rtw88xxa_get_bb_swing(rtwdev, band, RF_PATH_A));
rtw_write32_mask(rtwdev, REG_TXSCALE_B, BB_SWING_MASK,
rtw88xxa_get_bb_swing(rtwdev, band, RF_PATH_B));
rtw88xxa_pwrtrack_init(rtwdev);
}
static void rtw8821a_set_ext_band_switch(struct rtw_dev *rtwdev, u8 band)
{
rtw_write32_mask(rtwdev, REG_LED_CFG, BIT_DPDT_SEL_EN, 0);
rtw_write32_mask(rtwdev, REG_LED_CFG, BIT_DPDT_WL_SEL, 1);
rtw_write32_mask(rtwdev, REG_RFE_INV_A, 0xf, 7);
rtw_write32_mask(rtwdev, REG_RFE_INV_A, 0xf0, 7);
if (band == RTW_BAND_2G)
rtw_write32_mask(rtwdev, REG_RFE_INV_A, BIT(29) | BIT(28), 1);
else
rtw_write32_mask(rtwdev, REG_RFE_INV_A, BIT(29) | BIT(28), 2);
}
static void rtw8821a_phy_set_rfe_reg_24g(struct rtw_dev *rtwdev)
{
struct rtw_efuse *efuse = &rtwdev->efuse;
/* Turn off RF PA and LNA */
/* 0xCB0[15:12] = 0x7 (LNA_On)*/
rtw_write32_mask(rtwdev, REG_RFE_PINMUX_A, 0xF000, 0x7);
/* 0xCB0[7:4] = 0x7 (PAPE_A)*/
rtw_write32_mask(rtwdev, REG_RFE_PINMUX_A, 0xF0, 0x7);
if (efuse->ext_lna_2g) {
/* Turn on 2.4G External LNA */
rtw_write32_mask(rtwdev, REG_RFE_INV_A, BIT(20), 1);
rtw_write32_mask(rtwdev, REG_RFE_INV_A, BIT(22), 0);
rtw_write32_mask(rtwdev, REG_RFE_PINMUX_A, GENMASK(2, 0), 0x2);
rtw_write32_mask(rtwdev, REG_RFE_PINMUX_A, GENMASK(10, 8), 0x2);
} else {
/* Bypass 2.4G External LNA */
rtw_write32_mask(rtwdev, REG_RFE_INV_A, BIT(20), 0);
rtw_write32_mask(rtwdev, REG_RFE_INV_A, BIT(22), 0);
rtw_write32_mask(rtwdev, REG_RFE_PINMUX_A, GENMASK(2, 0), 0x7);
rtw_write32_mask(rtwdev, REG_RFE_PINMUX_A, GENMASK(10, 8), 0x7);
}
}
static void rtw8821a_phy_set_rfe_reg_5g(struct rtw_dev *rtwdev)
{
/* Turn ON RF PA and LNA */
/* 0xCB0[15:12] = 0x7 (LNA_On)*/
rtw_write32_mask(rtwdev, REG_RFE_PINMUX_A, 0xF000, 0x5);
/* 0xCB0[7:4] = 0x7 (PAPE_A)*/
rtw_write32_mask(rtwdev, REG_RFE_PINMUX_A, 0xF0, 0x4);
/* Bypass 2.4G External LNA */
rtw_write32_mask(rtwdev, REG_RFE_INV_A, BIT(20), 0);
rtw_write32_mask(rtwdev, REG_RFE_INV_A, BIT(22), 0);
rtw_write32_mask(rtwdev, REG_RFE_PINMUX_A, GENMASK(2, 0), 0x7);
rtw_write32_mask(rtwdev, REG_RFE_PINMUX_A, GENMASK(10, 8), 0x7);
}
static void rtw8812a_phy_set_rfe_reg_24g(struct rtw_dev *rtwdev)
{
switch (rtwdev->efuse.rfe_option) {
case 0:
case 2:
rtw_write32(rtwdev, REG_RFE_PINMUX_A, 0x77777777);
rtw_write32(rtwdev, REG_RFE_PINMUX_B, 0x77777777);
rtw_write32_mask(rtwdev, REG_RFE_INV_A, RFE_INV_MASK, 0x000);
rtw_write32_mask(rtwdev, REG_RFE_INV_B, RFE_INV_MASK, 0x000);
break;
case 1:
if (rtwdev->efuse.btcoex) {
rtw_write32_mask(rtwdev, REG_RFE_PINMUX_A, 0xffffff, 0x777777);
rtw_write32(rtwdev, REG_RFE_PINMUX_B, 0x77777777);
rtw_write32_mask(rtwdev, REG_RFE_INV_A, 0x33f00000, 0x000);
rtw_write32_mask(rtwdev, REG_RFE_INV_B, RFE_INV_MASK, 0x000);
} else {
rtw_write32(rtwdev, REG_RFE_PINMUX_A, 0x77777777);
rtw_write32(rtwdev, REG_RFE_PINMUX_B, 0x77777777);
rtw_write32_mask(rtwdev, REG_RFE_INV_A, RFE_INV_MASK, 0x000);
rtw_write32_mask(rtwdev, REG_RFE_INV_B, RFE_INV_MASK, 0x000);
}
break;
case 3:
rtw_write32(rtwdev, REG_RFE_PINMUX_A, 0x54337770);
rtw_write32(rtwdev, REG_RFE_PINMUX_B, 0x54337770);
rtw_write32_mask(rtwdev, REG_RFE_INV_A, RFE_INV_MASK, 0x010);
rtw_write32_mask(rtwdev, REG_RFE_INV_B, RFE_INV_MASK, 0x010);
rtw_write32_mask(rtwdev, REG_ANTSEL_SW, 0x00000303, 0x1);
break;
case 4:
rtw_write32(rtwdev, REG_RFE_PINMUX_A, 0x77777777);
rtw_write32(rtwdev, REG_RFE_PINMUX_B, 0x77777777);
rtw_write32_mask(rtwdev, REG_RFE_INV_A, RFE_INV_MASK, 0x001);
rtw_write32_mask(rtwdev, REG_RFE_INV_B, RFE_INV_MASK, 0x001);
break;
case 5:
rtw_write8(rtwdev, REG_RFE_PINMUX_A + 2, 0x77);
rtw_write32(rtwdev, REG_RFE_PINMUX_B, 0x77777777);
rtw_write8_clr(rtwdev, REG_RFE_INV_A + 3, BIT(0));
rtw_write32_mask(rtwdev, REG_RFE_INV_B, RFE_INV_MASK, 0x000);
break;
case 6:
rtw_write32(rtwdev, REG_RFE_PINMUX_A, 0x07772770);
rtw_write32(rtwdev, REG_RFE_PINMUX_B, 0x07772770);
rtw_write32(rtwdev, REG_RFE_INV_A, 0x00000077);
rtw_write32(rtwdev, REG_RFE_INV_B, 0x00000077);
break;
default:
break;
}
}
static void rtw8812a_phy_set_rfe_reg_5g(struct rtw_dev *rtwdev)
{
switch (rtwdev->efuse.rfe_option) {
case 0:
rtw_write32(rtwdev, REG_RFE_PINMUX_A, 0x77337717);
rtw_write32(rtwdev, REG_RFE_PINMUX_B, 0x77337717);
rtw_write32_mask(rtwdev, REG_RFE_INV_A, RFE_INV_MASK, 0x010);
rtw_write32_mask(rtwdev, REG_RFE_INV_B, RFE_INV_MASK, 0x010);
break;
case 1:
if (rtwdev->efuse.btcoex) {
rtw_write32_mask(rtwdev, REG_RFE_PINMUX_A, 0xffffff, 0x337717);
rtw_write32(rtwdev, REG_RFE_PINMUX_B, 0x77337717);
rtw_write32_mask(rtwdev, REG_RFE_INV_A, 0x33f00000, 0x000);
rtw_write32_mask(rtwdev, REG_RFE_INV_B, RFE_INV_MASK, 0x000);
} else {
rtw_write32(rtwdev, REG_RFE_PINMUX_A, 0x77337717);
rtw_write32(rtwdev, REG_RFE_PINMUX_B, 0x77337717);
rtw_write32_mask(rtwdev, REG_RFE_INV_A, RFE_INV_MASK, 0x000);
rtw_write32_mask(rtwdev, REG_RFE_INV_B, RFE_INV_MASK, 0x000);
}
break;
case 2:
case 4:
rtw_write32(rtwdev, REG_RFE_PINMUX_A, 0x77337777);
rtw_write32(rtwdev, REG_RFE_PINMUX_B, 0x77337777);
rtw_write32_mask(rtwdev, REG_RFE_INV_A, RFE_INV_MASK, 0x010);
rtw_write32_mask(rtwdev, REG_RFE_INV_B, RFE_INV_MASK, 0x010);
break;
case 3:
rtw_write32(rtwdev, REG_RFE_PINMUX_A, 0x54337717);
rtw_write32(rtwdev, REG_RFE_PINMUX_B, 0x54337717);
rtw_write32_mask(rtwdev, REG_RFE_INV_A, RFE_INV_MASK, 0x010);
rtw_write32_mask(rtwdev, REG_RFE_INV_B, RFE_INV_MASK, 0x010);
rtw_write32_mask(rtwdev, REG_ANTSEL_SW, 0x00000303, 0x1);
break;
case 5:
rtw_write8(rtwdev, REG_RFE_PINMUX_A + 2, 0x33);
rtw_write32(rtwdev, REG_RFE_PINMUX_B, 0x77337777);
rtw_write8_set(rtwdev, REG_RFE_INV_A + 3, BIT(0));
rtw_write32_mask(rtwdev, REG_RFE_INV_B, RFE_INV_MASK, 0x010);
break;
case 6:
rtw_write32(rtwdev, REG_RFE_PINMUX_A, 0x07737717);
rtw_write32(rtwdev, REG_RFE_PINMUX_B, 0x07737717);
rtw_write32(rtwdev, REG_RFE_INV_A, 0x00000077);
rtw_write32(rtwdev, REG_RFE_INV_B, 0x00000077);
break;
default:
break;
}
}
static void rtw88xxa_switch_band(struct rtw_dev *rtwdev, u8 new_band, u8 bw)
{
const struct rtw_chip_info *chip = rtwdev->chip;
u16 basic_rates, reg_41a;
/* 8811au one antenna module doesn't support antenna div, so driver must
* control antenna band, otherwise one of the band will have issue
*/
if (chip->id == RTW_CHIP_TYPE_8821A && !rtwdev->efuse.btcoex &&
rtwdev->efuse.ant_div_cfg == 0)
rtw8821a_set_ext_band_switch(rtwdev, new_band);
if (new_band == RTW_BAND_2G) {
rtw_write32_set(rtwdev, REG_RXPSEL, BIT_RX_PSEL_RST);
if (chip->id == RTW_CHIP_TYPE_8821A) {
rtw8821a_phy_set_rfe_reg_24g(rtwdev);
rtw_write32_mask(rtwdev, REG_TXSCALE_A, 0xf00, 0);
} else {
rtw_write32_mask(rtwdev, REG_BWINDICATION, 0x3, 0x1);
rtw_write32_mask(rtwdev, REG_PDMFTH, GENMASK(17, 13), 0x17);
if (bw == RTW_CHANNEL_WIDTH_20 &&
rtwdev->hal.rf_type == RF_1T1R &&
!rtwdev->efuse.ext_lna_2g)
rtw_write32_mask(rtwdev, REG_PDMFTH, GENMASK(3, 1), 0x02);
else
rtw_write32_mask(rtwdev, REG_PDMFTH, GENMASK(3, 1), 0x04);
rtw_write32_mask(rtwdev, REG_CCASEL, 0x3, 0);
rtw8812a_phy_set_rfe_reg_24g(rtwdev);
}
rtw_write32_mask(rtwdev, REG_TXPSEL, 0xf0, 0x1);
rtw_write32_mask(rtwdev, REG_CCK_RX, 0x0f000000, 0x1);
basic_rates = BIT(DESC_RATE1M) | BIT(DESC_RATE2M) |
BIT(DESC_RATE5_5M) | BIT(DESC_RATE11M) |
BIT(DESC_RATE6M) | BIT(DESC_RATE12M) |
BIT(DESC_RATE24M);
rtw_write32_mask(rtwdev, REG_RRSR, 0xfffff, basic_rates);
rtw_write8_clr(rtwdev, REG_CCK_CHECK, BIT_CHECK_CCK_EN);
} else { /* RTW_BAND_5G */
if (chip->id == RTW_CHIP_TYPE_8821A)
rtw8821a_phy_set_rfe_reg_5g(rtwdev);
rtw_write8_set(rtwdev, REG_CCK_CHECK, BIT_CHECK_CCK_EN);
read_poll_timeout_atomic(rtw_read16, reg_41a, (reg_41a & 0x30) == 0x30,
50, 2500, false, rtwdev, REG_TXPKT_EMPTY);
rtw_write32_set(rtwdev, REG_RXPSEL, BIT_RX_PSEL_RST);
if (chip->id == RTW_CHIP_TYPE_8821A) {
rtw_write32_mask(rtwdev, REG_TXSCALE_A, 0xf00, 1);
} else {
rtw_write32_mask(rtwdev, REG_BWINDICATION, 0x3, 0x2);
rtw_write32_mask(rtwdev, REG_PDMFTH, GENMASK(17, 13), 0x15);
rtw_write32_mask(rtwdev, REG_PDMFTH, GENMASK(3, 1), 0x04);
rtw_write32_mask(rtwdev, REG_CCASEL, 0x3, 1);
rtw8812a_phy_set_rfe_reg_5g(rtwdev);
}
rtw_write32_mask(rtwdev, REG_TXPSEL, 0xf0, 0);
rtw_write32_mask(rtwdev, REG_CCK_RX, 0x0f000000, 0xf);
basic_rates = BIT(DESC_RATE6M) | BIT(DESC_RATE12M) |
BIT(DESC_RATE24M);
rtw_write32_mask(rtwdev, REG_RRSR, 0xfffff, basic_rates);