[migen][sim] How to import verilog source into migen design file ?

[henrydang80]

Hello,

I'm trying to import verilog code into migen design as below:

First I created shifter.v:

module shifter(
	input  sck_i,
	input  sdi_i,
	output sdo_o,
	input  csn_i,
);

reg [7:0] reg_i = 8'd0;
reg [7:0] cnt = 8'd0;

always @(negedge csn_i) begin
	cnt <= 1'd0;
end

always @(negedge sck_i) begin
	if ((cnt < 4'd8)) begin
		reg_i <= (reg_i <<< 1'd1);
	end
end

always @(posedge sck) begin
	if ((cnt < 4'd8)) begin
		cnt <= (cnt + 1'd1);
	end
	reg_i[0] <= sdi_i;
end

endmodule

Then I created module.py:

import os
from migen import *
from migen.fhdl import verilog
from random import randrange

class Serial(Module):
    def __init__(self, sck_i, sdi_i, sdo_o, csn_i):
        
        self.specials += [
            Instance("shifter",
                        i_sck_i = sck_i,
                        i_sdi_i = sdi_i,
                        o_sdo_o = sdo_o,
                        i_csn_i = csn_i,
                    )
        ]

#Simulation and verilog conversion
sck_i  = Signal()
sdi_i  = Signal()
sdo_o  = Signal()
csn_i  = Signal()
        
def generator(dut):
    for sck_i in range(500):
        yield sdi_i.eq(randrange(2))
        yield        
        
if __name__ == "__main__":
    sr = Serial(sck_i, sdi_i, sdo_o, csn_i)
    #print(verilog.convert(Serial(sck_i, sdi_i, sdo_o, csn_i), ios = {sck_i, sdi_i, sdo_o, csn_i}))
    run_simulation(sr, generator(sr), clocks={"sys": 10}, vcd_name="Serial.vcd") 

I don't know how to inport verilog into it, would you please how to do it ?

Thank you.

[TomKeddie]

@henrydang80 foboot (https://github.com/im-tomu/foboot/blob/master/hw/foboot-bitstream.py#L507) has an example where a verilog spi module is imported, take a look at that and see if it helps you.