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qsystem_tb.csv
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qsystem_tb.csv
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# system info qsystem_tb on 2015.04.26.21:08:12
system_info:
name,value
DEVICE,10M08SAE144C8GES
DEVICE_FAMILY,MAX 10
GENERATION_ID,1430078862
#
#
# Files generated for qsystem_tb on 2015.04.26.21:08:12
files:
filepath,kind,attributes,module,is_top
qsystem/testbench/qsystem_tb/simulation/qsystem_tb.v,VERILOG,,qsystem_tb,true
qsystem/testbench/qsystem_tb/simulation/submodules/qsystem.v,VERILOG,,qsystem,false
qsystem/testbench/qsystem_tb/simulation/submodules/verbosity_pkg.sv,SYSTEM_VERILOG, COMMON_SYSTEMVERILOG_PACKAGE=avalon_vip_verbosity_pkg,altera_conduit_bfm,false
qsystem/testbench/qsystem_tb/simulation/submodules/altera_conduit_bfm.sv,SYSTEM_VERILOG,,altera_conduit_bfm,false
qsystem/testbench/qsystem_tb/simulation/submodules/verbosity_pkg.sv,SYSTEM_VERILOG, COMMON_SYSTEMVERILOG_PACKAGE=avalon_vip_verbosity_pkg,altera_conduit_bfm_0002,false
qsystem/testbench/qsystem_tb/simulation/submodules/altera_conduit_bfm_0002.sv,SYSTEM_VERILOG,,altera_conduit_bfm_0002,false
qsystem/testbench/qsystem_tb/simulation/submodules/verbosity_pkg.sv,SYSTEM_VERILOG, COMMON_SYSTEMVERILOG_PACKAGE=avalon_vip_verbosity_pkg,altera_conduit_bfm_0003,false
qsystem/testbench/qsystem_tb/simulation/submodules/altera_conduit_bfm_0003.sv,SYSTEM_VERILOG,,altera_conduit_bfm_0003,false
qsystem/testbench/qsystem_tb/simulation/submodules/verbosity_pkg.sv,SYSTEM_VERILOG, COMMON_SYSTEMVERILOG_PACKAGE=avalon_vip_verbosity_pkg,altera_conduit_bfm_0004,false
qsystem/testbench/qsystem_tb/simulation/submodules/altera_conduit_bfm_0004.sv,SYSTEM_VERILOG,,altera_conduit_bfm_0004,false
qsystem/testbench/qsystem_tb/simulation/submodules/verbosity_pkg.sv,SYSTEM_VERILOG, COMMON_SYSTEMVERILOG_PACKAGE=avalon_vip_verbosity_pkg,altera_avalon_clock_source,false
qsystem/testbench/qsystem_tb/simulation/submodules/altera_avalon_clock_source.sv,SYSTEM_VERILOG,,altera_avalon_clock_source,false
qsystem/testbench/qsystem_tb/simulation/submodules/verbosity_pkg.sv,SYSTEM_VERILOG, COMMON_SYSTEMVERILOG_PACKAGE=avalon_vip_verbosity_pkg,altera_avalon_reset_source,false
qsystem/testbench/qsystem_tb/simulation/submodules/altera_avalon_reset_source.sv,SYSTEM_VERILOG,,altera_avalon_reset_source,false
qsystem/testbench/qsystem_tb/simulation/submodules/PWM.v,VERILOG,,Servo,false
qsystem/testbench/qsystem_tb/simulation/submodules/QEI.v,VERILOG,,QEI,false
qsystem/testbench/qsystem_tb/simulation/submodules/ST_ch_data_demux_and_swap.v,VERILOG,,ST_ch_data_demux_and_swap,false
qsystem/testbench/qsystem_tb/simulation/submodules/ST_channel_prefixer.v,VERILOG,,ST_channel_prefixer,false
qsystem/testbench/qsystem_tb/simulation/submodules/Triggered_ADC_Sequencer.v,VERILOG,,Triggered_ADC_Sequencer,false
qsystem/testbench/qsystem_tb/simulation/submodules/qsystem_altpll_0.vo,VERILOG,,qsystem_altpll_0,false
qsystem/testbench/qsystem_tb/simulation/submodules/qsystem_demultiplexer_0.sv,SYSTEM_VERILOG,,qsystem_demultiplexer_0,false
qsystem/testbench/qsystem_tb/simulation/submodules/qsystem_jtag_uart_0.v,VERILOG,,qsystem_jtag_uart_0,false
qsystem/testbench/qsystem_tb/simulation/submodules/qsystem_modular_adc_0.v,VERILOG,,qsystem_modular_adc_0,false
qsystem/testbench/qsystem_tb/simulation/submodules/qsystem_multiplexer_0.sv,SYSTEM_VERILOG,,qsystem_multiplexer_0,false
qsystem/testbench/qsystem_tb/simulation/submodules/qsystem_nios2_qsys_0.v,VERILOG,,qsystem_nios2_qsys_0,false
qsystem/testbench/qsystem_tb/simulation/submodules/qsystem_onchip_memory2_0.v,VERILOG,,qsystem_onchip_memory2_0,false
qsystem/testbench/qsystem_tb/simulation/submodules/altera_avalon_sc_fifo.v,VERILOG,,altera_avalon_sc_fifo,false
qsystem/testbench/qsystem_tb/simulation/submodules/qsystem_sysid_qsys_0.vo,VERILOG,,qsystem_sysid_qsys_0,false
qsystem/testbench/qsystem_tb/simulation/submodules/qsystem_mm_interconnect_0.v,VERILOG,,qsystem_mm_interconnect_0,false
qsystem/testbench/qsystem_tb/simulation/submodules/qsystem_irq_mapper.sv,SYSTEM_VERILOG,,qsystem_irq_mapper,false
qsystem/testbench/qsystem_tb/simulation/submodules/qsystem_irq_mapper_001.sv,SYSTEM_VERILOG,,qsystem_irq_mapper_001,false
qsystem/testbench/qsystem_tb/simulation/submodules/qsystem_avalon_st_adapter.v,VERILOG,,qsystem_avalon_st_adapter,false
qsystem/testbench/qsystem_tb/simulation/submodules/qsystem_avalon_st_adapter_001.v,VERILOG,,qsystem_avalon_st_adapter_001,false
qsystem/testbench/qsystem_tb/simulation/submodules/altera_reset_controller.v,VERILOG,,altera_reset_controller,false
qsystem/testbench/qsystem_tb/simulation/submodules/altera_reset_synchronizer.v,VERILOG,,altera_reset_controller,false
qsystem/testbench/qsystem_tb/simulation/submodules/altera_reset_controller.sdc,SDC,,altera_reset_controller,false
qsystem/testbench/qsystem_tb/simulation/submodules/altera_modular_adc_control.v,VERILOG,,altera_modular_adc_control,false
qsystem/testbench/qsystem_tb/simulation/submodules/altera_modular_adc_control_fsm.v,VERILOG,,altera_modular_adc_control,false
qsystem/testbench/qsystem_tb/simulation/submodules/chsel_code_converter_sw_to_hw.v,VERILOG,,altera_modular_adc_control,false
qsystem/testbench/qsystem_tb/simulation/submodules/fiftyfivenm_adcblock_primitive_wrapper.v,VERILOG,,altera_modular_adc_control,false
qsystem/testbench/qsystem_tb/simulation/submodules/fiftyfivenm_adcblock_top_wrapper.v,VERILOG,,altera_modular_adc_control,false
qsystem/testbench/qsystem_tb/simulation/submodules/qsystem_nios2_qsys_0_cpu.sdc,SDC,,qsystem_nios2_qsys_0_cpu,false
qsystem/testbench/qsystem_tb/simulation/submodules/qsystem_nios2_qsys_0_cpu.v,VERILOG,,qsystem_nios2_qsys_0_cpu,false
qsystem/testbench/qsystem_tb/simulation/submodules/qsystem_nios2_qsys_0_cpu_debug_slave_sysclk.v,VERILOG,,qsystem_nios2_qsys_0_cpu,false
qsystem/testbench/qsystem_tb/simulation/submodules/qsystem_nios2_qsys_0_cpu_debug_slave_tck.v,VERILOG,,qsystem_nios2_qsys_0_cpu,false
qsystem/testbench/qsystem_tb/simulation/submodules/qsystem_nios2_qsys_0_cpu_debug_slave_wrapper.v,VERILOG,,qsystem_nios2_qsys_0_cpu,false
qsystem/testbench/qsystem_tb/simulation/submodules/qsystem_nios2_qsys_0_cpu_nios2_waves.do,OTHER,,qsystem_nios2_qsys_0_cpu,false
qsystem/testbench/qsystem_tb/simulation/submodules/qsystem_nios2_qsys_0_cpu_ociram_default_contents.dat,DAT,,qsystem_nios2_qsys_0_cpu,false
qsystem/testbench/qsystem_tb/simulation/submodules/qsystem_nios2_qsys_0_cpu_ociram_default_contents.hex,HEX,,qsystem_nios2_qsys_0_cpu,false
qsystem/testbench/qsystem_tb/simulation/submodules/qsystem_nios2_qsys_0_cpu_ociram_default_contents.mif,MIF,,qsystem_nios2_qsys_0_cpu,false
qsystem/testbench/qsystem_tb/simulation/submodules/qsystem_nios2_qsys_0_cpu_oci_test_bench.v,VERILOG,,qsystem_nios2_qsys_0_cpu,false
qsystem/testbench/qsystem_tb/simulation/submodules/qsystem_nios2_qsys_0_cpu_rf_ram_a.dat,DAT,,qsystem_nios2_qsys_0_cpu,false
qsystem/testbench/qsystem_tb/simulation/submodules/qsystem_nios2_qsys_0_cpu_rf_ram_a.hex,HEX,,qsystem_nios2_qsys_0_cpu,false
qsystem/testbench/qsystem_tb/simulation/submodules/qsystem_nios2_qsys_0_cpu_rf_ram_a.mif,MIF,,qsystem_nios2_qsys_0_cpu,false
qsystem/testbench/qsystem_tb/simulation/submodules/qsystem_nios2_qsys_0_cpu_rf_ram_b.dat,DAT,,qsystem_nios2_qsys_0_cpu,false
qsystem/testbench/qsystem_tb/simulation/submodules/qsystem_nios2_qsys_0_cpu_rf_ram_b.hex,HEX,,qsystem_nios2_qsys_0_cpu,false
qsystem/testbench/qsystem_tb/simulation/submodules/qsystem_nios2_qsys_0_cpu_rf_ram_b.mif,MIF,,qsystem_nios2_qsys_0_cpu,false
qsystem/testbench/qsystem_tb/simulation/submodules/qsystem_nios2_qsys_0_cpu_test_bench.v,VERILOG,,qsystem_nios2_qsys_0_cpu,false
qsystem/testbench/qsystem_tb/simulation/submodules/altera_merlin_master_translator.sv,SYSTEM_VERILOG,,altera_merlin_master_translator,false
qsystem/testbench/qsystem_tb/simulation/submodules/altera_merlin_slave_translator.sv,SYSTEM_VERILOG,,altera_merlin_slave_translator,false
qsystem/testbench/qsystem_tb/simulation/submodules/altera_merlin_master_agent.sv,SYSTEM_VERILOG,,altera_merlin_master_agent,false
qsystem/testbench/qsystem_tb/simulation/submodules/altera_merlin_slave_agent.sv,SYSTEM_VERILOG,,altera_merlin_slave_agent,false
qsystem/testbench/qsystem_tb/simulation/submodules/altera_merlin_burst_uncompressor.sv,SYSTEM_VERILOG,,altera_merlin_slave_agent,false
qsystem/testbench/qsystem_tb/simulation/submodules/qsystem_mm_interconnect_0_router.sv,SYSTEM_VERILOG,,qsystem_mm_interconnect_0_router,false
qsystem/testbench/qsystem_tb/simulation/submodules/qsystem_mm_interconnect_0_router_001.sv,SYSTEM_VERILOG,,qsystem_mm_interconnect_0_router_001,false
qsystem/testbench/qsystem_tb/simulation/submodules/qsystem_mm_interconnect_0_router_002.sv,SYSTEM_VERILOG,,qsystem_mm_interconnect_0_router_002,false
qsystem/testbench/qsystem_tb/simulation/submodules/qsystem_mm_interconnect_0_router_007.sv,SYSTEM_VERILOG,,qsystem_mm_interconnect_0_router_007,false
qsystem/testbench/qsystem_tb/simulation/submodules/qsystem_mm_interconnect_0_cmd_demux.sv,SYSTEM_VERILOG,,qsystem_mm_interconnect_0_cmd_demux,false
qsystem/testbench/qsystem_tb/simulation/submodules/qsystem_mm_interconnect_0_cmd_demux_001.sv,SYSTEM_VERILOG,,qsystem_mm_interconnect_0_cmd_demux_001,false
qsystem/testbench/qsystem_tb/simulation/submodules/altera_merlin_arbitrator.sv,SYSTEM_VERILOG,,qsystem_mm_interconnect_0_cmd_mux,false
qsystem/testbench/qsystem_tb/simulation/submodules/qsystem_mm_interconnect_0_cmd_mux.sv,SYSTEM_VERILOG,,qsystem_mm_interconnect_0_cmd_mux,false
qsystem/testbench/qsystem_tb/simulation/submodules/altera_merlin_arbitrator.sv,SYSTEM_VERILOG,,qsystem_mm_interconnect_0_cmd_mux_005,false
qsystem/testbench/qsystem_tb/simulation/submodules/qsystem_mm_interconnect_0_cmd_mux_005.sv,SYSTEM_VERILOG,,qsystem_mm_interconnect_0_cmd_mux_005,false
qsystem/testbench/qsystem_tb/simulation/submodules/qsystem_mm_interconnect_0_rsp_demux.sv,SYSTEM_VERILOG,,qsystem_mm_interconnect_0_rsp_demux,false
qsystem/testbench/qsystem_tb/simulation/submodules/altera_merlin_arbitrator.sv,SYSTEM_VERILOG,,qsystem_mm_interconnect_0_rsp_mux,false
qsystem/testbench/qsystem_tb/simulation/submodules/qsystem_mm_interconnect_0_rsp_mux.sv,SYSTEM_VERILOG,,qsystem_mm_interconnect_0_rsp_mux,false
qsystem/testbench/qsystem_tb/simulation/submodules/altera_merlin_arbitrator.sv,SYSTEM_VERILOG,,qsystem_mm_interconnect_0_rsp_mux_001,false
qsystem/testbench/qsystem_tb/simulation/submodules/qsystem_mm_interconnect_0_rsp_mux_001.sv,SYSTEM_VERILOG,,qsystem_mm_interconnect_0_rsp_mux_001,false
qsystem/testbench/qsystem_tb/simulation/submodules/qsystem_avalon_st_adapter_timing_adapter_0.sv,SYSTEM_VERILOG,,qsystem_avalon_st_adapter_timing_adapter_0,false
qsystem/testbench/qsystem_tb/simulation/submodules/qsystem_avalon_st_adapter_001_timing_adapter_0.sv,SYSTEM_VERILOG,,qsystem_avalon_st_adapter_001_timing_adapter_0,false
#
# Map from instance-path to kind of module
instances:
instancePath,module
qsystem_tb.qsystem_inst,qsystem
qsystem_tb.qsystem_inst.PWM_0,Servo
qsystem_tb.qsystem_inst.QEI_0,QEI
qsystem_tb.qsystem_inst.ST_ch_data_demux_and_swap_0,ST_ch_data_demux_and_swap
qsystem_tb.qsystem_inst.ST_channel_prefixer_0,ST_channel_prefixer
qsystem_tb.qsystem_inst.Triggered_ADC_Sequencer_0,Triggered_ADC_Sequencer
qsystem_tb.qsystem_inst.altpll_0,qsystem_altpll_0
qsystem_tb.qsystem_inst.demultiplexer_0,qsystem_demultiplexer_0
qsystem_tb.qsystem_inst.jtag_uart_0,qsystem_jtag_uart_0
qsystem_tb.qsystem_inst.modular_adc_0,qsystem_modular_adc_0
qsystem_tb.qsystem_inst.modular_adc_0.control_internal,altera_modular_adc_control
qsystem_tb.qsystem_inst.multiplexer_0,qsystem_multiplexer_0
qsystem_tb.qsystem_inst.nios2_qsys_0,qsystem_nios2_qsys_0
qsystem_tb.qsystem_inst.nios2_qsys_0.cpu,qsystem_nios2_qsys_0_cpu
qsystem_tb.qsystem_inst.onchip_memory2_0,qsystem_onchip_memory2_0
qsystem_tb.qsystem_inst.sc_fifo_0,altera_avalon_sc_fifo
qsystem_tb.qsystem_inst.sysid_qsys_0,qsystem_sysid_qsys_0
qsystem_tb.qsystem_inst.mm_interconnect_0,qsystem_mm_interconnect_0
qsystem_tb.qsystem_inst.mm_interconnect_0.nios2_qsys_0_data_master_translator,altera_merlin_master_translator
qsystem_tb.qsystem_inst.mm_interconnect_0.nios2_qsys_0_instruction_master_translator,altera_merlin_master_translator
qsystem_tb.qsystem_inst.mm_interconnect_0.jtag_uart_0_avalon_jtag_slave_translator,altera_merlin_slave_translator
qsystem_tb.qsystem_inst.mm_interconnect_0.Triggered_ADC_Sequencer_0_avalon_slave_translator,altera_merlin_slave_translator
qsystem_tb.qsystem_inst.mm_interconnect_0.PWM_0_avalon_slave_translator,altera_merlin_slave_translator
qsystem_tb.qsystem_inst.mm_interconnect_0.QEI_0_avalon_slave_translator,altera_merlin_slave_translator
qsystem_tb.qsystem_inst.mm_interconnect_0.sysid_qsys_0_control_slave_translator,altera_merlin_slave_translator
qsystem_tb.qsystem_inst.mm_interconnect_0.nios2_qsys_0_debug_mem_slave_translator,altera_merlin_slave_translator
qsystem_tb.qsystem_inst.mm_interconnect_0.onchip_memory2_0_s1_translator,altera_merlin_slave_translator
qsystem_tb.qsystem_inst.mm_interconnect_0.nios2_qsys_0_data_master_agent,altera_merlin_master_agent
qsystem_tb.qsystem_inst.mm_interconnect_0.nios2_qsys_0_instruction_master_agent,altera_merlin_master_agent
qsystem_tb.qsystem_inst.mm_interconnect_0.jtag_uart_0_avalon_jtag_slave_agent,altera_merlin_slave_agent
qsystem_tb.qsystem_inst.mm_interconnect_0.Triggered_ADC_Sequencer_0_avalon_slave_agent,altera_merlin_slave_agent
qsystem_tb.qsystem_inst.mm_interconnect_0.PWM_0_avalon_slave_agent,altera_merlin_slave_agent
qsystem_tb.qsystem_inst.mm_interconnect_0.QEI_0_avalon_slave_agent,altera_merlin_slave_agent
qsystem_tb.qsystem_inst.mm_interconnect_0.sysid_qsys_0_control_slave_agent,altera_merlin_slave_agent
qsystem_tb.qsystem_inst.mm_interconnect_0.nios2_qsys_0_debug_mem_slave_agent,altera_merlin_slave_agent
qsystem_tb.qsystem_inst.mm_interconnect_0.onchip_memory2_0_s1_agent,altera_merlin_slave_agent
qsystem_tb.qsystem_inst.mm_interconnect_0.jtag_uart_0_avalon_jtag_slave_agent_rsp_fifo,altera_avalon_sc_fifo
qsystem_tb.qsystem_inst.mm_interconnect_0.Triggered_ADC_Sequencer_0_avalon_slave_agent_rsp_fifo,altera_avalon_sc_fifo
qsystem_tb.qsystem_inst.mm_interconnect_0.PWM_0_avalon_slave_agent_rsp_fifo,altera_avalon_sc_fifo
qsystem_tb.qsystem_inst.mm_interconnect_0.QEI_0_avalon_slave_agent_rsp_fifo,altera_avalon_sc_fifo
qsystem_tb.qsystem_inst.mm_interconnect_0.sysid_qsys_0_control_slave_agent_rsp_fifo,altera_avalon_sc_fifo
qsystem_tb.qsystem_inst.mm_interconnect_0.nios2_qsys_0_debug_mem_slave_agent_rsp_fifo,altera_avalon_sc_fifo
qsystem_tb.qsystem_inst.mm_interconnect_0.onchip_memory2_0_s1_agent_rsp_fifo,altera_avalon_sc_fifo
qsystem_tb.qsystem_inst.mm_interconnect_0.router,qsystem_mm_interconnect_0_router
qsystem_tb.qsystem_inst.mm_interconnect_0.router_001,qsystem_mm_interconnect_0_router_001
qsystem_tb.qsystem_inst.mm_interconnect_0.router_002,qsystem_mm_interconnect_0_router_002
qsystem_tb.qsystem_inst.mm_interconnect_0.router_003,qsystem_mm_interconnect_0_router_002
qsystem_tb.qsystem_inst.mm_interconnect_0.router_004,qsystem_mm_interconnect_0_router_002
qsystem_tb.qsystem_inst.mm_interconnect_0.router_005,qsystem_mm_interconnect_0_router_002
qsystem_tb.qsystem_inst.mm_interconnect_0.router_006,qsystem_mm_interconnect_0_router_002
qsystem_tb.qsystem_inst.mm_interconnect_0.router_007,qsystem_mm_interconnect_0_router_007
qsystem_tb.qsystem_inst.mm_interconnect_0.router_008,qsystem_mm_interconnect_0_router_007
qsystem_tb.qsystem_inst.mm_interconnect_0.cmd_demux,qsystem_mm_interconnect_0_cmd_demux
qsystem_tb.qsystem_inst.mm_interconnect_0.cmd_demux_001,qsystem_mm_interconnect_0_cmd_demux_001
qsystem_tb.qsystem_inst.mm_interconnect_0.rsp_demux_005,qsystem_mm_interconnect_0_cmd_demux_001
qsystem_tb.qsystem_inst.mm_interconnect_0.rsp_demux_006,qsystem_mm_interconnect_0_cmd_demux_001
qsystem_tb.qsystem_inst.mm_interconnect_0.cmd_mux,qsystem_mm_interconnect_0_cmd_mux
qsystem_tb.qsystem_inst.mm_interconnect_0.cmd_mux_001,qsystem_mm_interconnect_0_cmd_mux
qsystem_tb.qsystem_inst.mm_interconnect_0.cmd_mux_002,qsystem_mm_interconnect_0_cmd_mux
qsystem_tb.qsystem_inst.mm_interconnect_0.cmd_mux_003,qsystem_mm_interconnect_0_cmd_mux
qsystem_tb.qsystem_inst.mm_interconnect_0.cmd_mux_004,qsystem_mm_interconnect_0_cmd_mux
qsystem_tb.qsystem_inst.mm_interconnect_0.cmd_mux_005,qsystem_mm_interconnect_0_cmd_mux_005
qsystem_tb.qsystem_inst.mm_interconnect_0.cmd_mux_006,qsystem_mm_interconnect_0_cmd_mux_005
qsystem_tb.qsystem_inst.mm_interconnect_0.rsp_demux,qsystem_mm_interconnect_0_rsp_demux
qsystem_tb.qsystem_inst.mm_interconnect_0.rsp_demux_001,qsystem_mm_interconnect_0_rsp_demux
qsystem_tb.qsystem_inst.mm_interconnect_0.rsp_demux_002,qsystem_mm_interconnect_0_rsp_demux
qsystem_tb.qsystem_inst.mm_interconnect_0.rsp_demux_003,qsystem_mm_interconnect_0_rsp_demux
qsystem_tb.qsystem_inst.mm_interconnect_0.rsp_demux_004,qsystem_mm_interconnect_0_rsp_demux
qsystem_tb.qsystem_inst.mm_interconnect_0.rsp_mux,qsystem_mm_interconnect_0_rsp_mux
qsystem_tb.qsystem_inst.mm_interconnect_0.rsp_mux_001,qsystem_mm_interconnect_0_rsp_mux_001
qsystem_tb.qsystem_inst.irq_mapper,qsystem_irq_mapper
qsystem_tb.qsystem_inst.irq_mapper_001,qsystem_irq_mapper_001
qsystem_tb.qsystem_inst.avalon_st_adapter,qsystem_avalon_st_adapter
qsystem_tb.qsystem_inst.avalon_st_adapter.timing_adapter_0,qsystem_avalon_st_adapter_timing_adapter_0
qsystem_tb.qsystem_inst.avalon_st_adapter_001,qsystem_avalon_st_adapter_001
qsystem_tb.qsystem_inst.avalon_st_adapter_001.timing_adapter_0,qsystem_avalon_st_adapter_001_timing_adapter_0
qsystem_tb.qsystem_inst.rst_controller,altera_reset_controller
qsystem_tb.qsystem_inst.rst_controller_001,altera_reset_controller
qsystem_tb.qsystem_inst_PWM_0_PWMout_bfm,altera_conduit_bfm
qsystem_tb.qsystem_inst_QEI_0_EncoderIn_bfm,altera_conduit_bfm_0002
qsystem_tb.qsystem_inst_altpll_0_areset_conduit_bfm,altera_conduit_bfm_0003
qsystem_tb.qsystem_inst_altpll_0_locked_conduit_bfm,altera_conduit_bfm_0004
qsystem_tb.qsystem_inst_altpll_0_phasedone_conduit_bfm,altera_conduit_bfm_0004
qsystem_tb.qsystem_inst_clk_bfm,altera_avalon_clock_source
qsystem_tb.qsystem_inst_reset_bfm,altera_avalon_reset_source