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Copy pathsystem_processing_system7_0_wrapper.ncf
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system_processing_system7_0_wrapper.ncf
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############################################################################
##
## Xilinx, Inc. 2006 www.xilinx.com
############################################################################
## File name : D:/HDL/FndtnISEWork/Zynq-7000/ZYBO/ZYBO_CDC_VGA/system/implementation/processing_system7_0_wrapper/processing_system7_0_wrapper.ucf
##
## Details : Constraints file
## FPGA family: zynq
## FPGA: xc7z010clg400-1
## Device Size:
## Package:
## Speedgrade: -1
##
##Note: This is a generated file. Configuration settings should not be edited
##
############################################################################
############################################################################
############################################################################
# Clock constraints #
############################################################################
NET FCLK_CLK0 TNM_NET = clk_fpga_0;
TIMESPEC TS_clk_fpga_0 = PERIOD clk_fpga_0 100000 kHz;
############################################################################
# I/O STANDARDS and Location Constraints #
############################################################################
NET "MIO[53]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "slow" | LOC = "C11" ; # Enet 0 / mdio / MIO[53]
NET "MIO[52]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "slow" | LOC = "C10" ; # Enet 0 / mdc / MIO[52]
NET "MIO[51]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "slow" | LOC = "B9" ; # GPIO / gpio[51] / MIO[51]
NET "MIO[50]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "slow" | LOC = "B13" ; # GPIO / gpio[50] / MIO[50]
NET "MIO[49]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "slow" | LOC = "C12" ; # UART 1 / rx / MIO[49]
NET "MIO[48]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "slow" | LOC = "B12" ; # UART 1 / tx / MIO[48]
NET "MIO[47]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "slow" | LOC = "B14" ; # SD 0 / cd / MIO[47]
NET "MIO[46]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "slow" | LOC = "D16" ; # USB 0 / reset / MIO[46]
NET "MIO[45]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "fast" | LOC = "B15" ; # SD 0 / data[3] / MIO[45]
NET "MIO[44]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "fast" | LOC = "F13" ; # SD 0 / data[2] / MIO[44]
NET "MIO[43]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "fast" | LOC = "A9" ; # SD 0 / data[1] / MIO[43]
NET "MIO[42]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "fast" | LOC = "E12" ; # SD 0 / data[0] / MIO[42]
NET "MIO[41]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "fast" | LOC = "C17" ; # SD 0 / cmd / MIO[41]
NET "MIO[40]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "fast" | LOC = "D14" ; # SD 0 / clk / MIO[40]
NET "MIO[39]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "fast" | LOC = "C18" ; # USB 0 / data[7] / MIO[39]
NET "MIO[38]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "fast" | LOC = "E13" ; # USB 0 / data[6] / MIO[38]
NET "MIO[37]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "fast" | LOC = "A10" ; # USB 0 / data[5] / MIO[37]
NET "MIO[36]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "fast" | LOC = "A11" ; # USB 0 / clk / MIO[36]
NET "MIO[35]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "fast" | LOC = "F12" ; # USB 0 / data[3] / MIO[35]
NET "MIO[34]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "fast" | LOC = "A12" ; # USB 0 / data[2] / MIO[34]
NET "MIO[33]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "fast" | LOC = "D15" ; # USB 0 / data[1] / MIO[33]
NET "MIO[32]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "fast" | LOC = "A14" ; # USB 0 / data[0] / MIO[32]
NET "MIO[31]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "fast" | LOC = "E16" ; # USB 0 / nxt / MIO[31]
NET "MIO[30]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "fast" | LOC = "C15" ; # USB 0 / stp / MIO[30]
NET "MIO[29]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "fast" | LOC = "C13" ; # USB 0 / dir / MIO[29]
NET "MIO[28]" IOSTANDARD = LVCMOS18 | DRIVE = "8" | SLEW = "fast" | LOC = "C16" ; # USB 0 / data[4] / MIO[28]
NET "MIO[27]" IOSTANDARD = HSTL_I_18 | SLEW = "fast" | LOC = "D13" ; # Enet 0 / rx_ctl / MIO[27]
NET "MIO[26]" IOSTANDARD = HSTL_I_18 | SLEW = "fast" | LOC = "A15" ; # Enet 0 / rxd[3] / MIO[26]
NET "MIO[25]" IOSTANDARD = HSTL_I_18 | SLEW = "fast" | LOC = "F15" ; # Enet 0 / rxd[2] / MIO[25]
NET "MIO[24]" IOSTANDARD = HSTL_I_18 | SLEW = "fast" | LOC = "A16" ; # Enet 0 / rxd[1] / MIO[24]
NET "MIO[23]" IOSTANDARD = HSTL_I_18 | SLEW = "fast" | LOC = "D11" ; # Enet 0 / rxd[0] / MIO[23]
NET "MIO[22]" IOSTANDARD = HSTL_I_18 | SLEW = "fast" | LOC = "B17" ; # Enet 0 / rx_clk / MIO[22]
NET "MIO[21]" IOSTANDARD = HSTL_I_18 | SLEW = "fast" | LOC = "F14" ; # Enet 0 / tx_ctl / MIO[21]
NET "MIO[20]" IOSTANDARD = HSTL_I_18 | SLEW = "fast" | LOC = "A17" ; # Enet 0 / txd[3] / MIO[20]
NET "MIO[19]" IOSTANDARD = HSTL_I_18 | SLEW = "fast" | LOC = "D10" ; # Enet 0 / txd[2] / MIO[19]
NET "MIO[18]" IOSTANDARD = HSTL_I_18 | SLEW = "fast" | LOC = "B18" ; # Enet 0 / txd[1] / MIO[18]
NET "MIO[17]" IOSTANDARD = HSTL_I_18 | SLEW = "fast" | LOC = "E14" ; # Enet 0 / txd[0] / MIO[17]
NET "MIO[16]" IOSTANDARD = HSTL_I_18 | SLEW = "fast" | LOC = "A19" ; # Enet 0 / tx_clk / MIO[16]
NET "MIO[15]" IOSTANDARD = LVCMOS33 | DRIVE = "8" | SLEW = "slow" | LOC = "C8" ; # GPIO / gpio[15] / MIO[15]
NET "MIO[14]" IOSTANDARD = LVCMOS33 | DRIVE = "8" | SLEW = "slow" | LOC = "C5" ; # GPIO / gpio[14] / MIO[14]
NET "MIO[13]" IOSTANDARD = LVCMOS33 | DRIVE = "8" | SLEW = "slow" | LOC = "E8" ; # GPIO / gpio[13] / MIO[13]
NET "MIO[12]" IOSTANDARD = LVCMOS33 | DRIVE = "8" | SLEW = "slow" | LOC = "D9" ; # GPIO / gpio[12] / MIO[12]
NET "MIO[11]" IOSTANDARD = LVCMOS33 | DRIVE = "8" | SLEW = "slow" | LOC = "C6" ; # GPIO / gpio[11] / MIO[11]
NET "MIO[10]" IOSTANDARD = LVCMOS33 | DRIVE = "8" | SLEW = "slow" | LOC = "E9" ; # GPIO / gpio[10] / MIO[10]
NET "MIO[9]" IOSTANDARD = LVCMOS33 | DRIVE = "8" | SLEW = "slow" | LOC = "B5" ; # GPIO / gpio[9] / MIO[9]
NET "MIO[8]" IOSTANDARD = LVCMOS33 | DRIVE = "8" | SLEW = "fast" | LOC = "D5" ; # Quad SPI Flash / qspi_fbclk / MIO[8]
NET "MIO[7]" IOSTANDARD = LVCMOS33 | DRIVE = "8" | SLEW = "slow" | LOC = "D8" ; # GPIO / gpio[7] / MIO[7]
NET "MIO[6]" IOSTANDARD = LVCMOS33 | DRIVE = "8" | SLEW = "fast" | LOC = "A5" ; # Quad SPI Flash / qspi0_sclk / MIO[6]
NET "MIO[5]" IOSTANDARD = LVCMOS33 | DRIVE = "8" | SLEW = "fast" | LOC = "A6" ; # Quad SPI Flash / qspi0_io[3] / MIO[5]
NET "MIO[4]" IOSTANDARD = LVCMOS33 | DRIVE = "8" | SLEW = "fast" | LOC = "B7" ; # Quad SPI Flash / qspi0_io[2] / MIO[4]
NET "MIO[3]" IOSTANDARD = LVCMOS33 | DRIVE = "8" | SLEW = "fast" | LOC = "D6" ; # Quad SPI Flash / qspi0_io[1] / MIO[3]
NET "MIO[2]" IOSTANDARD = LVCMOS33 | DRIVE = "8" | SLEW = "fast" | LOC = "B8" ; # Quad SPI Flash / qspi0_io[0] / MIO[2]
NET "MIO[1]" IOSTANDARD = LVCMOS33 | DRIVE = "8" | SLEW = "fast" | LOC = "A7" ; # Quad SPI Flash / qspi0_ss_b / MIO[1]
NET "MIO[0]" IOSTANDARD = LVCMOS33 | DRIVE = "8" | SLEW = "slow" | LOC = "E6" ; # GPIO / gpio[0] / MIO[0]
NET "DDR_WEB" IOSTANDARD = SSTL15 | SLEW = "SLOW" | LOC = "M5" ;
NET "DDR_VRP" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "H5" ;
NET "DDR_VRN" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "G5" ;
NET "DDR_RAS_n" IOSTANDARD = SSTL15 | SLEW = "SLOW" | LOC = "P4" ;
NET "DDR_ODT" IOSTANDARD = SSTL15 | SLEW = "SLOW" | LOC = "N5" ;
NET "DDR_DRSTB" IOSTANDARD = SSTL15 | SLEW = "FAST" | LOC = "B4" ;
NET "DDR_DQS[3]" IOSTANDARD = DIFF_SSTL15_T_DCI | SLEW = "FAST" | LOC = "W5" ;
NET "DDR_DQS[2]" IOSTANDARD = DIFF_SSTL15_T_DCI | SLEW = "FAST" | LOC = "R2" ;
NET "DDR_DQS[1]" IOSTANDARD = DIFF_SSTL15_T_DCI | SLEW = "FAST" | LOC = "G2" ;
NET "DDR_DQS[0]" IOSTANDARD = DIFF_SSTL15_T_DCI | SLEW = "FAST" | LOC = "C2" ;
NET "DDR_DQS_n[3]" IOSTANDARD = DIFF_SSTL15_T_DCI | SLEW = "FAST" | LOC = "W4" ;
NET "DDR_DQS_n[2]" IOSTANDARD = DIFF_SSTL15_T_DCI | SLEW = "FAST" | LOC = "T2" ;
NET "DDR_DQS_n[1]" IOSTANDARD = DIFF_SSTL15_T_DCI | SLEW = "FAST" | LOC = "F2" ;
NET "DDR_DQS_n[0]" IOSTANDARD = DIFF_SSTL15_T_DCI | SLEW = "FAST" | LOC = "B2" ;
NET "DDR_DQ[9]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "E3" ;
NET "DDR_DQ[8]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "E2" ;
NET "DDR_DQ[7]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "E1" ;
NET "DDR_DQ[6]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "C1" ;
NET "DDR_DQ[5]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "D1" ;
NET "DDR_DQ[4]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "D3" ;
NET "DDR_DQ[3]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "A4" ;
NET "DDR_DQ[31]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "V3" ;
NET "DDR_DQ[30]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "V2" ;
NET "DDR_DQ[2]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "A2" ;
NET "DDR_DQ[29]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "W3" ;
NET "DDR_DQ[28]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "Y2" ;
NET "DDR_DQ[27]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "Y4" ;
NET "DDR_DQ[26]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "W1" ;
NET "DDR_DQ[25]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "Y3" ;
NET "DDR_DQ[24]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "V1" ;
NET "DDR_DQ[23]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "U3" ;
NET "DDR_DQ[22]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "U2" ;
NET "DDR_DQ[21]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "U4" ;
NET "DDR_DQ[20]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "T4" ;
NET "DDR_DQ[1]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "B3" ;
NET "DDR_DQ[19]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "R1" ;
NET "DDR_DQ[18]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "R3" ;
NET "DDR_DQ[17]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "P3" ;
NET "DDR_DQ[16]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "P1" ;
NET "DDR_DQ[15]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "J1" ;
NET "DDR_DQ[14]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "H1" ;
NET "DDR_DQ[13]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "H2" ;
NET "DDR_DQ[12]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "J3" ;
NET "DDR_DQ[11]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "H3" ;
NET "DDR_DQ[10]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "G3" ;
NET "DDR_DQ[0]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "C3" ;
NET "DDR_DM[3]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "Y1" ;
NET "DDR_DM[2]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "T1" ;
NET "DDR_DM[1]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "F1" ;
NET "DDR_DM[0]" IOSTANDARD = SSTL15_T_DCI | SLEW = "FAST" | LOC = "A1" ;
NET "DDR_CS_n" IOSTANDARD = SSTL15 | SLEW = "SLOW" | LOC = "N1" ;
NET "DDR_CKE" IOSTANDARD = SSTL15 | SLEW = "SLOW" | LOC = "N3" ;
NET "DDR_Clk" IOSTANDARD = DIFF_SSTL15 | SLEW = "FAST" | LOC = "L2" ;
NET "DDR_Clk_n" IOSTANDARD = DIFF_SSTL15 | SLEW = "FAST" | LOC = "M2" ;
NET "DDR_CAS_n" IOSTANDARD = SSTL15 | SLEW = "SLOW" | LOC = "P5" ;
NET "DDR_BankAddr[2]" IOSTANDARD = SSTL15 | SLEW = "SLOW" | LOC = "J5" ;
NET "DDR_BankAddr[1]" IOSTANDARD = SSTL15 | SLEW = "SLOW" | LOC = "R4" ;
NET "DDR_BankAddr[0]" IOSTANDARD = SSTL15 | SLEW = "SLOW" | LOC = "L5" ;
NET "DDR_Addr[9]" IOSTANDARD = SSTL15 | SLEW = "SLOW" | LOC = "J4" ;
NET "DDR_Addr[8]" IOSTANDARD = SSTL15 | SLEW = "SLOW" | LOC = "K1" ;
NET "DDR_Addr[7]" IOSTANDARD = SSTL15 | SLEW = "SLOW" | LOC = "K4" ;
NET "DDR_Addr[6]" IOSTANDARD = SSTL15 | SLEW = "SLOW" | LOC = "L4" ;
NET "DDR_Addr[5]" IOSTANDARD = SSTL15 | SLEW = "SLOW" | LOC = "L1" ;
NET "DDR_Addr[4]" IOSTANDARD = SSTL15 | SLEW = "SLOW" | LOC = "M4" ;
NET "DDR_Addr[3]" IOSTANDARD = SSTL15 | SLEW = "SLOW" | LOC = "K3" ;
NET "DDR_Addr[2]" IOSTANDARD = SSTL15 | SLEW = "SLOW" | LOC = "M3" ;
NET "DDR_Addr[1]" IOSTANDARD = SSTL15 | SLEW = "SLOW" | LOC = "K2" ;
NET "DDR_Addr[14]" IOSTANDARD = SSTL15 | SLEW = "SLOW" | LOC = "F4" ;
NET "DDR_Addr[13]" IOSTANDARD = SSTL15 | SLEW = "SLOW" | LOC = "D4" ;
NET "DDR_Addr[12]" IOSTANDARD = SSTL15 | SLEW = "SLOW" | LOC = "E4" ;
NET "DDR_Addr[11]" IOSTANDARD = SSTL15 | SLEW = "SLOW" | LOC = "G4" ;
NET "DDR_Addr[10]" IOSTANDARD = SSTL15 | SLEW = "SLOW" | LOC = "F5" ;
NET "DDR_Addr[0]" IOSTANDARD = SSTL15 | SLEW = "SLOW" | LOC = "N2" ;
NET "PS_PORB" IOSTANDARD = LVCMOS33 | DRIVE = "8" | SLEW = "slow" | LOC = "C7" ;
NET "PS_SRSTB" IOSTANDARD = LVCMOS33 | DRIVE = "8" | SLEW = "slow" | LOC = "B10" ;
NET "PS_CLK" IOSTANDARD = LVCMOS33 | DRIVE = "8" | SLEW = "slow" | LOC = "E7" ;