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system_top.syr
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Release 14.7 - xst P.20131013 (nt64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
--> Parameter TMPDIR set to xst/projnav.tmp
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.24 secs
--> Parameter xsthdpdir set to xst
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.24 secs
--> Reading design: system_top.prj
TABLE OF CONTENTS
1) Synthesis Options Summary
2) HDL Parsing
3) HDL Elaboration
4) HDL Synthesis
4.1) HDL Synthesis Report
5) Advanced HDL Synthesis
5.1) Advanced HDL Synthesis Report
6) Low Level Synthesis
7) Partition Report
8) Design Summary
8.1) Primitive and Black Box Usage
8.2) Device utilization summary
8.3) Partition Resource Summary
8.4) Timing Report
8.4.1) Clock Information
8.4.2) Asynchronous Control Signals Information
8.4.3) Timing Summary
8.4.4) Timing Details
8.4.5) Cross Clock Domains Report
=========================================================================
* Synthesis Options Summary *
=========================================================================
---- Source Parameters
Input File Name : "system_top.prj"
Ignore Synthesis Constraint File : NO
---- Target Parameters
Output File Name : "system_top"
Output Format : NGC
Target Device : xc7z010-1-clg400
---- Source Options
Top Module Name : system_top
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
Safe Implementation : No
FSM Style : LUT
RAM Extraction : Yes
RAM Style : Auto
ROM Extraction : Yes
Shift Register Extraction : YES
ROM Style : Auto
Resource Sharing : YES
Asynchronous To Synchronous : NO
Shift Register Minimum Size : 2
Use DSP Block : Auto
Automatic Register Balancing : No
---- Target Options
LUT Combining : Auto
Reduce Control Sets : Auto
Add IO Buffers : YES
Global Maximum Fanout : 100000
Add Generic Clock Buffer(BUFG) : 32
Register Duplication : YES
Optimize Instantiated Primitives : NO
Use Clock Enable : Auto
Use Synchronous Set : Auto
Use Synchronous Reset : Auto
Pack IO Registers into IOBs : Auto
Equivalent register Removal : YES
---- General Options
Optimization Goal : Speed
Optimization Effort : 1
Power Reduction : NO
Keep Hierarchy : No
Netlist Hierarchy : As_Optimized
RTL Output : Yes
Global Optimization : AllClockNets
Read Cores : YES
Write Timing Constraints : NO
Cross Clock Analysis : NO
Hierarchy Separator : /
Bus Delimiter : <>
Case Specifier : Maintain
Slice Utilization Ratio : 100
BRAM Utilization Ratio : 100
DSP48 Utilization Ratio : 100
Auto BRAM Packing : NO
Slice Utilization Ratio Delta : 5
=========================================================================
=========================================================================
* HDL Parsing *
=========================================================================
Parsing VHDL file "D:/HDL/FndtnISEWork/Zynq-7000/ZYBO/ZYBO_CDC_VGA/system/hdl/system.vhd" into library work
Parsing entity <system>.
Parsing architecture <STRUCTURE> of entity <system>.
Parsing VHDL file "D:\HDL\FndtnISEWork\Zynq-7000\ZYBO\ZYBO_CDC_VGA\system\system_top.vhd" into library work
Parsing entity <system_top>.
Parsing architecture <STRUCTURE> of entity <system_top>.
=========================================================================
* HDL Elaboration *
=========================================================================
Elaborating entity <system_top> (architecture <STRUCTURE>) from library <work>.
Elaborating entity <system> (architecture <>) from library <work>.
=========================================================================
* HDL Synthesis *
=========================================================================
Synthesizing Unit <system_top>.
Related source file is "D:\HDL\FndtnISEWork\Zynq-7000\ZYBO\ZYBO_CDC_VGA\system\system_top.vhd".
Set property "BOX_TYPE = user_black_box" for instance <system_i>.
Summary:
no macro.
Unit <system_top> synthesized.
=========================================================================
HDL Synthesis Report
Found no macro
=========================================================================
=========================================================================
* Advanced HDL Synthesis *
=========================================================================
Reading core <system.ngc>.
Reading core <system_processing_system7_0_wrapper.ngc>.
Reading core <system_axi_interconnect_1_wrapper.ngc>.
Reading core <system_clock_generator_0_wrapper.ngc>.
Reading core <system_cdc_vga_axi_slave_0_wrapper.ngc>.
Reading core <system_clkgen_reset_logic_wrapper.ngc>.
Reading core <system_cdc_reset_logic_wrapper.ngc>.
Loading core <system_processing_system7_0_wrapper> for timing and area information for instance <processing_system7_0>.
Loading core <system_axi_interconnect_1_wrapper> for timing and area information for instance <axi_interconnect_1>.
Loading core <system_clock_generator_0_wrapper> for timing and area information for instance <clock_generator_0>.
Loading core <system_cdc_vga_axi_slave_0_wrapper> for timing and area information for instance <cdc_vga_axi_slave_0>.
Loading core <system_clkgen_reset_logic_wrapper> for timing and area information for instance <clkgen_reset_logic>.
Loading core <system_cdc_reset_logic_wrapper> for timing and area information for instance <cdc_reset_logic>.
Loading core <system> for timing and area information for instance <system_i>.
INFO:Xst:1901 - Instance cdc_vga_axi_slave_0/CDC_inst/char_gen_rom_inst/CHAR_GEN_ROM_INST in unit cdc_vga_axi_slave_0/CDC_inst/char_gen_rom_inst/CHAR_GEN_ROM_INST of type RAMB16_S9 has been replaced by RAMB18E1
=========================================================================
Advanced HDL Synthesis Report
Found no macro
=========================================================================
=========================================================================
* Low Level Synthesis *
=========================================================================
WARNING:Xst:528 - Multi-source in Unit <processing_system7_0> on signal <PS_SRSTB>; this signal is connected to multiple drivers.
Drivers are:
Primary input port <processing_system7_0_PS_SRSTB_pin>
Output port PS7:PSSRSTB of instance <system_i/processing_system7_0/processing_system7_0/PS7_i>
WARNING:Xst:528 - Multi-source in Unit <processing_system7_0> on signal <PS_CLK>; this signal is connected to multiple drivers.
Drivers are:
Primary input port <processing_system7_0_PS_CLK_pin>
Output port PS7:PSCLK of instance <system_i/processing_system7_0/processing_system7_0/PS7_i>
WARNING:Xst:528 - Multi-source in Unit <processing_system7_0> on signal <PS_PORB>; this signal is connected to multiple drivers.
Drivers are:
Primary input port <processing_system7_0_PS_PORB_pin>
Output port PS7:PSPORB of instance <system_i/processing_system7_0/processing_system7_0/PS7_i>
Optimizing unit <system_top> ...
Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block system_top, actual ratio is 0.
INFO:Xst:2260 - The FF/Latch <cdc_vga_axi_slave_0/rdt_cs_FSM_FFd1> in Unit <cdc_vga_axi_slave_0> is equivalent to the following 2 FFs/Latches : <cdc_vga_axi_slave_0/rdt_cs_FSM_FFd1_1> <cdc_vga_axi_slave_0/rdt_cs_FSM_FFd1_2>
INFO:Xst:2260 - The FF/Latch <cdc_vga_axi_slave_0/rdt_cs_FSM_FFd2> in Unit <cdc_vga_axi_slave_0> is equivalent to the following 2 FFs/Latches : <cdc_vga_axi_slave_0/rdt_cs_FSM_FFd2_1> <cdc_vga_axi_slave_0/rdt_cs_FSM_FFd2_2>
INFO:Xst:2260 - The FF/Latch <U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2> in Unit <cdc_vga_axi_slave_0/rdfifo> is equivalent to the following FF/Latch : <U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0>
INFO:Xst:2260 - The FF/Latch <U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i> in Unit <cdc_vga_axi_slave_0/rdfifo> is equivalent to the following FF/Latch : <U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i>
INFO:Xst:2260 - The FF/Latch <U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/aempty_fwft_i> in Unit <cdc_vga_axi_slave_0/rdfifo> is equivalent to the following FF/Latch : <U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/aempty_fwft_fb>
INFO:Xst:2260 - The FF/Latch <U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_i> in Unit <cdc_vga_axi_slave_0/rdfifo> is equivalent to the following FF/Latch : <U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb>
INFO:Xst:2260 - The FF/Latch <cdc_vga_axi_slave_0/rdt_cs_FSM_FFd1> in Unit <cdc_vga_axi_slave_0> is equivalent to the following 2 FFs/Latches : <cdc_vga_axi_slave_0/rdt_cs_FSM_FFd1_1> <cdc_vga_axi_slave_0/rdt_cs_FSM_FFd1_2>
INFO:Xst:2260 - The FF/Latch <cdc_vga_axi_slave_0/rdt_cs_FSM_FFd2> in Unit <cdc_vga_axi_slave_0> is equivalent to the following 2 FFs/Latches : <cdc_vga_axi_slave_0/rdt_cs_FSM_FFd2_1> <cdc_vga_axi_slave_0/rdt_cs_FSM_FFd2_2>
INFO:Xst:2260 - The FF/Latch <U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2> in Unit <cdc_vga_axi_slave_0/rdfifo> is equivalent to the following FF/Latch : <U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0>
INFO:Xst:2260 - The FF/Latch <U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i> in Unit <cdc_vga_axi_slave_0/rdfifo> is equivalent to the following FF/Latch : <U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i>
INFO:Xst:2260 - The FF/Latch <U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/aempty_fwft_i> in Unit <cdc_vga_axi_slave_0/rdfifo> is equivalent to the following FF/Latch : <U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/aempty_fwft_fb>
INFO:Xst:2260 - The FF/Latch <U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_i> in Unit <cdc_vga_axi_slave_0/rdfifo> is equivalent to the following FF/Latch : <U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb>
INFO:Xst:2260 - The FF/Latch <cdc_vga_axi_slave_0/rdt_cs_FSM_FFd1> in Unit <cdc_vga_axi_slave_0> is equivalent to the following 2 FFs/Latches : <cdc_vga_axi_slave_0/rdt_cs_FSM_FFd1_1> <cdc_vga_axi_slave_0/rdt_cs_FSM_FFd1_2>
INFO:Xst:2260 - The FF/Latch <cdc_vga_axi_slave_0/rdt_cs_FSM_FFd2> in Unit <cdc_vga_axi_slave_0> is equivalent to the following 2 FFs/Latches : <cdc_vga_axi_slave_0/rdt_cs_FSM_FFd2_1> <cdc_vga_axi_slave_0/rdt_cs_FSM_FFd2_2>
INFO:Xst:2260 - The FF/Latch <U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2> in Unit <cdc_vga_axi_slave_0/rdfifo> is equivalent to the following FF/Latch : <U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0>
INFO:Xst:2260 - The FF/Latch <U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i> in Unit <cdc_vga_axi_slave_0/rdfifo> is equivalent to the following FF/Latch : <U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i>
INFO:Xst:2260 - The FF/Latch <U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/aempty_fwft_i> in Unit <cdc_vga_axi_slave_0/rdfifo> is equivalent to the following FF/Latch : <U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/aempty_fwft_fb>
INFO:Xst:2260 - The FF/Latch <U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_i> in Unit <cdc_vga_axi_slave_0/rdfifo> is equivalent to the following FF/Latch : <U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb>
INFO:Xst:2260 - The FF/Latch <U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_2> in Unit <cdc_vga_axi_slave_0/rdfifo> is equivalent to the following FF/Latch : <U0/xst_fifo_generator/gconvfifo.rf/grf.rf/rstblk/ngwrdrst.grst.rd_rst_reg_0>
INFO:Xst:2260 - The FF/Latch <U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i> in Unit <cdc_vga_axi_slave_0/rdfifo> is equivalent to the following FF/Latch : <U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i>
INFO:Xst:2260 - The FF/Latch <U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/aempty_fwft_i> in Unit <cdc_vga_axi_slave_0/rdfifo> is equivalent to the following FF/Latch : <U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/aempty_fwft_fb>
INFO:Xst:2260 - The FF/Latch <U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_i> in Unit <cdc_vga_axi_slave_0/rdfifo> is equivalent to the following FF/Latch : <U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.rfwft/empty_fwft_fb>
Final Macro Processing ...
=========================================================================
Final Register Report
Found no macro
=========================================================================
=========================================================================
* Partition Report *
=========================================================================
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
=========================================================================
* Design Summary *
=========================================================================
Top Level Output File Name : system_top.ngc
Primitive and Black Box Usage:
------------------------------
# BELS : 517
# GND : 7
# INV : 104
# LUT1 : 11
# LUT2 : 33
# LUT3 : 38
# LUT4 : 76
# LUT5 : 34
# LUT6 : 63
# MUXCY : 70
# MUXF7 : 1
# VCC : 4
# XORCY : 76
# FlipFlops/Latches : 286
# FD : 18
# FDC : 30
# FDCE : 61
# FDE : 3
# FDP : 16
# FDR : 35
# FDRE : 112
# FDS : 11
# RAMS : 23
# RAM32M : 2
# RAM32X1D : 4
# RAMB18E1 : 1
# RAMB36E1 : 16
# Shift Registers : 3
# SRLC16E : 3
# Clock Buffers : 3
# BUFG : 3
# IO Buffers : 21
# IBUF : 3
# OBUF : 18
# Others : 2
# MMCME2_ADV : 1
# PS7 : 1
Device utilization summary:
---------------------------
Selected Device : 7z010clg400-1
Slice Logic Utilization:
Number of Slice Registers: 286 out of 35200 0%
Number of Slice LUTs: 378 out of 17600 2%
Number used as Logic: 359 out of 17600 2%
Number used as Memory: 19 out of 6000 0%
Number used as RAM: 16
Number used as SRL: 3
Slice Logic Distribution:
Number of LUT Flip Flop pairs used: 514
Number with an unused Flip Flop: 228 out of 514 44%
Number with an unused LUT: 136 out of 514 26%
Number of fully used LUT-FF pairs: 150 out of 514 29%
Number of unique control sets: 28
IO Utilization:
Number of IOs: 148
Number of bonded IOBs: 21 out of 100 21%
Specific Feature Utilization:
Number of Block RAM/FIFO: 17 out of 60 28%
Number using Block RAM only: 17
Number of BUFG/BUFGCTRLs: 3 out of 32 9%
---------------------------
Partition Resource Summary:
---------------------------
No Partitions were found in this design.
---------------------------
=========================================================================
Timing Report
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
------------------
------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------+
system_i/processing_system7_0/processing_system7_0/FCLK_CLK_unbuffered<0> | BUFG | 202 |
system_i/clock_generator_0/clock_generator_0/SIG_MMCM1_CLKOUT0 | BUFG | 126 |
system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/CDC_inst/char_gen_rom_inst/CHAR_GEN_ROM_INST/N0| NONE(system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/CDC_inst/char_gen_rom_inst/CHAR_GEN_ROM_INST/cdc_vga_axi_slave_0/CDC_inst/char_gen_rom_inst/CHAR_GEN_ROM_INST)| 1 |
system_i/cdc_vga_axi_slave_0/blue_out<0> | NONE(system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/CDC_inst/frame_buffer_inst/Mram_mem15) | 16 |
------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------+
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.
Asynchronous Control Signals Information:
----------------------------------------
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------+
Control Signal | Buffer(FF name) | Load |
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------+
system_i/cdc_vga_axi_slave_0/N1(system_i/cdc_vga_axi_slave_0/XST_VCC:P) | NONE(system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/CDC_inst/frame_buffer_inst/Mram_mem4) | 2976 |
system_i/cdc_vga_axi_slave_0/blue_out<0>(system_i/cdc_vga_axi_slave_0/XST_GND:G) | NONE(system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/CDC_inst/frame_buffer_inst/Mram_mem4) | 1728 |
system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/CDC_inst/char_gen_rom_inst/CHAR_GEN_ROM_INST/N0(system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/CDC_inst/char_gen_rom_inst/CHAR_GEN_ROM_INST/XST_GND:G) | NONE(system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/CDC_inst/char_gen_rom_inst/CHAR_GEN_ROM_INST/cdc_vga_axi_slave_0/CDC_inst/char_gen_rom_inst/CHAR_GEN_ROM_INST)| 12 |
system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/CDC_inst/char_gen_rom_inst/CHAR_GEN_ROM_INST/N11(system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/CDC_inst/char_gen_rom_inst/CHAR_GEN_ROM_INST/XST_VCC:P)| NONE(system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/CDC_inst/char_gen_rom_inst/CHAR_GEN_ROM_INST/cdc_vga_axi_slave_0/CDC_inst/char_gen_rom_inst/CHAR_GEN_ROM_INST)| 8 |
----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------+
Timing Summary:
---------------
Speed Grade: -1
Minimum period: 3.069ns (Maximum Frequency: 325.839MHz)
Minimum input arrival time before clock: 2.819ns
Maximum output required time after clock: 1.370ns
Maximum combinational path delay: 0.472ns
Timing Details:
---------------
All values displayed in nanoseconds (ns)
=========================================================================
Timing constraint: Default period analysis for Clock 'system_i/processing_system7_0/processing_system7_0/FCLK_CLK_unbuffered<0>'
Clock period: 3.069ns (frequency: 325.839MHz)
Total number of paths / destination ports: 2457 / 467
-------------------------------------------------------------------------
Delay: 3.069ns (Levels of Logic = 5)
Source: system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/rdt_cs_FSM_FFd2_1 (FF)
Destination: system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/rd_cdc_count_8 (FF)
Source Clock: system_i/processing_system7_0/processing_system7_0/FCLK_CLK_unbuffered<0> rising
Destination Clock: system_i/processing_system7_0/processing_system7_0/FCLK_CLK_unbuffered<0> rising
Data Path: system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/rdt_cs_FSM_FFd2_1 to system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/rd_cdc_count_8
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDR:C->Q 2 0.282 0.491 cdc_vga_axi_slave_0/rdt_cs_FSM_FFd2_1 (cdc_vga_axi_slave_0/rdt_cs_FSM_FFd2_1)
LUT2:I0->O 18 0.053 0.747 cdc_vga_axi_slave_0/rdt_cs_PWR_8_o_rdt_cs[1]_equal_77_o1 (cdc_vga_axi_slave_0/PWR_8_o_rdt_cs[1]_equal_77_o)
LUT6:I2->O 1 0.053 0.413 cdc_vga_axi_slave_0/Mmux_rd_cdc_count[8]_GND_8_o_mux_61_OUT_rs_cy<2>11 (cdc_vga_axi_slave_0/Mmux_rd_cdc_count[8]_GND_8_o_mux_61_OUT_rs_cy<2>1)
LUT5:I4->O 4 0.053 0.433 cdc_vga_axi_slave_0/Mmux_rd_cdc_count[8]_GND_8_o_mux_61_OUT_rs_cy<5>11_SW0 (cdc_vga_axi_slave_0/Mmux_rd_cdc_count[8]_GND_8_o_mux_61_OUT_rs_cy<2>)
LUT5:I4->O 3 0.053 0.427 cdc_vga_axi_slave_0/Mmux_rd_cdc_count[8]_GND_8_o_mux_61_OUT_rs_cy<5>11 (cdc_vga_axi_slave_0/Mmux_rd_cdc_count[8]_GND_8_o_mux_61_OUT_rs_cy<5>1)
LUT6:I5->O 1 0.053 0.000 cdc_vga_axi_slave_0/Mmux_rd_cdc_count[8]_GND_8_o_mux_61_OUT_rs_xor<8>11 (cdc_vga_axi_slave_0/rd_cdc_count[8]_GND_8_o_mux_61_OUT<8>)
FDRE:D 0.011 cdc_vga_axi_slave_0/rd_cdc_count_8
----------------------------------------
Total 3.069ns (0.558ns logic, 2.511ns route)
(18.2% logic, 81.8% route)
=========================================================================
Timing constraint: Default period analysis for Clock 'system_i/clock_generator_0/clock_generator_0/SIG_MMCM1_CLKOUT0'
Clock period: 2.984ns (frequency: 335.121MHz)
Total number of paths / destination ports: 2817 / 258
-------------------------------------------------------------------------
Delay: 2.984ns (Levels of Logic = 2)
Source: system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/CDC_inst/char_gen_rom_inst/CHAR_GEN_ROM_INST/cdc_vga_axi_slave_0/CDC_inst/char_gen_rom_inst/CHAR_GEN_ROM_INST (RAM)
Destination: system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/CDC_inst/blue_node_2 (FF)
Source Clock: system_i/clock_generator_0/clock_generator_0/SIG_MMCM1_CLKOUT0 rising
Destination Clock: system_i/clock_generator_0/clock_generator_0/SIG_MMCM1_CLKOUT0 rising
Data Path: system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/CDC_inst/char_gen_rom_inst/CHAR_GEN_ROM_INST/cdc_vga_axi_slave_0/CDC_inst/char_gen_rom_inst/CHAR_GEN_ROM_INST to system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/CDC_inst/blue_node_2
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
RAMB18E1:CLKARDCLK->DOADO0 9 2.454 0.466 cdc_vga_axi_slave_0/CDC_inst/char_gen_rom_inst/CHAR_GEN_ROM_INST (DO0)
end scope: 'system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/CDC_inst/char_gen_rom_inst/CHAR_GEN_ROM_INST:DO0'
LUT6:I5->O 1 0.053 0.000 cdc_vga_axi_slave_0/CDC_inst/blue_node_2_glue_rst (cdc_vga_axi_slave_0/CDC_inst/blue_node_2_glue_rst)
FDS:D 0.011 cdc_vga_axi_slave_0/CDC_inst/blue_node_2
----------------------------------------
Total 2.984ns (2.518ns logic, 0.466ns route)
(84.4% logic, 15.6% route)
=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'system_i/processing_system7_0/processing_system7_0/FCLK_CLK_unbuffered<0>'
Total number of paths / destination ports: 476 / 181
-------------------------------------------------------------------------
Offset: 2.819ns (Levels of Logic = 7)
Source: system_i/processing_system7_0/processing_system7_0/PS7_i:MAXIGP0ARLEN1 (PAD)
Destination: system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/rd_cdc_count_8 (FF)
Destination Clock: system_i/processing_system7_0/processing_system7_0/FCLK_CLK_unbuffered<0> rising
Data Path: system_i/processing_system7_0/processing_system7_0/PS7_i:MAXIGP0ARLEN1 to system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/rd_cdc_count_8
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
PS7:MAXIGP0ARLEN1 5 0.000 0.000 processing_system7_0/PS7_i (M_AXI_GP0_ARLEN<1>)
end scope: 'system_i/processing_system7_0:M_AXI_GP0_ARLEN<1>'
begin scope: 'system_i/axi_interconnect_1:S_AXI_ARLEN<1>'
end scope: 'system_i/axi_interconnect_1:M_AXI_ARLEN<1>'
begin scope: 'system_i/cdc_vga_axi_slave_0:S_AXI_ARLEN<1>'
LUT4:I0->O 2 0.053 0.608 cdc_vga_axi_slave_0/Mmux_rd_cdc_count[8]_GND_8_o_mux_61_OUT_rs_lut<1>1 (cdc_vga_axi_slave_0/Mmux_rd_cdc_count[8]_GND_8_o_mux_61_OUT_rs_lut<1>)
LUT6:I3->O 1 0.053 0.413 cdc_vga_axi_slave_0/Mmux_rd_cdc_count[8]_GND_8_o_mux_61_OUT_rs_cy<2>11 (cdc_vga_axi_slave_0/Mmux_rd_cdc_count[8]_GND_8_o_mux_61_OUT_rs_cy<2>1)
LUT5:I4->O 4 0.053 0.433 cdc_vga_axi_slave_0/Mmux_rd_cdc_count[8]_GND_8_o_mux_61_OUT_rs_cy<5>11_SW0 (cdc_vga_axi_slave_0/Mmux_rd_cdc_count[8]_GND_8_o_mux_61_OUT_rs_cy<2>)
LUT5:I4->O 3 0.053 0.427 cdc_vga_axi_slave_0/Mmux_rd_cdc_count[8]_GND_8_o_mux_61_OUT_rs_cy<5>11 (cdc_vga_axi_slave_0/Mmux_rd_cdc_count[8]_GND_8_o_mux_61_OUT_rs_cy<5>1)
LUT6:I5->O 1 0.053 0.000 cdc_vga_axi_slave_0/Mmux_rd_cdc_count[8]_GND_8_o_mux_61_OUT_rs_xor<8>11 (cdc_vga_axi_slave_0/rd_cdc_count[8]_GND_8_o_mux_61_OUT<8>)
FDRE:D 0.011 cdc_vga_axi_slave_0/rd_cdc_count_8
----------------------------------------
Total 2.819ns (0.938ns logic, 1.881ns route)
(33.3% logic, 66.7% route)
=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'system_i/clock_generator_0/clock_generator_0/SIG_MMCM1_CLKOUT0'
Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Offset: 0.872ns (Levels of Logic = 3)
Source: system_i/clock_generator_0/clock_generator_0/MMCM1_INST/MMCM_ADV_inst:LOCKED (PAD)
Destination: system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/Mshreg_reset_p2d (FF)
Destination Clock: system_i/clock_generator_0/clock_generator_0/SIG_MMCM1_CLKOUT0 rising
Data Path: system_i/clock_generator_0/clock_generator_0/MMCM1_INST/MMCM_ADV_inst:LOCKED to system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/Mshreg_reset_p2d
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
MMCME2_ADV:LOCKED 1 0.000 0.000 clock_generator_0/MMCM1_INST/MMCM_ADV_inst (LOCKED)
end scope: 'system_i/clock_generator_0:LOCKED'
begin scope: 'system_i/cdc_reset_logic:Op1<0>'
INV:I->O 1 0.067 0.399 cdc_reset_logic/Res1_INV_0 (Res<0>)
end scope: 'system_i/cdc_reset_logic:Res<0>'
begin scope: 'system_i/cdc_vga_axi_slave_0:reset_pixclk'
SRLC16E:D 0.007 cdc_vga_axi_slave_0/Mshreg_reset_p2d
----------------------------------------
Total 0.872ns (0.473ns logic, 0.399ns route)
(54.2% logic, 45.8% route)
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'system_i/clock_generator_0/clock_generator_0/SIG_MMCM1_CLKOUT0'
Total number of paths / destination ports: 11 / 11
-------------------------------------------------------------------------
Offset: 0.681ns (Levels of Logic = 2)
Source: system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/red_out_4 (FF)
Destination: vga_red<4> (PAD)
Source Clock: system_i/clock_generator_0/clock_generator_0/SIG_MMCM1_CLKOUT0 rising
Data Path: system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/red_out_4 to vga_red<4>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDR:C->Q 1 0.282 0.399 cdc_vga_axi_slave_0/red_out_4 (red_out<4>)
end scope: 'system_i/cdc_vga_axi_slave_0:red_out<4>'
end scope: 'system_i:vga_red<4>'
OBUF:I->O 0.000 vga_red_4_OBUF (vga_red<4>)
----------------------------------------
Total 0.681ns (0.282ns logic, 0.399ns route)
(41.4% logic, 58.6% route)
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'system_i/processing_system7_0/processing_system7_0/FCLK_CLK_unbuffered<0>'
Total number of paths / destination ports: 49 / 48
-------------------------------------------------------------------------
Offset: 1.370ns (Levels of Logic = 3)
Source: system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/wrt_cs_FSM_FFd2 (FF)
Destination: system_i/processing_system7_0/processing_system7_0/PS7_i:MAXIGP0WREADY (PAD)
Source Clock: system_i/processing_system7_0/processing_system7_0/FCLK_CLK_unbuffered<0> rising
Data Path: system_i/cdc_vga_axi_slave_0/cdc_vga_axi_slave_0/wrt_cs_FSM_FFd2 to system_i/processing_system7_0/processing_system7_0/PS7_i:MAXIGP0WREADY
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDR:C->Q 25 0.282 0.636 cdc_vga_axi_slave_0/wrt_cs_FSM_FFd2 (cdc_vga_axi_slave_0/wrt_cs_FSM_FFd2)
LUT2:I0->O 1 0.053 0.399 cdc_vga_axi_slave_0/wrt_cs_S_AXI_WREADY1 (S_AXI_WREADY)
end scope: 'system_i/cdc_vga_axi_slave_0:S_AXI_WREADY'
begin scope: 'system_i/axi_interconnect_1:M_AXI_WREADY<0>'
end scope: 'system_i/axi_interconnect_1:S_AXI_WREADY<0>'
begin scope: 'system_i/processing_system7_0:M_AXI_GP0_WREADY'
PS7:MAXIGP0WREADY 0.000 processing_system7_0/PS7_i
----------------------------------------
Total 1.370ns (0.335ns logic, 1.035ns route)
(24.5% logic, 75.5% route)
=========================================================================
Timing constraint: Default path analysis
Total number of paths / destination ports: 129 / 129
-------------------------------------------------------------------------
Delay: 0.472ns (Levels of Logic = 3)
Source: system_i/processing_system7_0/processing_system7_0/PS7_i:FCLKRESETN0 (PAD)
Destination: system_i/clock_generator_0/clock_generator_0/MMCM1_INST/MMCM_ADV_inst:RST (PAD)
Data Path: system_i/processing_system7_0/processing_system7_0/PS7_i:FCLKRESETN0 to system_i/clock_generator_0/clock_generator_0/MMCM1_INST/MMCM_ADV_inst:RST
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
PS7:FCLKRESETN0 2 0.000 0.000 processing_system7_0/PS7_i (FCLK_RESET0_N)
end scope: 'system_i/processing_system7_0:FCLK_RESET0_N'
begin scope: 'system_i/clkgen_reset_logic:Op1<0>'
INV:I->O 0 0.067 0.000 clkgen_reset_logic/Res1_INV_0 (Res<0>)
end scope: 'system_i/clkgen_reset_logic:Res<0>'
begin scope: 'system_i/clock_generator_0:RST'
MMCME2_ADV:RST 0.000 clock_generator_0/MMCM1_INST/MMCM_ADV_inst
----------------------------------------
Total 0.472ns (0.472ns logic, 0.000ns route)
(100.0% logic, 0.0% route)
=========================================================================
Cross Clock Domains Report:
--------------------------
Clock to Setup on destination clock system_i/clock_generator_0/clock_generator_0/SIG_MMCM1_CLKOUT0
--------------------------------------------------------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
--------------------------------------------------------------+---------+---------+---------+---------+
system_i/cdc_vga_axi_slave_0/blue_out<0> | 3.419| | | |
system_i/clock_generator_0/clock_generator_0/SIG_MMCM1_CLKOUT0| 2.984| | | |
--------------------------------------------------------------+---------+---------+---------+---------+
Clock to Setup on destination clock system_i/processing_system7_0/processing_system7_0/FCLK_CLK_unbuffered<0>
-------------------------------------------------------------------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
-------------------------------------------------------------------------+---------+---------+---------+---------+
system_i/cdc_vga_axi_slave_0/blue_out<0> | 3.176| | | |
system_i/processing_system7_0/processing_system7_0/FCLK_CLK_unbuffered<0>| 3.069| | | |
-------------------------------------------------------------------------+---------+---------+---------+---------+
=========================================================================
Total REAL time to Xst completion: 57.00 secs
Total CPU time to Xst completion: 56.50 secs
-->
Total memory usage is 507832 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 3 ( 0 filtered)
Number of infos : 24 ( 0 filtered)