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sesame.par
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Release 14.6 par P.68d (nt64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
CS152A-11:: Thu Mar 10 16:12:57 2016
par -w -intstyle ise -ol high -mt off sesame_map.ncd sesame.ncd sesame.pcf
Constraints file: sesame.pcf.
Loading device for application Rf_Device from file '6slx16.nph' in environment C:\Xilinx\14.6\ISE_DS\ISE\.
"sesame" is an NCD, version 3.2, device xc6slx16, package csg324, speed -2
vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
INFO:Security:54 - 'xc6slx16' is a WebPack part.
WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue
to function, but you no longer qualify for Xilinx software updates or new releases.
----------------------------------------------------------------------
Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
Device speed data version: "PRODUCTION 1.23 2013-06-08".
Device Utilization Summary:
Slice Logic Utilization:
Number of Slice Registers: 447 out of 18,224 2%
Number used as Flip Flops: 417
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 30
Number of Slice LUTs: 1,023 out of 9,112 11%
Number used as logic: 989 out of 9,112 10%
Number using O6 output only: 460
Number using O5 output only: 236
Number using O5 and O6: 293
Number used as ROM: 0
Number used as Memory: 0 out of 2,176 0%
Number used exclusively as route-thrus: 34
Number with same-slice register load: 4
Number with same-slice carry load: 30
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 347 out of 2,278 15%
Number of MUXCYs used: 636 out of 4,556 13%
Number of LUT Flip Flop pairs used: 1,049
Number with an unused Flip Flop: 664 out of 1,049 63%
Number with an unused LUT: 26 out of 1,049 2%
Number of fully used LUT-FF pairs: 359 out of 1,049 34%
Number of slice register sites lost
to control set restrictions: 0 out of 18,224 0%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
IO Utilization:
Number of bonded IOBs: 28 out of 232 12%
Number of LOCed IOBs: 28 out of 28 100%
IOB Flip Flops: 4
Specific Feature Utilization:
Number of RAMB16BWERs: 24 out of 32 75%
Number of RAMB8BWERs: 16 out of 64 25%
Number of BUFIO2/BUFIO2_2CLKs: 0 out of 32 0%
Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0%
Number of BUFG/BUFGMUXs: 5 out of 16 31%
Number used as BUFGs: 5
Number used as BUFGMUX: 0
Number of DCM/DCM_CLKGENs: 0 out of 4 0%
Number of ILOGIC2/ISERDES2s: 4 out of 248 1%
Number used as ILOGIC2s: 4
Number used as ISERDES2s: 0
Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 248 0%
Number of OLOGIC2/OSERDES2s: 0 out of 248 0%
Number of BSCANs: 0 out of 4 0%
Number of BUFHs: 0 out of 128 0%
Number of BUFPLLs: 0 out of 8 0%
Number of BUFPLL_MCBs: 0 out of 4 0%
Number of DSP48A1s: 5 out of 32 15%
Number of ICAPs: 0 out of 1 0%
Number of MCBs: 0 out of 2 0%
Number of PCILOGICSEs: 0 out of 2 0%
Number of PLL_ADVs: 0 out of 2 0%
Number of PMVs: 0 out of 1 0%
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Overall effort level (-ol): High
Router effort level (-rl): High
Starting initial Timing Analysis. REAL time: 5 secs
Finished initial Timing Analysis. REAL time: 5 secs
Starting Router
Phase 1 : 8992 unrouted; REAL time: 5 secs
Phase 2 : 5037 unrouted; REAL time: 6 secs
Phase 3 : 1847 unrouted; REAL time: 8 secs
Phase 4 : 1858 unrouted; (Setup:73619, Hold:0, Component Switching Limit:0) REAL time: 9 secs
Updating file: sesame.ncd with current fully routed design.
Phase 5 : 0 unrouted; (Setup:74745, Hold:0, Component Switching Limit:0) REAL time: 13 secs
Phase 6 : 0 unrouted; (Setup:70697, Hold:0, Component Switching Limit:0) REAL time: 15 secs
Updating file: sesame.ncd with current fully routed design.
Phase 7 : 0 unrouted; (Setup:70697, Hold:0, Component Switching Limit:0) REAL time: 19 secs
Phase 8 : 0 unrouted; (Setup:70697, Hold:0, Component Switching Limit:0) REAL time: 19 secs
Phase 9 : 0 unrouted; (Setup:70697, Hold:0, Component Switching Limit:0) REAL time: 19 secs
Phase 10 : 0 unrouted; (Setup:63434, Hold:0, Component Switching Limit:0) REAL time: 19 secs
Total REAL time to Router completion: 19 secs
Total CPU time to Router completion: 19 secs
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
Generating "PAR" statistics.
**************************
Generating Clock Report
**************************
+---------------------+--------------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
| clk_BUFGP | BUFGMUX_X3Y13| No | 148 | 0.058 | 1.135 |
+---------------------+--------------+------+------+------------+-------------+
| joy/clk_joy_BUFG | BUFGMUX_X2Y1| No | 18 | 0.026 | 1.099 |
+---------------------+--------------+------+------+------------+-------------+
| clk_vga_BUFG | BUFGMUX_X2Y3| No | 17 | 0.028 | 1.116 |
+---------------------+--------------+------+------+------------+-------------+
| comboLR_BUFG | BUFGMUX_X2Y4| No | 10 | 0.007 | 1.095 |
+---------------------+--------------+------+------+------------+-------------+
| clk_cursor_BUFG | BUFGMUX_X2Y2| No | 6 | 0.008 | 1.090 |
+---------------------+--------------+------+------+------------+-------------+
| comboUD | Local| | 1 | 0.000 | 0.373 |
+---------------------+--------------+------+------+------------+-------------+
| clk_debounce | Local| | 9 | 0.625 | 1.833 |
+---------------------+--------------+------+------+------------+-------------+
| counter_vga | Local| | 2 | 0.000 | 0.588 |
+---------------------+--------------+------+------+------------+-------------+
* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.
* The fanout is the number of component pins not the individual BEL loads,
for example SLICE loads not FF loads.
Timing Score: 63434 (Setup: 63434, Hold: 0, Component Switching Limit: 0)
WARNING:Par:468 - Your design did not meet timing. The following are some suggestions to assist you to meet timing in your design.
Review the timing report using Timing Analyzer (In ISE select "Post-Place &
Route Static Timing Report"). Go to the failing constraint(s) and evaluate the failing paths for each constraint.
Try the Design Goal and Strategies for Timing Performance(In ISE select Project -> Design Goals & Strategies) to ensure the best options
are set in the tools for timing closure.
Use the Xilinx "SmartXplorer" script to try special combinations of
options known to produce very good results.
Visit the Xilinx technical support web at http://support.xilinx.com and go to
either "Troubleshoot->Tech Tips->Timing & Constraints" or "
TechXclusives->Timing Closure" for tips and suggestions for meeting timing
in your design.
Asterisk (*) preceding a constraint indicates it was not met.
This may be due to a setup or hold violation.
----------------------------------------------------------------------------------------------------------
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
----------------------------------------------------------------------------------------------------------
* TS_sys_clk_pin = PERIOD TIMEGRP "sys_clk_ | SETUP | -3.189ns| 13.189ns| 31| 63434
pin" 100 MHz HIGH 50% | HOLD | 0.418ns| | 0| 0
----------------------------------------------------------------------------------------------------------
1 constraint not met.
Generating Pad Report.
All signals are completely routed.
Total REAL time to PAR completion: 20 secs
Total CPU time to PAR completion: 20 secs
Peak Memory Usage: 363 MB
Placer: Placement generated during map.
Routing: Completed - No errors found.
Timing: Completed - 31 errors found.
Number of error messages: 0
Number of warning messages: 1
Number of info messages: 0
Writing design to file sesame.ncd
PAR done!