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sesame.twx
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<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE twReport [
<!ELEMENT twReport (twHead?, (twWarn | twDebug | twInfo)*, twBody, twSum?,
twDebug*, twFoot?, twClientInfo?)>
<!ATTLIST twReport version CDATA "10,4">
<!ELEMENT twHead (twExecVer?, twCopyright, twCmdLine?, twDesign?, twPCF?, twDevInfo, twRptInfo, twEnvVar*)>
<!ELEMENT twExecVer (#PCDATA)>
<!ELEMENT twCopyright (#PCDATA)>
<!ELEMENT twCmdLine (#PCDATA)>
<!ELEMENT twDesign (#PCDATA)>
<!ELEMENT twPCF (#PCDATA)>
<!ELEMENT twDevInfo (twDevName, twSpeedGrade, twSpeedVer?)>
<!ELEMENT twDevName (#PCDATA)>
<!ATTLIST twDevInfo arch CDATA #IMPLIED pkg CDATA #IMPLIED>
<!ELEMENT twSpeedGrade (#PCDATA)>
<!ELEMENT twSpeedVer (#PCDATA)>
<!ELEMENT twRptInfo (twItemLimit?, (twUnconst, twUnconstLimit?)?)>
<!ATTLIST twRptInfo twRptLvl (twErr | twVerbose | twTerseErr | twSum | twTimeGrp) #REQUIRED>
<!ATTLIST twRptInfo twAdvRpt (TRUE | FALSE) "FALSE">
<!ATTLIST twRptInfo twTimeUnits (twPsec | twNsec | twUsec | twMsec | twSec) "twNsec">
<!ATTLIST twRptInfo twFreqUnits (twGHz | twMHz | twHz) "twMHz">
<!ATTLIST twRptInfo twReportMinPaths CDATA #IMPLIED>
<!ELEMENT twItemLimit (#PCDATA)>
<!ELEMENT twUnconst EMPTY>
<!ELEMENT twUnconstLimit (#PCDATA)>
<!ELEMENT twEnvVar EMPTY>
<!ATTLIST twEnvVar name CDATA #REQUIRED>
<!ATTLIST twEnvVar description CDATA #REQUIRED>
<!ELEMENT twWarn (#PCDATA)>
<!ELEMENT twInfo (#PCDATA)>
<!ELEMENT twDebug (#PCDATA)>
<!ELEMENT twBody (twDerating?, (twSumRpt | twVerboseRpt | twErrRpt | twTerseErrRpt | twTimeGrpRpt), twNonDedClks?)>
<!ATTLIST twBody twFastPaths CDATA #IMPLIED>
<!ELEMENT twDerating (twProc?, twTemp?, twVolt?)>
<!ELEMENT twProc (#PCDATA)>
<!ELEMENT twTemp (#PCDATA)>
<!ELEMENT twVolt (#PCDATA)>
<!ELEMENT twSumRpt (twConstRollupTable*, twConstList?, twConstSummaryTable?, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?)>
<!ELEMENT twErrRpt (twCycles?, (twConst | twTIG | twConstRollupTable)*, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?, twTimeGrp*)>
<!ELEMENT twTerseErrRpt (twConstList, twUnmetConstCnt?, twDataSheet?)>
<!ELEMENT twVerboseRpt (twCycles?, (twConst | twTIG | twConstRollupTable)*, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?, twTimeGrp*)>
<!ELEMENT twCycles (twSigConn+)>
<!ATTLIST twCycles twNum CDATA #REQUIRED>
<!ELEMENT twSigConn (twSig, twDriver, twLoad)>
<!ELEMENT twSig (#PCDATA)>
<!ELEMENT twDriver (#PCDATA)>
<!ELEMENT twLoad (#PCDATA)>
<!ELEMENT twConst (twConstHead, ((twPathRpt?,twRacePathRpt?, twPathRptBanner?)* | (twPathRpt*, twRacePathRpt?) | twNetRpt* | twClkSkewLimit*))>
<!ATTLIST twConst twConstType (NET |
NETDELAY |
NETSKEW |
PATH |
DEFPERIOD |
UNCONSTPATH |
DEFPATH |
PATH2SETUP |
UNCONSTPATH2SETUP |
PATHCLASS |
PATHDELAY |
PERIOD |
FREQUENCY |
PATHBLOCK |
OFFSET |
OFFSETIN |
OFFSETINCLOCK |
UNCONSTOFFSETINCLOCK |
OFFSETINDELAY |
OFFSETINMOD |
OFFSETOUT |
OFFSETOUTCLOCK |
UNCONSTOFFSETOUTCLOCK |
OFFSETOUTDELAY |
OFFSETOUTMOD| CLOCK_SKEW_LIMITS) #IMPLIED>
<!ELEMENT twConstHead (twConstName, twItemCnt, twErrCntSetup, twErrCntEndPt?, twErrCntHold,
twEndPtCnt?,
twPathErrCnt?, (twMinPer| twMaxDel| twMaxFreq| twMaxNetDel| twMaxNetSkew| twMinOff| twMaxOff)*)>
<!ELEMENT twConstName (#PCDATA)>
<!ATTLIST twConstName UCFConstName CDATA #IMPLIED>
<!ATTLIST twConstHead uID CDATA #IMPLIED>
<!ELEMENT twItemCnt (#PCDATA)>
<!ELEMENT twErrCnt (#PCDATA)>
<!ELEMENT twErrCntEndPt (#PCDATA)>
<!ELEMENT twErrCntSetup (#PCDATA)>
<!ELEMENT twErrCntHold (#PCDATA)>
<!ATTLIST twErrCntHold twRaceChecked (TRUE | FALSE) "FALSE">
<!ELEMENT twEndPtCnt (#PCDATA)>
<!ELEMENT twPathErrCnt (#PCDATA)>
<!ELEMENT twMinPer (#PCDATA) >
<!ELEMENT twFootnote EMPTY>
<!ATTLIST twFootnote number CDATA #REQUIRED>
<!ELEMENT twMaxDel (#PCDATA)>
<!ELEMENT twMaxFreq (#PCDATA)>
<!ELEMENT twMinOff (#PCDATA)>
<!ELEMENT twMaxOff (#PCDATA)>
<!ELEMENT twTIG (twTIGHead, (twPathRpt*,twRacePathRpt?))>
<!ELEMENT twTIGHead (twTIGName, twInstantiated, twBlocked)>
<!ELEMENT twTIGName (#PCDATA)>
<!ELEMENT twInstantiated (#PCDATA)>
<!ELEMENT twBlocked (#PCDATA)>
<!ELEMENT twRacePathRpt (twRacePath+)>
<!ELEMENT twPathRpt (twUnconstPath | twConstPath | twUnconstOffIn | twConstOffIn | twUnconstOffOut | twConstOffOut | twModOffOut)>
<!ELEMENT twUnconstPath (twTotDel, twSrc, twDest, (twDel, twSUTime)?, twTotPathDel?, twClkSkew?, tw2Phase?, twClkUncert?, twDetPath?)>
<!ATTLIST twUnconstPath twDataPathType CDATA #IMPLIED
twSimpleMinPath CDATA #IMPLIED>
<!ELEMENT twTotDel (#PCDATA)>
<!ELEMENT twSrc (#PCDATA)>
<!ATTLIST twSrc BELType CDATA #IMPLIED>
<!ELEMENT twDest (#PCDATA)>
<!ATTLIST twDest BELType CDATA #IMPLIED>
<!ELEMENT twDel (#PCDATA)>
<!ELEMENT twSUTime (#PCDATA)>
<!ELEMENT twTotPathDel (#PCDATA)>
<!ELEMENT twClkSkew (#PCDATA)>
<!ATTLIST twClkSkew dest CDATA #IMPLIED src CDATA #IMPLIED>
<!ELEMENT twConstPath (twSlack, twSrc, twDest, twTotPathDel?, twClkSkew?, twDelConst, tw2Phase?, twClkUncert?, twDetPath?)>
<!ATTLIST twConstPath twDataPathType CDATA "twDataPathMaxDelay">
<!ATTLIST twConstPath constType (period | fromto | unknown) "unknown">
<!ELEMENT twSlack (#PCDATA)>
<!ELEMENT twDelConst (#PCDATA)>
<!ELEMENT tw2Phase EMPTY>
<!ELEMENT twClkUncert (#PCDATA)>
<!ATTLIST twClkUncert fSysJit CDATA #IMPLIED fInputJit CDATA #IMPLIED
fDCMJit CDATA #IMPLIED
fPhaseErr CDATA #IMPLIED
sEqu CDATA #IMPLIED>
<!ELEMENT twRacePath (twSlack, twSrc, twDest, twClkSkew, twDelConst?, twClkUncert?, twDetPath)>
<!ELEMENT twPathRptBanner (#PCDATA)>
<!ATTLIST twPathRptBanner sType CDATA #IMPLIED iPaths CDATA #IMPLIED iCriticalPaths CDATA #IMPLIED>
<!ELEMENT twUnconstOffIn (twOff, twSrc, twDest, twGuaranteed?, twClkUncert?, (twDataPath, twClkPath)?)>
<!ATTLIST twUnconstOffIn twDataPathType CDATA #IMPLIED>
<!ELEMENT twOff (#PCDATA)>
<!ELEMENT twGuaranteed EMPTY>
<!ELEMENT twConstOffIn (twSlack, twSrc, twDest, ((twClkDel, twClkSrc, twClkDest) | twGuarInSetup), twOff, twOffSrc, twOffDest, twClkUncert?, (twDataPath, twClkPath)?)>
<!ATTLIST twConstOffIn twDataPathType CDATA "twDataPathMaxDelay">
<!ATTLIST twConstOffIn twDurationNotSpecified CDATA #IMPLIED>
<!ELEMENT twClkDel (#PCDATA)>
<!ELEMENT twClkSrc (#PCDATA)>
<!ELEMENT twClkDest (#PCDATA)>
<!ELEMENT twGuarInSetup (#PCDATA)>
<!ELEMENT twOffSrc (#PCDATA)>
<!ELEMENT twOffDest (#PCDATA)>
<!ELEMENT twUnconstOffOut (twOff, twSrc, twDest, twClkUncert?, (twClkPath, twDataPath)?)>
<!ATTLIST twUnconstOffOut twDataPathType CDATA #IMPLIED>
<!ELEMENT twConstOffOut (twSlack, twSrc, twDest, twClkDel, twClkSrc, twClkDest, twDataDel, twDataSrc, twDataDest, twOff, twOffSrc, twOffDest, twClkUncert?, (twClkPath, twDataPath)?)>
<!ATTLIST twConstOffOut twDataPathType CDATA "twDataPathMaxDelay">
<!ELEMENT twDataDel (#PCDATA)>
<!ELEMENT twDataSrc (#PCDATA)>
<!ELEMENT twDataDest (#PCDATA)>
<!ELEMENT twModOffOut (twSlack, twDest, twDataDel, twDataSrc, twDataDest, twClkUncert?, twDataPath?)>
<!ELEMENT twDetPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
<!ATTLIST twDetPath maxSiteLen CDATA #IMPLIED>
<!ELEMENT twDataPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
<!ATTLIST twDataPath maxSiteLen CDATA #IMPLIED>
<!ELEMENT twClkPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
<!ATTLIST twClkPath maxSiteLen CDATA #IMPLIED>
<!ELEMENT twLogLvls (#PCDATA)>
<!ELEMENT twSrcSite (#PCDATA)>
<!ELEMENT twSrcClk (#PCDATA)>
<!ATTLIST twSrcClk twEdge (twRising | twFalling) "twRising">
<!ATTLIST twSrcClk twArriveTime CDATA #IMPLIED>
<!ATTLIST twSrcClk twClkRes CDATA #IMPLIED>
<!ELEMENT twPathDel (twSite, twDelType, twFanCnt?, twDelInfo?, twComp, twNet?, twBEL*)>
<!ATTLIST twPathDel twHoldTime (TRUE | FALSE) "FALSE">
<!ELEMENT twDelInfo (#PCDATA)>
<!ATTLIST twDelInfo twEdge (twRising | twFalling | twIndet) #REQUIRED>
<!ATTLIST twDelInfo twAcc (twRouted | twEst | twApprox) "twRouted">
<!ELEMENT twSite (#PCDATA)>
<!ELEMENT twDelType (#PCDATA)>
<!ELEMENT twFanCnt (#PCDATA)>
<!ELEMENT twComp (#PCDATA)>
<!ELEMENT twNet (#PCDATA)>
<!ELEMENT twBEL (#PCDATA)>
<!ELEMENT twLogDel (#PCDATA)>
<!ELEMENT twRouteDel (#PCDATA)>
<!ELEMENT twDestClk (#PCDATA)>
<!ATTLIST twDestClk twEdge (twRising | twFalling) "twRising">
<!ATTLIST twDestClk twArriveTime CDATA #IMPLIED>
<!ATTLIST twDestClk twClkRes CDATA #IMPLIED>
<!ELEMENT twPctLog (#PCDATA)>
<!ELEMENT twPctRoute (#PCDATA)>
<!ELEMENT twNetRpt (twDelNet | twSlackNet | twSkewNet)>
<!ELEMENT twDelNet (twDel, twNet, twDetNet?)>
<!ELEMENT twSlackNet (twSlack, twNet, twDel, twNotMet?, twTimeConst, twAbsSlack, twDetNet?)>
<!ELEMENT twTimeConst (#PCDATA)>
<!ELEMENT twAbsSlack (#PCDATA)>
<!ELEMENT twSkewNet (twSlack, twNet, twSkew, twNotMet?, twTimeConst, twAbsSlack, twDetSkewNet?)>
<!ELEMENT twSkew (#PCDATA)>
<!ELEMENT twDetNet (twNetDel*)>
<!ELEMENT twNetDel (twSrc, twDest, twNetDelInfo)>
<!ELEMENT twNetDelInfo (#PCDATA)>
<!ATTLIST twNetDelInfo twAcc (twRouted | twEst | twApprox) "twRouted">
<!ELEMENT twDetSkewNet (twNetSkew*)>
<!ELEMENT twNetSkew (twSrc, twDest, twNetDelInfo, twSkew)>
<!ELEMENT twClkSkewLimit EMPTY>
<!ATTLIST twClkSkewLimit slack CDATA #IMPLIED skew CDATA #IMPLIED arrv1name CDATA #IMPLIED arrv1 CDATA #IMPLIED
arrv2name CDATA #IMPLIED arrv2 CDATA #IMPLIED uncert CDATA #IMPLIED>
<!ELEMENT twConstRollupTable (twConstRollup*)>
<!ATTLIST twConstRollupTable uID CDATA #IMPLIED>
<!ELEMENT twConstRollup EMPTY>
<!ATTLIST twConstRollup name CDATA #IMPLIED fullName CDATA #IMPLIED type CDATA #IMPLIED requirement CDATA #IMPLIED prefType CDATA #IMPLIED actual CDATA #IMPLIED>
<!ATTLIST twConstRollup actualRollup CDATA #IMPLIED errors CDATA #IMPLIED errorRollup CDATA #IMPLIED items CDATA #IMPLIED itemsRollup CDATA #IMPLIED>
<!ELEMENT twConstList (twConstListItem)*>
<!ELEMENT twConstListItem (twConstName, twNotMet?, twReqVal?, twActVal?, twLogLvls?)>
<!ATTLIST twConstListItem twUnits (twTime | twFreq) "twTime">
<!ELEMENT twNotMet EMPTY>
<!ELEMENT twReqVal (#PCDATA)>
<!ELEMENT twActVal (#PCDATA)>
<!ELEMENT twConstSummaryTable (twConstStats|twConstSummary)*>
<!ATTLIST twConstSummaryTable twEmptyConstraints CDATA #IMPLIED>
<!ELEMENT twConstStats (twConstName)>
<!ATTLIST twConstStats twUnits (twTime | twFreq) "twTime">
<!ATTLIST twConstStats twRequired CDATA #IMPLIED>
<!ATTLIST twConstStats twActual CDATA #IMPLIED>
<!ATTLIST twConstStats twSlack CDATA #IMPLIED>
<!ATTLIST twConstStats twLogLvls CDATA #IMPLIED>
<!ATTLIST twConstStats twErrors CDATA #IMPLIED>
<!ATTLIST twConstStats twPCFIndex CDATA #IMPLIED>
<!ATTLIST twConstStats twAbsSlackIndex CDATA #IMPLIED>
<!ATTLIST twConstStats twTCType CDATA #IMPLIED>
<!ELEMENT twConstSummary (twConstName, twConstData?, twConstData*)>
<!ATTLIST twConstSummary PCFIndex CDATA #IMPLIED slackIndex CDATA #IMPLIED>
<!ELEMENT twConstData EMPTY>
<!ATTLIST twConstData type CDATA #IMPLIED units (MHz | ns) "ns" slack CDATA #IMPLIED
best CDATA #IMPLIED requested CDATA #IMPLIED
errors CDATA #IMPLIED
score CDATA #IMPLIED>
<!ELEMENT twTimeGrpRpt (twTimeGrp)*>
<!ELEMENT twTimeGrp (twTimeGrpName, twCompList?, twBELList?, twMacList?, twBlockList?, twSigList?, twPinList?)>
<!ELEMENT twTimeGrpName (#PCDATA)>
<!ELEMENT twCompList (twCompName+)>
<!ELEMENT twCompName (#PCDATA)>
<!ELEMENT twSigList (twSigName+)>
<!ELEMENT twSigName (#PCDATA)>
<!ELEMENT twBELList (twBELName+)>
<!ELEMENT twBELName (#PCDATA)>
<!ELEMENT twBlockList (twBlockName+)>
<!ELEMENT twBlockName (#PCDATA)>
<!ELEMENT twMacList (twMacName+)>
<!ELEMENT twMacName (#PCDATA)>
<!ELEMENT twPinList (twPinName+)>
<!ELEMENT twPinName (#PCDATA)>
<!ELEMENT twUnmetConstCnt (#PCDATA)>
<!ELEMENT twDataSheet (twSUH2ClkList*, (twClk2PadList|twClk2OutList)*, twClk2SUList*, twPad2PadList?, twOffsetTables?)>
<!ATTLIST twDataSheet twNameLen CDATA #REQUIRED>
<!ELEMENT twSUH2ClkList (twDest, twSUH2Clk+)>
<!ATTLIST twSUH2ClkList twDestWidth CDATA #IMPLIED>
<!ATTLIST twSUH2ClkList twPhaseWidth CDATA #IMPLIED>
<!ELEMENT twSUH2Clk (twSrc, twSUHTime, twSUHTime?)>
<!ELEMENT twSUHTime (twSU2ClkTime?,twH2ClkTime?)>
<!ATTLIST twSUHTime twInternalClk CDATA #IMPLIED>
<!ATTLIST twSUHTime twClkPhase CDATA #IMPLIED>
<!ELEMENT twSU2ClkTime (#PCDATA)>
<!ATTLIST twSU2ClkTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
<!ELEMENT twH2ClkTime (#PCDATA)>
<!ATTLIST twH2ClkTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
<!ELEMENT twClk2PadList (twSrc, twClk2Pad+)>
<!ELEMENT twClk2Pad (twDest, twTime)>
<!ELEMENT twTime (#PCDATA)>
<!ATTLIST twTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
<!ELEMENT twClk2OutList (twSrc, twClk2Out+)>
<!ATTLIST twClk2OutList twDestWidth CDATA #REQUIRED>
<!ATTLIST twClk2OutList twPhaseWidth CDATA #REQUIRED>
<!ELEMENT twClk2Out EMPTY>
<!ATTLIST twClk2Out twOutPad CDATA #REQUIRED>
<!ATTLIST twClk2Out twMinTime CDATA #REQUIRED>
<!ATTLIST twClk2Out twMinEdge CDATA #REQUIRED>
<!ATTLIST twClk2Out twMaxTime CDATA #REQUIRED>
<!ATTLIST twClk2Out twMaxEdge CDATA #REQUIRED>
<!ATTLIST twClk2Out twInternalClk CDATA #REQUIRED>
<!ATTLIST twClk2Out twClkPhase CDATA #REQUIRED>
<!ELEMENT twClk2SUList (twDest, twClk2SU+)>
<!ATTLIST twClk2SUList twDestWidth CDATA #IMPLIED>
<!ELEMENT twClk2SU (twSrc, twRiseRise?, twFallRise?, twRiseFall?, twFallFall?)>
<!ELEMENT twRiseRise (#PCDATA)>
<!ELEMENT twFallRise (#PCDATA)>
<!ELEMENT twRiseFall (#PCDATA)>
<!ELEMENT twFallFall (#PCDATA)>
<!ELEMENT twPad2PadList (twPad2Pad+)>
<!ATTLIST twPad2PadList twSrcWidth CDATA #IMPLIED>
<!ATTLIST twPad2PadList twDestWidth CDATA #IMPLIED>
<!ELEMENT twPad2Pad (twSrc, twDest, twDel)>
<!ELEMENT twOffsetTables (twOffsetInTable*,twOffsetOutTable*)>
<!ELEMENT twOffsetInTable (twConstName, twOffInTblRow*)>
<!ATTLIST twOffsetInTable twDestWidth CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstWindow CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstSetup CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstHold CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstSetupSlack CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstHoldSlack CDATA #IMPLIED>
<!ELEMENT twOffsetOutTable (twConstName, twOffOutTblRow*)>
<!ATTLIST twOffsetOutTable twDestWidth CDATA #IMPLIED>
<!ATTLIST twOffsetOutTable twMinSlack CDATA #IMPLIED>
<!ATTLIST twOffsetOutTable twMaxSlack CDATA #IMPLIED>
<!ATTLIST twOffsetOutTable twRelSkew CDATA #IMPLIED>
<!ELEMENT twOffInTblRow (twSrc, twSUHSlackTime*)>
<!ELEMENT twSUHSlackTime (twSU2ClkTime?,twH2ClkTime?)>
<!ATTLIST twSUHSlackTime twSetupSlack CDATA #IMPLIED twHoldSlack CDATA #IMPLIED>
<!ELEMENT twOffOutTblRow EMPTY>
<!ATTLIST twOffOutTblRow twOutPad CDATA #IMPLIED>
<!ATTLIST twOffOutTblRow twSlack CDATA #IMPLIED>
<!ATTLIST twOffOutTblRow twRelSkew CDATA #IMPLIED>
<!ELEMENT twNonDedClks ((twWarn | twInfo), twNonDedClk+)>
<!ELEMENT twNonDedClk (#PCDATA)>
<!ELEMENT twSum ( twErrCnt, twScore, twConstCov, twStats)>
<!ELEMENT twScore (#PCDATA)>
<!ELEMENT twConstCov (twPathCnt, twNetCnt, twConnCnt, twPct?)>
<!ELEMENT twPathCnt (#PCDATA)>
<!ELEMENT twNetCnt (#PCDATA)>
<!ELEMENT twConnCnt (#PCDATA)>
<!ELEMENT twPct (#PCDATA)>
<!ELEMENT twStats ( twMinPer?, twFootnote?, twMaxFreq?, twMaxCombDel?, twMaxFromToDel?, twMaxNetDel?, twMaxNetSkew?, twMaxInAfterClk?, twMinInBeforeClk?, twMaxOutBeforeClk?, twMinOutAfterClk?, (twInfo | twWarn)*)>
<!ELEMENT twMaxCombDel (#PCDATA)>
<!ELEMENT twMaxFromToDel (#PCDATA)>
<!ELEMENT twMaxNetDel (#PCDATA)>
<!ELEMENT twMaxNetSkew (#PCDATA)>
<!ELEMENT twMaxInAfterClk (#PCDATA)>
<!ELEMENT twMinInBeforeClk (#PCDATA)>
<!ELEMENT twMaxOutBeforeClk (#PCDATA)>
<!ELEMENT twMinOutAfterClk (#PCDATA)>
<!ELEMENT twFoot (twFootnoteExplanation*, twTimestamp)>
<!ELEMENT twTimestamp (#PCDATA)>
<!ELEMENT twFootnoteExplanation EMPTY>
<!ATTLIST twFootnoteExplanation number CDATA #REQUIRED>
<!ATTLIST twFootnoteExplanation text CDATA #REQUIRED>
<!ELEMENT twClientInfo (twClientName, twAttrList?)>
<!ELEMENT twClientName (#PCDATA)>
<!ELEMENT twAttrList (twAttrListItem)*>
<!ELEMENT twAttrListItem (twName, twValue*)>
<!ELEMENT twName (#PCDATA)>
<!ELEMENT twValue (#PCDATA)>
]>
<twReport><twHead anchorID="1"><twExecVer>Release 14.6 Trace (nt64)</twExecVer><twCopyright>Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.</twCopyright><twCmdLine>C:\Xilinx\14.6\ISE_DS\ISE\bin\nt64\unwrapped\trce.exe -intstyle ise -v 3 -s 2
-n 3 -fastpaths -xml sesame.twx sesame.ncd -o sesame.twr sesame.pcf -ucf
nexys3.ucf
</twCmdLine><twDesign>sesame.ncd</twDesign><twDesignPath>sesame.ncd</twDesignPath><twPCF>sesame.pcf</twPCF><twPcfPath>sesame.pcf</twPcfPath><twDevInfo arch="spartan6" pkg="csg324"><twDevName>xc6slx16</twDevName><twDevRange>C</twDevRange><twSpeedGrade>-2</twSpeedGrade><twSpeedVer>PRODUCTION 1.23 2013-06-08</twSpeedVer><twQuadDly>1</twQuadDly></twDevInfo><twRptInfo twRptLvl="twVerbose" twReportMinPaths="true" dlyHyperLnks="t" ><twEndptLimit>3</twEndptLimit></twRptInfo><twEnvVar name="NONE" description="No environment variables were set" /></twHead><twInfo anchorID="2">INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).</twInfo><twInfo anchorID="3">INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.</twInfo><twInfo anchorID="4">INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.</twInfo><twBody><twVerboseRpt><twConst anchorID="5" twConstType="PERIOD" ><twConstHead uID="1"><twConstName UCFConstName="TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 100000 kHz;" ScopeName="">TS_sys_clk_pin = PERIOD TIMEGRP "sys_clk_pin" 100 MHz HIGH 50%;</twConstName><twItemCnt>1558639</twItemCnt><twErrCntSetup>31</twErrCntSetup><twErrCntEndPt>31</twErrCntEndPt><twErrCntHold twRaceChecked="TRUE">0</twErrCntHold><twErrCntPinLimit>0</twErrCntPinLimit><twEndPtCnt>1795</twEndPtCnt><twPathErrCnt>1535449</twPathErrCnt><twMinPer>13.189</twMinPer></twConstHead><twPathRptBanner iPaths="148909" iCriticalPaths="148876" sType="EndPoint">Paths for end point pmin_addr_11 (SLICE_X27Y23.B6), 148909 paths
</twPathRptBanner><twPathRpt anchorID="6"><twConstPath anchorID="7" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>-3.189</twSlack><twSrc BELType="FF">pencil_y_0</twSrc><twDest BELType="FF">pmin_addr_11</twDest><twTotPathDel>13.132</twTotPathDel><twClkSkew dest = "0.307" src = "0.329">0.022</twClkSkew><twDelConst>10.000</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.035</twClkUncert><twDetPath maxSiteLen="17" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>pencil_y_0</twSrc><twDest BELType='FF'>pmin_addr_11</twDest><twLogLvls>10</twLogLvls><twSrcSite>SLICE_X24Y17.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">clk_BUFGP</twSrcClk><twPathDel><twSite>SLICE_X24Y17.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.476</twDelInfo><twComp>pencil_y<3></twComp><twBEL>pencil_y_0</twBEL></twPathDel><twPathDel><twSite>SLICE_X25Y17.A6</twSite><twDelType>net</twDelType><twFanCnt>4</twFanCnt><twDelInfo twEdge="twRising">0.615</twDelInfo><twComp>pencil_y<0></twComp></twPathDel><twPathDel><twSite>SLICE_X25Y17.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>Msub_GND_1_o_GND_1_o_sub_229_OUT</twComp><twBEL>Msub_GND_1_o_GND_1_o_sub_229_OUT</twBEL></twPathDel><twPathDel><twSite>SLICE_X26Y17.B5</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twRising">0.422</twDelInfo><twComp>Msub_GND_1_o_GND_1_o_sub_229_OUT</twComp></twPathDel><twPathDel><twSite>SLICE_X26Y17.COUT</twSite><twDelType>Topcyb</twDelType><twDelInfo twEdge="twRising">0.483</twDelInfo><twComp>GND_1_o_GND_1_o_sub_229_OUT<3></twComp><twBEL>Msub_GND_1_o_GND_1_o_sub_229_OUT_lut<0>1</twBEL><twBEL>Msub_GND_1_o_GND_1_o_sub_229_OUT_cy<0>_2</twBEL></twPathDel><twPathDel><twSite>SLICE_X26Y18.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.003</twDelInfo><twComp>Msub_GND_1_o_GND_1_o_sub_229_OUT_cy<0>3</twComp></twPathDel><twPathDel><twSite>SLICE_X26Y18.BQ</twSite><twDelType>Tito_logic</twDelType><twDelInfo twEdge="twRising">0.788</twDelInfo><twComp>GND_1_o_GND_1_o_sub_229_OUT<7></twComp><twBEL>Msub_GND_1_o_GND_1_o_sub_229_OUT_cy<0>_6</twBEL><twBEL>GND_1_o_GND_1_o_sub_229_OUT<5>_rt</twBEL></twPathDel><twPathDel><twSite>DSP48_X1Y5.B5</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.822</twDelInfo><twComp>GND_1_o_GND_1_o_sub_229_OUT<5></twComp></twPathDel><twPathDel><twSite>DSP48_X1Y5.M0</twSite><twDelType>Tdspdo_B_M</twDelType><twDelInfo twEdge="twRising">3.894</twDelInfo><twComp>Mmult_n0523</twComp><twBEL>Mmult_n0523</twBEL></twPathDel><twPathDel><twSite>SLICE_X24Y20.A6</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twRising">1.042</twDelInfo><twComp>n0523<0></twComp></twPathDel><twPathDel><twSite>SLICE_X24Y20.COUT</twSite><twDelType>Topcya</twDelType><twDelInfo twEdge="twRising">0.472</twDelInfo><twComp>ADDER_FOR_MULTADD_Madd_cy<3></twComp><twBEL>ADDER_FOR_MULTADD_Madd_lut<0></twBEL><twBEL>ADDER_FOR_MULTADD_Madd_cy<3></twBEL></twPathDel><twPathDel><twSite>SLICE_X24Y21.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.003</twDelInfo><twComp>ADDER_FOR_MULTADD_Madd_cy<3></twComp></twPathDel><twPathDel><twSite>SLICE_X24Y21.CMUX</twSite><twDelType>Tcinc</twDelType><twDelInfo twEdge="twRising">0.289</twDelInfo><twComp>ADDER_FOR_MULTADD_Madd_cy<7></twComp><twBEL>ADDER_FOR_MULTADD_Madd_cy<7></twBEL></twPathDel><twPathDel><twSite>SLICE_X28Y21.C3</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.680</twDelInfo><twComp>ADDER_FOR_MULTADD_Madd_6</twComp></twPathDel><twPathDel><twSite>SLICE_X28Y21.CMUX</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.298</twDelInfo><twComp>ADDERTREE_INTERNAL_Madd_71</twComp><twBEL>ADDERTREE_INTERNAL_Madd16</twBEL></twPathDel><twPathDel><twSite>SLICE_X28Y21.DX</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twRising">0.739</twDelInfo><twComp>ADDERTREE_INTERNAL_Madd16</twComp></twPathDel><twPathDel><twSite>SLICE_X28Y21.COUT</twSite><twDelType>Tdxcy</twDelType><twDelInfo twEdge="twRising">0.121</twDelInfo><twComp>ADDERTREE_INTERNAL_Madd_71</twComp><twBEL>ADDERTREE_INTERNAL_Madd1_cy<0>_6</twBEL></twPathDel><twPathDel><twSite>SLICE_X28Y22.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.003</twDelInfo><twComp>ADDERTREE_INTERNAL_Madd1_cy<0>7</twComp></twPathDel><twPathDel><twSite>SLICE_X28Y22.DQ</twSite><twDelType>Tito_logic</twDelType><twDelInfo twEdge="twRising">0.763</twDelInfo><twComp>ADDERTREE_INTERNAL_Madd_111</twComp><twBEL>ADDERTREE_INTERNAL_Madd1_cy<0>_10</twBEL><twBEL>ADDERTREE_INTERNAL_Madd_111_rt</twBEL></twPathDel><twPathDel><twSite>SLICE_X27Y23.B6</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.587</twDelInfo><twComp>ADDERTREE_INTERNAL_Madd_111</twComp></twPathDel><twPathDel><twSite>SLICE_X27Y23.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.373</twDelInfo><twComp>pmin_addr<11></twComp><twBEL>Mmux_pmin_addr[15]_GND_1_o_mux_292_OUT34</twBEL><twBEL>pmin_addr_11</twBEL></twPathDel><twLogDel>8.216</twLogDel><twRouteDel>4.916</twRouteDel><twTotDel>13.132</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="10.000">clk_BUFGP</twDestClk><twPctLog>62.6</twPctLog><twPctRoute>37.4</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="8"><twConstPath anchorID="9" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>-3.130</twSlack><twSrc BELType="FF">pencil_y_0</twSrc><twDest BELType="FF">pmin_addr_11</twDest><twTotPathDel>13.073</twTotPathDel><twClkSkew dest = "0.307" src = "0.329">0.022</twClkSkew><twDelConst>10.000</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.035</twClkUncert><twDetPath maxSiteLen="17" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>pencil_y_0</twSrc><twDest BELType='FF'>pmin_addr_11</twDest><twLogLvls>10</twLogLvls><twSrcSite>SLICE_X24Y17.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">clk_BUFGP</twSrcClk><twPathDel><twSite>SLICE_X24Y17.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.476</twDelInfo><twComp>pencil_y<3></twComp><twBEL>pencil_y_0</twBEL></twPathDel><twPathDel><twSite>SLICE_X25Y17.A6</twSite><twDelType>net</twDelType><twFanCnt>4</twFanCnt><twDelInfo twEdge="twRising">0.615</twDelInfo><twComp>pencil_y<0></twComp></twPathDel><twPathDel><twSite>SLICE_X25Y17.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>Msub_GND_1_o_GND_1_o_sub_229_OUT</twComp><twBEL>Msub_GND_1_o_GND_1_o_sub_229_OUT</twBEL></twPathDel><twPathDel><twSite>SLICE_X26Y17.B5</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twRising">0.422</twDelInfo><twComp>Msub_GND_1_o_GND_1_o_sub_229_OUT</twComp></twPathDel><twPathDel><twSite>SLICE_X26Y17.COUT</twSite><twDelType>Topcyb</twDelType><twDelInfo twEdge="twRising">0.483</twDelInfo><twComp>GND_1_o_GND_1_o_sub_229_OUT<3></twComp><twBEL>Msub_GND_1_o_GND_1_o_sub_229_OUT_lut<0>1</twBEL><twBEL>Msub_GND_1_o_GND_1_o_sub_229_OUT_cy<0>_2</twBEL></twPathDel><twPathDel><twSite>SLICE_X26Y18.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.003</twDelInfo><twComp>Msub_GND_1_o_GND_1_o_sub_229_OUT_cy<0>3</twComp></twPathDel><twPathDel><twSite>SLICE_X26Y18.BQ</twSite><twDelType>Tito_logic</twDelType><twDelInfo twEdge="twRising">0.788</twDelInfo><twComp>GND_1_o_GND_1_o_sub_229_OUT<7></twComp><twBEL>Msub_GND_1_o_GND_1_o_sub_229_OUT_cy<0>_6</twBEL><twBEL>GND_1_o_GND_1_o_sub_229_OUT<5>_rt</twBEL></twPathDel><twPathDel><twSite>DSP48_X1Y5.B5</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.822</twDelInfo><twComp>GND_1_o_GND_1_o_sub_229_OUT<5></twComp></twPathDel><twPathDel><twSite>DSP48_X1Y5.M0</twSite><twDelType>Tdspdo_B_M</twDelType><twDelInfo twEdge="twRising">3.894</twDelInfo><twComp>Mmult_n0523</twComp><twBEL>Mmult_n0523</twBEL></twPathDel><twPathDel><twSite>SLICE_X24Y20.AX</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twRising">1.174</twDelInfo><twComp>n0523<0></twComp></twPathDel><twPathDel><twSite>SLICE_X24Y20.COUT</twSite><twDelType>Taxcy</twDelType><twDelInfo twEdge="twRising">0.281</twDelInfo><twComp>ADDER_FOR_MULTADD_Madd_cy<3></twComp><twBEL>ADDER_FOR_MULTADD_Madd_cy<3></twBEL></twPathDel><twPathDel><twSite>SLICE_X24Y21.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.003</twDelInfo><twComp>ADDER_FOR_MULTADD_Madd_cy<3></twComp></twPathDel><twPathDel><twSite>SLICE_X24Y21.CMUX</twSite><twDelType>Tcinc</twDelType><twDelInfo twEdge="twRising">0.289</twDelInfo><twComp>ADDER_FOR_MULTADD_Madd_cy<7></twComp><twBEL>ADDER_FOR_MULTADD_Madd_cy<7></twBEL></twPathDel><twPathDel><twSite>SLICE_X28Y21.C3</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.680</twDelInfo><twComp>ADDER_FOR_MULTADD_Madd_6</twComp></twPathDel><twPathDel><twSite>SLICE_X28Y21.CMUX</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.298</twDelInfo><twComp>ADDERTREE_INTERNAL_Madd_71</twComp><twBEL>ADDERTREE_INTERNAL_Madd16</twBEL></twPathDel><twPathDel><twSite>SLICE_X28Y21.DX</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twRising">0.739</twDelInfo><twComp>ADDERTREE_INTERNAL_Madd16</twComp></twPathDel><twPathDel><twSite>SLICE_X28Y21.COUT</twSite><twDelType>Tdxcy</twDelType><twDelInfo twEdge="twRising">0.121</twDelInfo><twComp>ADDERTREE_INTERNAL_Madd_71</twComp><twBEL>ADDERTREE_INTERNAL_Madd1_cy<0>_6</twBEL></twPathDel><twPathDel><twSite>SLICE_X28Y22.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.003</twDelInfo><twComp>ADDERTREE_INTERNAL_Madd1_cy<0>7</twComp></twPathDel><twPathDel><twSite>SLICE_X28Y22.DQ</twSite><twDelType>Tito_logic</twDelType><twDelInfo twEdge="twRising">0.763</twDelInfo><twComp>ADDERTREE_INTERNAL_Madd_111</twComp><twBEL>ADDERTREE_INTERNAL_Madd1_cy<0>_10</twBEL><twBEL>ADDERTREE_INTERNAL_Madd_111_rt</twBEL></twPathDel><twPathDel><twSite>SLICE_X27Y23.B6</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.587</twDelInfo><twComp>ADDERTREE_INTERNAL_Madd_111</twComp></twPathDel><twPathDel><twSite>SLICE_X27Y23.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.373</twDelInfo><twComp>pmin_addr<11></twComp><twBEL>Mmux_pmin_addr[15]_GND_1_o_mux_292_OUT34</twBEL><twBEL>pmin_addr_11</twBEL></twPathDel><twLogDel>8.025</twLogDel><twRouteDel>5.048</twRouteDel><twTotDel>13.073</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="10.000">clk_BUFGP</twDestClk><twPctLog>61.4</twPctLog><twPctRoute>38.6</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="10"><twConstPath anchorID="11" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>-3.111</twSlack><twSrc BELType="FF">pencil_y_0</twSrc><twDest BELType="FF">pmin_addr_11</twDest><twTotPathDel>13.054</twTotPathDel><twClkSkew dest = "0.307" src = "0.329">0.022</twClkSkew><twDelConst>10.000</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.035</twClkUncert><twDetPath maxSiteLen="17" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>pencil_y_0</twSrc><twDest BELType='FF'>pmin_addr_11</twDest><twLogLvls>10</twLogLvls><twSrcSite>SLICE_X24Y17.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">clk_BUFGP</twSrcClk><twPathDel><twSite>SLICE_X24Y17.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.476</twDelInfo><twComp>pencil_y<3></twComp><twBEL>pencil_y_0</twBEL></twPathDel><twPathDel><twSite>SLICE_X25Y17.A6</twSite><twDelType>net</twDelType><twFanCnt>4</twFanCnt><twDelInfo twEdge="twRising">0.615</twDelInfo><twComp>pencil_y<0></twComp></twPathDel><twPathDel><twSite>SLICE_X25Y17.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>Msub_GND_1_o_GND_1_o_sub_229_OUT</twComp><twBEL>Msub_GND_1_o_GND_1_o_sub_229_OUT</twBEL></twPathDel><twPathDel><twSite>SLICE_X26Y17.B5</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twRising">0.422</twDelInfo><twComp>Msub_GND_1_o_GND_1_o_sub_229_OUT</twComp></twPathDel><twPathDel><twSite>SLICE_X26Y17.COUT</twSite><twDelType>Topcyb</twDelType><twDelInfo twEdge="twRising">0.483</twDelInfo><twComp>GND_1_o_GND_1_o_sub_229_OUT<3></twComp><twBEL>Msub_GND_1_o_GND_1_o_sub_229_OUT_lut<0>1</twBEL><twBEL>Msub_GND_1_o_GND_1_o_sub_229_OUT_cy<0>_2</twBEL></twPathDel><twPathDel><twSite>SLICE_X26Y18.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.003</twDelInfo><twComp>Msub_GND_1_o_GND_1_o_sub_229_OUT_cy<0>3</twComp></twPathDel><twPathDel><twSite>SLICE_X26Y18.BQ</twSite><twDelType>Tito_logic</twDelType><twDelInfo twEdge="twRising">0.788</twDelInfo><twComp>GND_1_o_GND_1_o_sub_229_OUT<7></twComp><twBEL>Msub_GND_1_o_GND_1_o_sub_229_OUT_cy<0>_6</twBEL><twBEL>GND_1_o_GND_1_o_sub_229_OUT<5>_rt</twBEL></twPathDel><twPathDel><twSite>DSP48_X1Y5.B5</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.822</twDelInfo><twComp>GND_1_o_GND_1_o_sub_229_OUT<5></twComp></twPathDel><twPathDel><twSite>DSP48_X1Y5.M0</twSite><twDelType>Tdspdo_B_M</twDelType><twDelInfo twEdge="twRising">3.894</twDelInfo><twComp>Mmult_n0523</twComp><twBEL>Mmult_n0523</twBEL></twPathDel><twPathDel><twSite>SLICE_X24Y20.A6</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twRising">1.042</twDelInfo><twComp>n0523<0></twComp></twPathDel><twPathDel><twSite>SLICE_X24Y20.COUT</twSite><twDelType>Topcya</twDelType><twDelInfo twEdge="twRising">0.472</twDelInfo><twComp>ADDER_FOR_MULTADD_Madd_cy<3></twComp><twBEL>ADDER_FOR_MULTADD_Madd_lut<0></twBEL><twBEL>ADDER_FOR_MULTADD_Madd_cy<3></twBEL></twPathDel><twPathDel><twSite>SLICE_X24Y21.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.003</twDelInfo><twComp>ADDER_FOR_MULTADD_Madd_cy<3></twComp></twPathDel><twPathDel><twSite>SLICE_X24Y21.BMUX</twSite><twDelType>Tcinb</twDelType><twDelInfo twEdge="twRising">0.277</twDelInfo><twComp>ADDER_FOR_MULTADD_Madd_cy<7></twComp><twBEL>ADDER_FOR_MULTADD_Madd_cy<7></twBEL></twPathDel><twPathDel><twSite>SLICE_X28Y21.B3</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.694</twDelInfo><twComp>ADDER_FOR_MULTADD_Madd_5</twComp></twPathDel><twPathDel><twSite>SLICE_X28Y21.BMUX</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.298</twDelInfo><twComp>ADDERTREE_INTERNAL_Madd_71</twComp><twBEL>ADDERTREE_INTERNAL_Madd15</twBEL></twPathDel><twPathDel><twSite>SLICE_X28Y21.C5</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twRising">0.455</twDelInfo><twComp>ADDERTREE_INTERNAL_Madd15</twComp></twPathDel><twPathDel><twSite>SLICE_X28Y21.COUT</twSite><twDelType>Topcyc</twDelType><twDelInfo twEdge="twRising">0.325</twDelInfo><twComp>ADDERTREE_INTERNAL_Madd_71</twComp><twBEL>ADDERTREE_INTERNAL_Madd1_lut<0>6</twBEL><twBEL>ADDERTREE_INTERNAL_Madd1_cy<0>_6</twBEL></twPathDel><twPathDel><twSite>SLICE_X28Y22.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.003</twDelInfo><twComp>ADDERTREE_INTERNAL_Madd1_cy<0>7</twComp></twPathDel><twPathDel><twSite>SLICE_X28Y22.DQ</twSite><twDelType>Tito_logic</twDelType><twDelInfo twEdge="twRising">0.763</twDelInfo><twComp>ADDERTREE_INTERNAL_Madd_111</twComp><twBEL>ADDERTREE_INTERNAL_Madd1_cy<0>_10</twBEL><twBEL>ADDERTREE_INTERNAL_Madd_111_rt</twBEL></twPathDel><twPathDel><twSite>SLICE_X27Y23.B6</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.587</twDelInfo><twComp>ADDERTREE_INTERNAL_Madd_111</twComp></twPathDel><twPathDel><twSite>SLICE_X27Y23.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.373</twDelInfo><twComp>pmin_addr<11></twComp><twBEL>Mmux_pmin_addr[15]_GND_1_o_mux_292_OUT34</twBEL><twBEL>pmin_addr_11</twBEL></twPathDel><twLogDel>8.408</twLogDel><twRouteDel>4.646</twRouteDel><twTotDel>13.054</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="10.000">clk_BUFGP</twDestClk><twPctLog>64.4</twPctLog><twPctRoute>35.6</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="204130" iCriticalPaths="204091" sType="EndPoint">Paths for end point pmin_addr_13 (SLICE_X29Y24.A6), 204130 paths
</twPathRptBanner><twPathRpt anchorID="12"><twConstPath anchorID="13" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>-3.075</twSlack><twSrc BELType="FF">pencil_y_0</twSrc><twDest BELType="FF">pmin_addr_13</twDest><twTotPathDel>13.025</twTotPathDel><twClkSkew dest = "0.314" src = "0.329">0.015</twClkSkew><twDelConst>10.000</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.035</twClkUncert><twDetPath maxSiteLen="17" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>pencil_y_0</twSrc><twDest BELType='FF'>pmin_addr_13</twDest><twLogLvls>11</twLogLvls><twSrcSite>SLICE_X24Y17.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">clk_BUFGP</twSrcClk><twPathDel><twSite>SLICE_X24Y17.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.476</twDelInfo><twComp>pencil_y<3></twComp><twBEL>pencil_y_0</twBEL></twPathDel><twPathDel><twSite>SLICE_X25Y17.A6</twSite><twDelType>net</twDelType><twFanCnt>4</twFanCnt><twDelInfo twEdge="twRising">0.615</twDelInfo><twComp>pencil_y<0></twComp></twPathDel><twPathDel><twSite>SLICE_X25Y17.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>Msub_GND_1_o_GND_1_o_sub_229_OUT</twComp><twBEL>Msub_GND_1_o_GND_1_o_sub_229_OUT</twBEL></twPathDel><twPathDel><twSite>SLICE_X26Y17.B5</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twRising">0.422</twDelInfo><twComp>Msub_GND_1_o_GND_1_o_sub_229_OUT</twComp></twPathDel><twPathDel><twSite>SLICE_X26Y17.COUT</twSite><twDelType>Topcyb</twDelType><twDelInfo twEdge="twRising">0.483</twDelInfo><twComp>GND_1_o_GND_1_o_sub_229_OUT<3></twComp><twBEL>Msub_GND_1_o_GND_1_o_sub_229_OUT_lut<0>1</twBEL><twBEL>Msub_GND_1_o_GND_1_o_sub_229_OUT_cy<0>_2</twBEL></twPathDel><twPathDel><twSite>SLICE_X26Y18.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.003</twDelInfo><twComp>Msub_GND_1_o_GND_1_o_sub_229_OUT_cy<0>3</twComp></twPathDel><twPathDel><twSite>SLICE_X26Y18.BQ</twSite><twDelType>Tito_logic</twDelType><twDelInfo twEdge="twRising">0.788</twDelInfo><twComp>GND_1_o_GND_1_o_sub_229_OUT<7></twComp><twBEL>Msub_GND_1_o_GND_1_o_sub_229_OUT_cy<0>_6</twBEL><twBEL>GND_1_o_GND_1_o_sub_229_OUT<5>_rt</twBEL></twPathDel><twPathDel><twSite>DSP48_X1Y5.B5</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.822</twDelInfo><twComp>GND_1_o_GND_1_o_sub_229_OUT<5></twComp></twPathDel><twPathDel><twSite>DSP48_X1Y5.M0</twSite><twDelType>Tdspdo_B_M</twDelType><twDelInfo twEdge="twRising">3.894</twDelInfo><twComp>Mmult_n0523</twComp><twBEL>Mmult_n0523</twBEL></twPathDel><twPathDel><twSite>SLICE_X24Y20.A6</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twRising">1.042</twDelInfo><twComp>n0523<0></twComp></twPathDel><twPathDel><twSite>SLICE_X24Y20.COUT</twSite><twDelType>Topcya</twDelType><twDelInfo twEdge="twRising">0.472</twDelInfo><twComp>ADDER_FOR_MULTADD_Madd_cy<3></twComp><twBEL>ADDER_FOR_MULTADD_Madd_lut<0></twBEL><twBEL>ADDER_FOR_MULTADD_Madd_cy<3></twBEL></twPathDel><twPathDel><twSite>SLICE_X24Y21.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.003</twDelInfo><twComp>ADDER_FOR_MULTADD_Madd_cy<3></twComp></twPathDel><twPathDel><twSite>SLICE_X24Y21.CMUX</twSite><twDelType>Tcinc</twDelType><twDelInfo twEdge="twRising">0.289</twDelInfo><twComp>ADDER_FOR_MULTADD_Madd_cy<7></twComp><twBEL>ADDER_FOR_MULTADD_Madd_cy<7></twBEL></twPathDel><twPathDel><twSite>SLICE_X28Y21.C3</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.680</twDelInfo><twComp>ADDER_FOR_MULTADD_Madd_6</twComp></twPathDel><twPathDel><twSite>SLICE_X28Y21.CMUX</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.298</twDelInfo><twComp>ADDERTREE_INTERNAL_Madd_71</twComp><twBEL>ADDERTREE_INTERNAL_Madd16</twBEL></twPathDel><twPathDel><twSite>SLICE_X28Y21.DX</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twRising">0.739</twDelInfo><twComp>ADDERTREE_INTERNAL_Madd16</twComp></twPathDel><twPathDel><twSite>SLICE_X28Y21.COUT</twSite><twDelType>Tdxcy</twDelType><twDelInfo twEdge="twRising">0.121</twDelInfo><twComp>ADDERTREE_INTERNAL_Madd_71</twComp><twBEL>ADDERTREE_INTERNAL_Madd1_cy<0>_6</twBEL></twPathDel><twPathDel><twSite>SLICE_X28Y22.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.003</twDelInfo><twComp>ADDERTREE_INTERNAL_Madd1_cy<0>7</twComp></twPathDel><twPathDel><twSite>SLICE_X28Y22.COUT</twSite><twDelType>Tbyp</twDelType><twDelInfo twEdge="twRising">0.091</twDelInfo><twComp>ADDERTREE_INTERNAL_Madd_111</twComp><twBEL>ADDERTREE_INTERNAL_Madd1_cy<0>_10</twBEL></twPathDel><twPathDel><twSite>SLICE_X28Y23.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.003</twDelInfo><twComp>ADDERTREE_INTERNAL_Madd1_cy<0>11</twComp></twPathDel><twPathDel><twSite>SLICE_X28Y23.BQ</twSite><twDelType>Tito_logic</twDelType><twDelInfo twEdge="twRising">0.751</twDelInfo><twComp>ADDERTREE_INTERNAL_Madd_131</twComp><twBEL>ADDERTREE_INTERNAL_Madd1_xor<0>_14</twBEL><twBEL>ADDERTREE_INTERNAL_Madd_131_rt</twBEL></twPathDel><twPathDel><twSite>SLICE_X29Y24.A6</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.398</twDelInfo><twComp>ADDERTREE_INTERNAL_Madd_131</twComp></twPathDel><twPathDel><twSite>SLICE_X29Y24.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.373</twDelInfo><twComp>pmin_addr<13></twComp><twBEL>Mmux_pmin_addr[15]_GND_1_o_mux_292_OUT54</twBEL><twBEL>pmin_addr_13</twBEL></twPathDel><twLogDel>8.295</twLogDel><twRouteDel>4.730</twRouteDel><twTotDel>13.025</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="10.000">clk_BUFGP</twDestClk><twPctLog>63.7</twPctLog><twPctRoute>36.3</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="14"><twConstPath anchorID="15" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>-3.075</twSlack><twSrc BELType="FF">pencil_y_0</twSrc><twDest BELType="FF">pmin_addr_13</twDest><twTotPathDel>13.025</twTotPathDel><twClkSkew dest = "0.314" src = "0.329">0.015</twClkSkew><twDelConst>10.000</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.035</twClkUncert><twDetPath maxSiteLen="17" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>pencil_y_0</twSrc><twDest BELType='FF'>pmin_addr_13</twDest><twLogLvls>11</twLogLvls><twSrcSite>SLICE_X24Y17.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">clk_BUFGP</twSrcClk><twPathDel><twSite>SLICE_X24Y17.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.476</twDelInfo><twComp>pencil_y<3></twComp><twBEL>pencil_y_0</twBEL></twPathDel><twPathDel><twSite>SLICE_X25Y17.A6</twSite><twDelType>net</twDelType><twFanCnt>4</twFanCnt><twDelInfo twEdge="twRising">0.615</twDelInfo><twComp>pencil_y<0></twComp></twPathDel><twPathDel><twSite>SLICE_X25Y17.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>Msub_GND_1_o_GND_1_o_sub_229_OUT</twComp><twBEL>Msub_GND_1_o_GND_1_o_sub_229_OUT</twBEL></twPathDel><twPathDel><twSite>SLICE_X26Y17.B5</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twRising">0.422</twDelInfo><twComp>Msub_GND_1_o_GND_1_o_sub_229_OUT</twComp></twPathDel><twPathDel><twSite>SLICE_X26Y17.COUT</twSite><twDelType>Topcyb</twDelType><twDelInfo twEdge="twRising">0.483</twDelInfo><twComp>GND_1_o_GND_1_o_sub_229_OUT<3></twComp><twBEL>Msub_GND_1_o_GND_1_o_sub_229_OUT_lut<0>1</twBEL><twBEL>Msub_GND_1_o_GND_1_o_sub_229_OUT_cy<0>_2</twBEL></twPathDel><twPathDel><twSite>SLICE_X26Y18.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.003</twDelInfo><twComp>Msub_GND_1_o_GND_1_o_sub_229_OUT_cy<0>3</twComp></twPathDel><twPathDel><twSite>SLICE_X26Y18.BQ</twSite><twDelType>Tito_logic</twDelType><twDelInfo twEdge="twRising">0.788</twDelInfo><twComp>GND_1_o_GND_1_o_sub_229_OUT<7></twComp><twBEL>Msub_GND_1_o_GND_1_o_sub_229_OUT_cy<0>_6</twBEL><twBEL>GND_1_o_GND_1_o_sub_229_OUT<5>_rt</twBEL></twPathDel><twPathDel><twSite>DSP48_X1Y5.B5</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.822</twDelInfo><twComp>GND_1_o_GND_1_o_sub_229_OUT<5></twComp></twPathDel><twPathDel><twSite>DSP48_X1Y5.M0</twSite><twDelType>Tdspdo_B_M</twDelType><twDelInfo twEdge="twRising">3.894</twDelInfo><twComp>Mmult_n0523</twComp><twBEL>Mmult_n0523</twBEL></twPathDel><twPathDel><twSite>SLICE_X24Y20.A6</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twRising">1.042</twDelInfo><twComp>n0523<0></twComp></twPathDel><twPathDel><twSite>SLICE_X24Y20.COUT</twSite><twDelType>Topcya</twDelType><twDelInfo twEdge="twRising">0.472</twDelInfo><twComp>ADDER_FOR_MULTADD_Madd_cy<3></twComp><twBEL>ADDER_FOR_MULTADD_Madd_lut<0></twBEL><twBEL>ADDER_FOR_MULTADD_Madd_cy<3></twBEL></twPathDel><twPathDel><twSite>SLICE_X24Y21.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.003</twDelInfo><twComp>ADDER_FOR_MULTADD_Madd_cy<3></twComp></twPathDel><twPathDel><twSite>SLICE_X24Y21.COUT</twSite><twDelType>Tbyp</twDelType><twDelInfo twEdge="twRising">0.091</twDelInfo><twComp>ADDER_FOR_MULTADD_Madd_cy<7></twComp><twBEL>ADDER_FOR_MULTADD_Madd_cy<7></twBEL></twPathDel><twPathDel><twSite>SLICE_X24Y22.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.003</twDelInfo><twComp>ADDER_FOR_MULTADD_Madd_cy<7></twComp></twPathDel><twPathDel><twSite>SLICE_X24Y22.CMUX</twSite><twDelType>Tcinc</twDelType><twDelInfo twEdge="twRising">0.289</twDelInfo><twComp>ADDER_FOR_MULTADD_Madd_cy<11></twComp><twBEL>ADDER_FOR_MULTADD_Madd_cy<11></twBEL></twPathDel><twPathDel><twSite>SLICE_X28Y22.C3</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.680</twDelInfo><twComp>ADDER_FOR_MULTADD_Madd_10</twComp></twPathDel><twPathDel><twSite>SLICE_X28Y22.CMUX</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.298</twDelInfo><twComp>ADDERTREE_INTERNAL_Madd_111</twComp><twBEL>ADDERTREE_INTERNAL_Madd110</twBEL></twPathDel><twPathDel><twSite>SLICE_X28Y22.DX</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twRising">0.739</twDelInfo><twComp>ADDERTREE_INTERNAL_Madd110</twComp></twPathDel><twPathDel><twSite>SLICE_X28Y22.COUT</twSite><twDelType>Tdxcy</twDelType><twDelInfo twEdge="twRising">0.121</twDelInfo><twComp>ADDERTREE_INTERNAL_Madd_111</twComp><twBEL>ADDERTREE_INTERNAL_Madd1_cy<0>_10</twBEL></twPathDel><twPathDel><twSite>SLICE_X28Y23.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.003</twDelInfo><twComp>ADDERTREE_INTERNAL_Madd1_cy<0>11</twComp></twPathDel><twPathDel><twSite>SLICE_X28Y23.BQ</twSite><twDelType>Tito_logic</twDelType><twDelInfo twEdge="twRising">0.751</twDelInfo><twComp>ADDERTREE_INTERNAL_Madd_131</twComp><twBEL>ADDERTREE_INTERNAL_Madd1_xor<0>_14</twBEL><twBEL>ADDERTREE_INTERNAL_Madd_131_rt</twBEL></twPathDel><twPathDel><twSite>SLICE_X29Y24.A6</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.398</twDelInfo><twComp>ADDERTREE_INTERNAL_Madd_131</twComp></twPathDel><twPathDel><twSite>SLICE_X29Y24.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.373</twDelInfo><twComp>pmin_addr<13></twComp><twBEL>Mmux_pmin_addr[15]_GND_1_o_mux_292_OUT54</twBEL><twBEL>pmin_addr_13</twBEL></twPathDel><twLogDel>8.295</twLogDel><twRouteDel>4.730</twRouteDel><twTotDel>13.025</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="10.000">clk_BUFGP</twDestClk><twPctLog>63.7</twPctLog><twPctRoute>36.3</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="16"><twConstPath anchorID="17" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>-3.016</twSlack><twSrc BELType="FF">pencil_y_0</twSrc><twDest BELType="FF">pmin_addr_13</twDest><twTotPathDel>12.966</twTotPathDel><twClkSkew dest = "0.314" src = "0.329">0.015</twClkSkew><twDelConst>10.000</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.035</twClkUncert><twDetPath maxSiteLen="17" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>pencil_y_0</twSrc><twDest BELType='FF'>pmin_addr_13</twDest><twLogLvls>11</twLogLvls><twSrcSite>SLICE_X24Y17.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">clk_BUFGP</twSrcClk><twPathDel><twSite>SLICE_X24Y17.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.476</twDelInfo><twComp>pencil_y<3></twComp><twBEL>pencil_y_0</twBEL></twPathDel><twPathDel><twSite>SLICE_X25Y17.A6</twSite><twDelType>net</twDelType><twFanCnt>4</twFanCnt><twDelInfo twEdge="twRising">0.615</twDelInfo><twComp>pencil_y<0></twComp></twPathDel><twPathDel><twSite>SLICE_X25Y17.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>Msub_GND_1_o_GND_1_o_sub_229_OUT</twComp><twBEL>Msub_GND_1_o_GND_1_o_sub_229_OUT</twBEL></twPathDel><twPathDel><twSite>SLICE_X26Y17.B5</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twRising">0.422</twDelInfo><twComp>Msub_GND_1_o_GND_1_o_sub_229_OUT</twComp></twPathDel><twPathDel><twSite>SLICE_X26Y17.COUT</twSite><twDelType>Topcyb</twDelType><twDelInfo twEdge="twRising">0.483</twDelInfo><twComp>GND_1_o_GND_1_o_sub_229_OUT<3></twComp><twBEL>Msub_GND_1_o_GND_1_o_sub_229_OUT_lut<0>1</twBEL><twBEL>Msub_GND_1_o_GND_1_o_sub_229_OUT_cy<0>_2</twBEL></twPathDel><twPathDel><twSite>SLICE_X26Y18.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.003</twDelInfo><twComp>Msub_GND_1_o_GND_1_o_sub_229_OUT_cy<0>3</twComp></twPathDel><twPathDel><twSite>SLICE_X26Y18.BQ</twSite><twDelType>Tito_logic</twDelType><twDelInfo twEdge="twRising">0.788</twDelInfo><twComp>GND_1_o_GND_1_o_sub_229_OUT<7></twComp><twBEL>Msub_GND_1_o_GND_1_o_sub_229_OUT_cy<0>_6</twBEL><twBEL>GND_1_o_GND_1_o_sub_229_OUT<5>_rt</twBEL></twPathDel><twPathDel><twSite>DSP48_X1Y5.B5</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.822</twDelInfo><twComp>GND_1_o_GND_1_o_sub_229_OUT<5></twComp></twPathDel><twPathDel><twSite>DSP48_X1Y5.M0</twSite><twDelType>Tdspdo_B_M</twDelType><twDelInfo twEdge="twRising">3.894</twDelInfo><twComp>Mmult_n0523</twComp><twBEL>Mmult_n0523</twBEL></twPathDel><twPathDel><twSite>SLICE_X24Y20.AX</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twRising">1.174</twDelInfo><twComp>n0523<0></twComp></twPathDel><twPathDel><twSite>SLICE_X24Y20.COUT</twSite><twDelType>Taxcy</twDelType><twDelInfo twEdge="twRising">0.281</twDelInfo><twComp>ADDER_FOR_MULTADD_Madd_cy<3></twComp><twBEL>ADDER_FOR_MULTADD_Madd_cy<3></twBEL></twPathDel><twPathDel><twSite>SLICE_X24Y21.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.003</twDelInfo><twComp>ADDER_FOR_MULTADD_Madd_cy<3></twComp></twPathDel><twPathDel><twSite>SLICE_X24Y21.COUT</twSite><twDelType>Tbyp</twDelType><twDelInfo twEdge="twRising">0.091</twDelInfo><twComp>ADDER_FOR_MULTADD_Madd_cy<7></twComp><twBEL>ADDER_FOR_MULTADD_Madd_cy<7></twBEL></twPathDel><twPathDel><twSite>SLICE_X24Y22.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.003</twDelInfo><twComp>ADDER_FOR_MULTADD_Madd_cy<7></twComp></twPathDel><twPathDel><twSite>SLICE_X24Y22.CMUX</twSite><twDelType>Tcinc</twDelType><twDelInfo twEdge="twRising">0.289</twDelInfo><twComp>ADDER_FOR_MULTADD_Madd_cy<11></twComp><twBEL>ADDER_FOR_MULTADD_Madd_cy<11></twBEL></twPathDel><twPathDel><twSite>SLICE_X28Y22.C3</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.680</twDelInfo><twComp>ADDER_FOR_MULTADD_Madd_10</twComp></twPathDel><twPathDel><twSite>SLICE_X28Y22.CMUX</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.298</twDelInfo><twComp>ADDERTREE_INTERNAL_Madd_111</twComp><twBEL>ADDERTREE_INTERNAL_Madd110</twBEL></twPathDel><twPathDel><twSite>SLICE_X28Y22.DX</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twRising">0.739</twDelInfo><twComp>ADDERTREE_INTERNAL_Madd110</twComp></twPathDel><twPathDel><twSite>SLICE_X28Y22.COUT</twSite><twDelType>Tdxcy</twDelType><twDelInfo twEdge="twRising">0.121</twDelInfo><twComp>ADDERTREE_INTERNAL_Madd_111</twComp><twBEL>ADDERTREE_INTERNAL_Madd1_cy<0>_10</twBEL></twPathDel><twPathDel><twSite>SLICE_X28Y23.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.003</twDelInfo><twComp>ADDERTREE_INTERNAL_Madd1_cy<0>11</twComp></twPathDel><twPathDel><twSite>SLICE_X28Y23.BQ</twSite><twDelType>Tito_logic</twDelType><twDelInfo twEdge="twRising">0.751</twDelInfo><twComp>ADDERTREE_INTERNAL_Madd_131</twComp><twBEL>ADDERTREE_INTERNAL_Madd1_xor<0>_14</twBEL><twBEL>ADDERTREE_INTERNAL_Madd_131_rt</twBEL></twPathDel><twPathDel><twSite>SLICE_X29Y24.A6</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.398</twDelInfo><twComp>ADDERTREE_INTERNAL_Madd_131</twComp></twPathDel><twPathDel><twSite>SLICE_X29Y24.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.373</twDelInfo><twComp>pmin_addr<13></twComp><twBEL>Mmux_pmin_addr[15]_GND_1_o_mux_292_OUT54</twBEL><twBEL>pmin_addr_13</twBEL></twPathDel><twLogDel>8.104</twLogDel><twRouteDel>4.862</twRouteDel><twTotDel>12.966</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="10.000">clk_BUFGP</twDestClk><twPctLog>62.5</twPctLog><twPctRoute>37.5</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="123548" iCriticalPaths="123518" sType="EndPoint">Paths for end point pmin_addr_10 (SLICE_X29Y22.B6), 123548 paths
</twPathRptBanner><twPathRpt anchorID="18"><twConstPath anchorID="19" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>-2.945</twSlack><twSrc BELType="FF">pencil_y_0</twSrc><twDest BELType="FF">pmin_addr_10</twDest><twTotPathDel>12.897</twTotPathDel><twClkSkew dest = "0.316" src = "0.329">0.013</twClkSkew><twDelConst>10.000</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.035</twClkUncert><twDetPath maxSiteLen="17" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>pencil_y_0</twSrc><twDest BELType='FF'>pmin_addr_10</twDest><twLogLvls>10</twLogLvls><twSrcSite>SLICE_X24Y17.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">clk_BUFGP</twSrcClk><twPathDel><twSite>SLICE_X24Y17.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.476</twDelInfo><twComp>pencil_y<3></twComp><twBEL>pencil_y_0</twBEL></twPathDel><twPathDel><twSite>SLICE_X25Y17.A6</twSite><twDelType>net</twDelType><twFanCnt>4</twFanCnt><twDelInfo twEdge="twRising">0.615</twDelInfo><twComp>pencil_y<0></twComp></twPathDel><twPathDel><twSite>SLICE_X25Y17.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>Msub_GND_1_o_GND_1_o_sub_229_OUT</twComp><twBEL>Msub_GND_1_o_GND_1_o_sub_229_OUT</twBEL></twPathDel><twPathDel><twSite>SLICE_X26Y17.B5</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twRising">0.422</twDelInfo><twComp>Msub_GND_1_o_GND_1_o_sub_229_OUT</twComp></twPathDel><twPathDel><twSite>SLICE_X26Y17.COUT</twSite><twDelType>Topcyb</twDelType><twDelInfo twEdge="twRising">0.483</twDelInfo><twComp>GND_1_o_GND_1_o_sub_229_OUT<3></twComp><twBEL>Msub_GND_1_o_GND_1_o_sub_229_OUT_lut<0>1</twBEL><twBEL>Msub_GND_1_o_GND_1_o_sub_229_OUT_cy<0>_2</twBEL></twPathDel><twPathDel><twSite>SLICE_X26Y18.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.003</twDelInfo><twComp>Msub_GND_1_o_GND_1_o_sub_229_OUT_cy<0>3</twComp></twPathDel><twPathDel><twSite>SLICE_X26Y18.BQ</twSite><twDelType>Tito_logic</twDelType><twDelInfo twEdge="twRising">0.788</twDelInfo><twComp>GND_1_o_GND_1_o_sub_229_OUT<7></twComp><twBEL>Msub_GND_1_o_GND_1_o_sub_229_OUT_cy<0>_6</twBEL><twBEL>GND_1_o_GND_1_o_sub_229_OUT<5>_rt</twBEL></twPathDel><twPathDel><twSite>DSP48_X1Y5.B5</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.822</twDelInfo><twComp>GND_1_o_GND_1_o_sub_229_OUT<5></twComp></twPathDel><twPathDel><twSite>DSP48_X1Y5.M0</twSite><twDelType>Tdspdo_B_M</twDelType><twDelInfo twEdge="twRising">3.894</twDelInfo><twComp>Mmult_n0523</twComp><twBEL>Mmult_n0523</twBEL></twPathDel><twPathDel><twSite>SLICE_X24Y20.A6</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twRising">1.042</twDelInfo><twComp>n0523<0></twComp></twPathDel><twPathDel><twSite>SLICE_X24Y20.COUT</twSite><twDelType>Topcya</twDelType><twDelInfo twEdge="twRising">0.472</twDelInfo><twComp>ADDER_FOR_MULTADD_Madd_cy<3></twComp><twBEL>ADDER_FOR_MULTADD_Madd_lut<0></twBEL><twBEL>ADDER_FOR_MULTADD_Madd_cy<3></twBEL></twPathDel><twPathDel><twSite>SLICE_X24Y21.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.003</twDelInfo><twComp>ADDER_FOR_MULTADD_Madd_cy<3></twComp></twPathDel><twPathDel><twSite>SLICE_X24Y21.CMUX</twSite><twDelType>Tcinc</twDelType><twDelInfo twEdge="twRising">0.289</twDelInfo><twComp>ADDER_FOR_MULTADD_Madd_cy<7></twComp><twBEL>ADDER_FOR_MULTADD_Madd_cy<7></twBEL></twPathDel><twPathDel><twSite>SLICE_X28Y21.C3</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.680</twDelInfo><twComp>ADDER_FOR_MULTADD_Madd_6</twComp></twPathDel><twPathDel><twSite>SLICE_X28Y21.CMUX</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.298</twDelInfo><twComp>ADDERTREE_INTERNAL_Madd_71</twComp><twBEL>ADDERTREE_INTERNAL_Madd16</twBEL></twPathDel><twPathDel><twSite>SLICE_X28Y21.DX</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twRising">0.739</twDelInfo><twComp>ADDERTREE_INTERNAL_Madd16</twComp></twPathDel><twPathDel><twSite>SLICE_X28Y21.COUT</twSite><twDelType>Tdxcy</twDelType><twDelInfo twEdge="twRising">0.121</twDelInfo><twComp>ADDERTREE_INTERNAL_Madd_71</twComp><twBEL>ADDERTREE_INTERNAL_Madd1_cy<0>_6</twBEL></twPathDel><twPathDel><twSite>SLICE_X28Y22.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.003</twDelInfo><twComp>ADDERTREE_INTERNAL_Madd1_cy<0>7</twComp></twPathDel><twPathDel><twSite>SLICE_X28Y22.CQ</twSite><twDelType>Tito_logic</twDelType><twDelInfo twEdge="twRising">0.763</twDelInfo><twComp>ADDERTREE_INTERNAL_Madd_111</twComp><twBEL>ADDERTREE_INTERNAL_Madd1_cy<0>_10</twBEL><twBEL>ADDERTREE_INTERNAL_Madd_101_rt</twBEL></twPathDel><twPathDel><twSite>SLICE_X29Y22.B6</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.352</twDelInfo><twComp>ADDERTREE_INTERNAL_Madd_101</twComp></twPathDel><twPathDel><twSite>SLICE_X29Y22.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.373</twDelInfo><twComp>pmin_addr<10></twComp><twBEL>Mmux_pmin_addr[15]_GND_1_o_mux_292_OUT24</twBEL><twBEL>pmin_addr_10</twBEL></twPathDel><twLogDel>8.216</twLogDel><twRouteDel>4.681</twRouteDel><twTotDel>12.897</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="10.000">clk_BUFGP</twDestClk><twPctLog>63.7</twPctLog><twPctRoute>36.3</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="20"><twConstPath anchorID="21" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>-2.886</twSlack><twSrc BELType="FF">pencil_y_0</twSrc><twDest BELType="FF">pmin_addr_10</twDest><twTotPathDel>12.838</twTotPathDel><twClkSkew dest = "0.316" src = "0.329">0.013</twClkSkew><twDelConst>10.000</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.035</twClkUncert><twDetPath maxSiteLen="17" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>pencil_y_0</twSrc><twDest BELType='FF'>pmin_addr_10</twDest><twLogLvls>10</twLogLvls><twSrcSite>SLICE_X24Y17.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">clk_BUFGP</twSrcClk><twPathDel><twSite>SLICE_X24Y17.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.476</twDelInfo><twComp>pencil_y<3></twComp><twBEL>pencil_y_0</twBEL></twPathDel><twPathDel><twSite>SLICE_X25Y17.A6</twSite><twDelType>net</twDelType><twFanCnt>4</twFanCnt><twDelInfo twEdge="twRising">0.615</twDelInfo><twComp>pencil_y<0></twComp></twPathDel><twPathDel><twSite>SLICE_X25Y17.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>Msub_GND_1_o_GND_1_o_sub_229_OUT</twComp><twBEL>Msub_GND_1_o_GND_1_o_sub_229_OUT</twBEL></twPathDel><twPathDel><twSite>SLICE_X26Y17.B5</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twRising">0.422</twDelInfo><twComp>Msub_GND_1_o_GND_1_o_sub_229_OUT</twComp></twPathDel><twPathDel><twSite>SLICE_X26Y17.COUT</twSite><twDelType>Topcyb</twDelType><twDelInfo twEdge="twRising">0.483</twDelInfo><twComp>GND_1_o_GND_1_o_sub_229_OUT<3></twComp><twBEL>Msub_GND_1_o_GND_1_o_sub_229_OUT_lut<0>1</twBEL><twBEL>Msub_GND_1_o_GND_1_o_sub_229_OUT_cy<0>_2</twBEL></twPathDel><twPathDel><twSite>SLICE_X26Y18.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.003</twDelInfo><twComp>Msub_GND_1_o_GND_1_o_sub_229_OUT_cy<0>3</twComp></twPathDel><twPathDel><twSite>SLICE_X26Y18.BQ</twSite><twDelType>Tito_logic</twDelType><twDelInfo twEdge="twRising">0.788</twDelInfo><twComp>GND_1_o_GND_1_o_sub_229_OUT<7></twComp><twBEL>Msub_GND_1_o_GND_1_o_sub_229_OUT_cy<0>_6</twBEL><twBEL>GND_1_o_GND_1_o_sub_229_OUT<5>_rt</twBEL></twPathDel><twPathDel><twSite>DSP48_X1Y5.B5</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.822</twDelInfo><twComp>GND_1_o_GND_1_o_sub_229_OUT<5></twComp></twPathDel><twPathDel><twSite>DSP48_X1Y5.M0</twSite><twDelType>Tdspdo_B_M</twDelType><twDelInfo twEdge="twRising">3.894</twDelInfo><twComp>Mmult_n0523</twComp><twBEL>Mmult_n0523</twBEL></twPathDel><twPathDel><twSite>SLICE_X24Y20.AX</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twRising">1.174</twDelInfo><twComp>n0523<0></twComp></twPathDel><twPathDel><twSite>SLICE_X24Y20.COUT</twSite><twDelType>Taxcy</twDelType><twDelInfo twEdge="twRising">0.281</twDelInfo><twComp>ADDER_FOR_MULTADD_Madd_cy<3></twComp><twBEL>ADDER_FOR_MULTADD_Madd_cy<3></twBEL></twPathDel><twPathDel><twSite>SLICE_X24Y21.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.003</twDelInfo><twComp>ADDER_FOR_MULTADD_Madd_cy<3></twComp></twPathDel><twPathDel><twSite>SLICE_X24Y21.CMUX</twSite><twDelType>Tcinc</twDelType><twDelInfo twEdge="twRising">0.289</twDelInfo><twComp>ADDER_FOR_MULTADD_Madd_cy<7></twComp><twBEL>ADDER_FOR_MULTADD_Madd_cy<7></twBEL></twPathDel><twPathDel><twSite>SLICE_X28Y21.C3</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.680</twDelInfo><twComp>ADDER_FOR_MULTADD_Madd_6</twComp></twPathDel><twPathDel><twSite>SLICE_X28Y21.CMUX</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.298</twDelInfo><twComp>ADDERTREE_INTERNAL_Madd_71</twComp><twBEL>ADDERTREE_INTERNAL_Madd16</twBEL></twPathDel><twPathDel><twSite>SLICE_X28Y21.DX</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twRising">0.739</twDelInfo><twComp>ADDERTREE_INTERNAL_Madd16</twComp></twPathDel><twPathDel><twSite>SLICE_X28Y21.COUT</twSite><twDelType>Tdxcy</twDelType><twDelInfo twEdge="twRising">0.121</twDelInfo><twComp>ADDERTREE_INTERNAL_Madd_71</twComp><twBEL>ADDERTREE_INTERNAL_Madd1_cy<0>_6</twBEL></twPathDel><twPathDel><twSite>SLICE_X28Y22.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.003</twDelInfo><twComp>ADDERTREE_INTERNAL_Madd1_cy<0>7</twComp></twPathDel><twPathDel><twSite>SLICE_X28Y22.CQ</twSite><twDelType>Tito_logic</twDelType><twDelInfo twEdge="twRising">0.763</twDelInfo><twComp>ADDERTREE_INTERNAL_Madd_111</twComp><twBEL>ADDERTREE_INTERNAL_Madd1_cy<0>_10</twBEL><twBEL>ADDERTREE_INTERNAL_Madd_101_rt</twBEL></twPathDel><twPathDel><twSite>SLICE_X29Y22.B6</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.352</twDelInfo><twComp>ADDERTREE_INTERNAL_Madd_101</twComp></twPathDel><twPathDel><twSite>SLICE_X29Y22.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.373</twDelInfo><twComp>pmin_addr<10></twComp><twBEL>Mmux_pmin_addr[15]_GND_1_o_mux_292_OUT24</twBEL><twBEL>pmin_addr_10</twBEL></twPathDel><twLogDel>8.025</twLogDel><twRouteDel>4.813</twRouteDel><twTotDel>12.838</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="10.000">clk_BUFGP</twDestClk><twPctLog>62.5</twPctLog><twPctRoute>37.5</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRpt anchorID="22"><twConstPath anchorID="23" twDataPathType="twDataPathMaxDelay" constType="period"><twSlack>-2.867</twSlack><twSrc BELType="FF">pencil_y_0</twSrc><twDest BELType="FF">pmin_addr_10</twDest><twTotPathDel>12.819</twTotPathDel><twClkSkew dest = "0.316" src = "0.329">0.013</twClkSkew><twDelConst>10.000</twDelConst><twClkUncert fSysJit="0.070" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE">0.035</twClkUncert><twDetPath maxSiteLen="17" twPathCritProcCorner=" at Slow Process Corner"><twSrc BELType='FF'>pencil_y_0</twSrc><twDest BELType='FF'>pmin_addr_10</twDest><twLogLvls>10</twLogLvls><twSrcSite>SLICE_X24Y17.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="0.000">clk_BUFGP</twSrcClk><twPathDel><twSite>SLICE_X24Y17.AQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twRising">0.476</twDelInfo><twComp>pencil_y<3></twComp><twBEL>pencil_y_0</twBEL></twPathDel><twPathDel><twSite>SLICE_X25Y17.A6</twSite><twDelType>net</twDelType><twFanCnt>4</twFanCnt><twDelInfo twEdge="twRising">0.615</twDelInfo><twComp>pencil_y<0></twComp></twPathDel><twPathDel><twSite>SLICE_X25Y17.A</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.259</twDelInfo><twComp>Msub_GND_1_o_GND_1_o_sub_229_OUT</twComp><twBEL>Msub_GND_1_o_GND_1_o_sub_229_OUT</twBEL></twPathDel><twPathDel><twSite>SLICE_X26Y17.B5</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twRising">0.422</twDelInfo><twComp>Msub_GND_1_o_GND_1_o_sub_229_OUT</twComp></twPathDel><twPathDel><twSite>SLICE_X26Y17.COUT</twSite><twDelType>Topcyb</twDelType><twDelInfo twEdge="twRising">0.483</twDelInfo><twComp>GND_1_o_GND_1_o_sub_229_OUT<3></twComp><twBEL>Msub_GND_1_o_GND_1_o_sub_229_OUT_lut<0>1</twBEL><twBEL>Msub_GND_1_o_GND_1_o_sub_229_OUT_cy<0>_2</twBEL></twPathDel><twPathDel><twSite>SLICE_X26Y18.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.003</twDelInfo><twComp>Msub_GND_1_o_GND_1_o_sub_229_OUT_cy<0>3</twComp></twPathDel><twPathDel><twSite>SLICE_X26Y18.BQ</twSite><twDelType>Tito_logic</twDelType><twDelInfo twEdge="twRising">0.788</twDelInfo><twComp>GND_1_o_GND_1_o_sub_229_OUT<7></twComp><twBEL>Msub_GND_1_o_GND_1_o_sub_229_OUT_cy<0>_6</twBEL><twBEL>GND_1_o_GND_1_o_sub_229_OUT<5>_rt</twBEL></twPathDel><twPathDel><twSite>DSP48_X1Y5.B5</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.822</twDelInfo><twComp>GND_1_o_GND_1_o_sub_229_OUT<5></twComp></twPathDel><twPathDel><twSite>DSP48_X1Y5.M0</twSite><twDelType>Tdspdo_B_M</twDelType><twDelInfo twEdge="twRising">3.894</twDelInfo><twComp>Mmult_n0523</twComp><twBEL>Mmult_n0523</twBEL></twPathDel><twPathDel><twSite>SLICE_X24Y20.A6</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twRising">1.042</twDelInfo><twComp>n0523<0></twComp></twPathDel><twPathDel><twSite>SLICE_X24Y20.COUT</twSite><twDelType>Topcya</twDelType><twDelInfo twEdge="twRising">0.472</twDelInfo><twComp>ADDER_FOR_MULTADD_Madd_cy<3></twComp><twBEL>ADDER_FOR_MULTADD_Madd_lut<0></twBEL><twBEL>ADDER_FOR_MULTADD_Madd_cy<3></twBEL></twPathDel><twPathDel><twSite>SLICE_X24Y21.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.003</twDelInfo><twComp>ADDER_FOR_MULTADD_Madd_cy<3></twComp></twPathDel><twPathDel><twSite>SLICE_X24Y21.BMUX</twSite><twDelType>Tcinb</twDelType><twDelInfo twEdge="twRising">0.277</twDelInfo><twComp>ADDER_FOR_MULTADD_Madd_cy<7></twComp><twBEL>ADDER_FOR_MULTADD_Madd_cy<7></twBEL></twPathDel><twPathDel><twSite>SLICE_X28Y21.B3</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.694</twDelInfo><twComp>ADDER_FOR_MULTADD_Madd_5</twComp></twPathDel><twPathDel><twSite>SLICE_X28Y21.BMUX</twSite><twDelType>Tilo</twDelType><twDelInfo twEdge="twRising">0.298</twDelInfo><twComp>ADDERTREE_INTERNAL_Madd_71</twComp><twBEL>ADDERTREE_INTERNAL_Madd15</twBEL></twPathDel><twPathDel><twSite>SLICE_X28Y21.C5</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twRising">0.455</twDelInfo><twComp>ADDERTREE_INTERNAL_Madd15</twComp></twPathDel><twPathDel><twSite>SLICE_X28Y21.COUT</twSite><twDelType>Topcyc</twDelType><twDelInfo twEdge="twRising">0.325</twDelInfo><twComp>ADDERTREE_INTERNAL_Madd_71</twComp><twBEL>ADDERTREE_INTERNAL_Madd1_lut<0>6</twBEL><twBEL>ADDERTREE_INTERNAL_Madd1_cy<0>_6</twBEL></twPathDel><twPathDel><twSite>SLICE_X28Y22.CIN</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.003</twDelInfo><twComp>ADDERTREE_INTERNAL_Madd1_cy<0>7</twComp></twPathDel><twPathDel><twSite>SLICE_X28Y22.CQ</twSite><twDelType>Tito_logic</twDelType><twDelInfo twEdge="twRising">0.763</twDelInfo><twComp>ADDERTREE_INTERNAL_Madd_111</twComp><twBEL>ADDERTREE_INTERNAL_Madd1_cy<0>_10</twBEL><twBEL>ADDERTREE_INTERNAL_Madd_101_rt</twBEL></twPathDel><twPathDel><twSite>SLICE_X29Y22.B6</twSite><twDelType>net</twDelType><twFanCnt>1</twFanCnt><twDelInfo twEdge="twRising">0.352</twDelInfo><twComp>ADDERTREE_INTERNAL_Madd_101</twComp></twPathDel><twPathDel><twSite>SLICE_X29Y22.CLK</twSite><twDelType>Tas</twDelType><twDelInfo twEdge="twRising">0.373</twDelInfo><twComp>pmin_addr<10></twComp><twBEL>Mmux_pmin_addr[15]_GND_1_o_mux_292_OUT24</twBEL><twBEL>pmin_addr_10</twBEL></twPathDel><twLogDel>8.408</twLogDel><twRouteDel>4.411</twRouteDel><twTotDel>12.819</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="10.000">clk_BUFGP</twDestClk><twPctLog>65.6</twPctLog><twPctRoute>34.4</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner sType="PathClass">Hold Paths: TS_sys_clk_pin = PERIOD TIMEGRP "sys_clk_pin" 100 MHz HIGH 50%;
</twPathRptBanner><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point joy/clk_joy (SLICE_X0Y24.D6), 1 path
</twPathRptBanner><twPathRpt anchorID="24"><twConstPath anchorID="25" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.418</twSlack><twSrc BELType="FF">joy/clk_joy</twSrc><twDest BELType="FF">joy/clk_joy</twDest><twTotPathDel>0.418</twTotPathDel><twClkSkew>0.000</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="15" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='FF'>joy/clk_joy</twSrc><twDest BELType='FF'>joy/clk_joy</twDest><twLogLvls>1</twLogLvls><twSrcSite>SLICE_X0Y24.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="10.000">clk_BUFGP</twSrcClk><twPathDel><twSite>SLICE_X0Y24.DQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twFalling">0.200</twDelInfo><twComp>joy/clk_joy</twComp><twBEL>joy/clk_joy</twBEL></twPathDel><twPathDel><twSite>SLICE_X0Y24.D6</twSite><twDelType>net</twDelType><twFanCnt>3</twFanCnt><twDelInfo twEdge="twFalling">0.028</twDelInfo><twComp>joy/clk_joy</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>SLICE_X0Y24.CLK</twSite><twDelType>Tah</twDelType><twDelInfo twEdge="twFalling">0.190</twDelInfo><twComp>joy/clk_joy</twComp><twBEL>joy/clk_joy_BUFG_LUT1_INV_0</twBEL><twBEL>joy/clk_joy</twBEL></twPathDel><twLogDel>0.390</twLogDel><twRouteDel>0.028</twRouteDel><twTotDel>0.418</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="10.000">clk_BUFGP</twDestClk><twPctLog>93.3</twPctLog><twPctRoute>6.7</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point counter_vga (SLICE_X19Y37.D6), 1 path
</twPathRptBanner><twPathRpt anchorID="26"><twConstPath anchorID="27" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.438</twSlack><twSrc BELType="FF">counter_vga</twSrc><twDest BELType="FF">counter_vga</twDest><twTotPathDel>0.438</twTotPathDel><twClkSkew>0.000</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="16" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='FF'>counter_vga</twSrc><twDest BELType='FF'>counter_vga</twDest><twLogLvls>1</twLogLvls><twSrcSite>SLICE_X19Y37.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="10.000">clk_BUFGP</twSrcClk><twPathDel><twSite>SLICE_X19Y37.DQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twFalling">0.198</twDelInfo><twComp>counter_vga</twComp><twBEL>counter_vga</twBEL></twPathDel><twPathDel><twSite>SLICE_X19Y37.D6</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twFalling">0.025</twDelInfo><twComp>counter_vga</twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>SLICE_X19Y37.CLK</twSite><twDelType>Tah</twDelType><twDelInfo twEdge="twFalling">0.215</twDelInfo><twComp>counter_vga</twComp><twBEL>counter_vga_INV_12_o1_INV_0</twBEL><twBEL>counter_vga</twBEL></twPathDel><twLogDel>0.413</twLogDel><twRouteDel>0.025</twRouteDel><twTotDel>0.438</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="10.000">clk_BUFGP</twDestClk><twPctLog>94.3</twPctLog><twPctRoute>5.7</twPctRoute></twDetPath></twConstPath></twPathRpt><twPathRptBanner iPaths="1" iCriticalPaths="0" sType="EndPoint">Paths for end point joy/counter_joy_31 (SLICE_X0Y32.D6), 1 path
</twPathRptBanner><twPathRpt anchorID="28"><twConstPath anchorID="29" twDataPathType="twDataPathMinDelay" constType="period"><twSlack>0.461</twSlack><twSrc BELType="FF">joy/counter_joy_31</twSrc><twDest BELType="FF">joy/counter_joy_31</twDest><twTotPathDel>0.461</twTotPathDel><twClkSkew>0.000</twClkSkew><twDelConst>0.000</twDelConst><twClkUncert fSysJit="0.000" fInputJit="0.000" fDCMJit="0.000" fPhaseErr="0.000" sEqu="">0.000</twClkUncert><twDetPath maxSiteLen="15" twPathCritProcCorner=" at Fast Process Corner"><twSrc BELType='FF'>joy/counter_joy_31</twSrc><twDest BELType='FF'>joy/counter_joy_31</twDest><twLogLvls>1</twLogLvls><twSrcSite>SLICE_X0Y32.CLK</twSrcSite><twSrcClk twEdge ="twRising" twArriveTime ="10.000">clk_BUFGP</twSrcClk><twPathDel><twSite>SLICE_X0Y32.DQ</twSite><twDelType>Tcko</twDelType><twDelInfo twEdge="twFalling">0.200</twDelInfo><twComp>joy/counter_joy<31></twComp><twBEL>joy/counter_joy_31</twBEL></twPathDel><twPathDel><twSite>SLICE_X0Y32.D6</twSite><twDelType>net</twDelType><twFanCnt>2</twFanCnt><twDelInfo twEdge="twFalling">0.024</twDelInfo><twComp>joy/counter_joy<31></twComp></twPathDel><twPathDel twHoldTime="TRUE"><twSite>SLICE_X0Y32.CLK</twSite><twDelType>Tah</twDelType><twDelInfo twEdge="twFalling">0.237</twDelInfo><twComp>joy/counter_joy<31></twComp><twBEL>joy/counter_joy<31>_rt</twBEL><twBEL>joy/Mcount_counter_joy_xor<31></twBEL><twBEL>joy/counter_joy_31</twBEL></twPathDel><twLogDel>0.437</twLogDel><twRouteDel>0.024</twRouteDel><twTotDel>0.461</twTotDel><twDestClk twEdge ="twRising" twArriveTime ="10.000">clk_BUFGP</twDestClk><twPctLog>94.8</twPctLog><twPctRoute>5.2</twPctRoute></twDetPath></twConstPath></twPathRpt><twPinLimitRpt anchorID="30"><twPinLimitBanner>Component Switching Limit Checks: TS_sys_clk_pin = PERIOD TIMEGRP "sys_clk_pin" 100 MHz HIGH 50%;</twPinLimitBanner><twPinLimit anchorID="31" type="MINPERIOD" name="Trper_CLKA(Fmax)" slack="6.430" period="10.000" constraintValue="10.000" deviceLimit="3.570" freqLimit="280.112" physResource="pixel_map/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_init.ram/SDP.SIMPLE_PRIM9.ram/CLKAWRCLK" logResource="pixel_map/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_init.ram/SDP.SIMPLE_PRIM9.ram/CLKAWRCLK" locationPin="RAMB8_X0Y27.CLKAWRCLK" clockNet="clk_BUFGP"/><twPinLimit anchorID="32" type="MINPERIOD" name="Trper_CLKB(Fmax)" slack="6.430" period="10.000" constraintValue="10.000" deviceLimit="3.570" freqLimit="280.112" physResource="pixel_map/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_init.ram/SDP.SIMPLE_PRIM9.ram/CLKBRDCLK" logResource="pixel_map/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[3].ram.r/s6_init.ram/SDP.SIMPLE_PRIM9.ram/CLKBRDCLK" locationPin="RAMB8_X0Y27.CLKBRDCLK" clockNet="clk_BUFGP"/><twPinLimit anchorID="33" type="MINPERIOD" name="Trper_CLKA(Fmax)" slack="6.430" period="10.000" constraintValue="10.000" deviceLimit="3.570" freqLimit="280.112" physResource="pixel_map/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/s6_init.ram/SDP.SIMPLE_PRIM9.ram/CLKAWRCLK" logResource="pixel_map/U0/xst_blk_mem_generator/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[4].ram.r/s6_init.ram/SDP.SIMPLE_PRIM9.ram/CLKAWRCLK" locationPin="RAMB8_X0Y8.CLKAWRCLK" clockNet="clk_BUFGP"/></twPinLimitRpt></twConst><twUnmetConstCnt anchorID="34">1</twUnmetConstCnt><twDataSheet anchorID="35" twNameLen="15"><twClk2SUList anchorID="36" twDestWidth="3"><twDest>clk</twDest><twClk2SU><twSrc>clk</twSrc><twRiseRise>13.189</twRiseRise></twClk2SU></twClk2SUList><twOffsetTables></twOffsetTables></twDataSheet></twVerboseRpt></twBody><twSum anchorID="37"><twErrCnt>31</twErrCnt><twScore>63434</twScore><twSetupScore>63434</twSetupScore><twHoldScore>0</twHoldScore><twConstCov><twPathCnt>1558639</twPathCnt><twNetCnt>0</twNetCnt><twConnCnt>2236</twConnCnt></twConstCov><twStats anchorID="38"><twMinPer>13.189</twMinPer><twFootnote number="1" /><twMaxFreq>75.821</twMaxFreq></twStats></twSum><twFoot><twFootnoteExplanation number="1" text="The minimum period statistic assumes all single cycle delays."></twFootnoteExplanation><twTimestamp>Thu Mar 10 16:13:26 2016 </twTimestamp></twFoot><twClientInfo anchorID="39"><twClientName>Trace</twClientName><twAttrList><twAttrListItem><twName>Trace Settings</twName><twValue>
Peak Memory Usage: 236 MB
</twValue></twAttrListItem></twAttrList></twClientInfo></twReport>