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Hi,
the .v file of std cell is not compatible with synopsys VCS simulation.
some functions of cells are wrong.
some connection definitions are strange. like, **_Delay, CLK_Delay. those unused signals are connected to the primitives.
Also, when defining FUNCTIONAL, the VCS shows the following error msg. Error-[SE] Syntax error Following verilog source has syntax error : "/home/mzhang/Code/MIRISEVtry/sim_scanchian_nosram/run/../install/rtl/sky130_lib/stdcells.v", 51850: token is 'module' module sky130_fd_sc_hd__lpflow_inputiso0n (
The text was updated successfully, but these errors were encountered:
Hi,
the .v file of std cell is not compatible with synopsys VCS simulation.
some functions of cells are wrong.
some connection definitions are strange. like, **_Delay, CLK_Delay. those unused signals are connected to the primitives.
Also, when defining FUNCTIONAL, the VCS shows the following error msg.
Error-[SE] Syntax error
Following verilog source has syntax error :
"/home/mzhang/Code/MIRISEVtry/sim_scanchian_nosram/run/../install/rtl/sky130_lib/stdcells.v",
51850: token is 'module'
module sky130_fd_sc_hd__lpflow_inputiso0n (
The text was updated successfully, but these errors were encountered: